xref: /linux/arch/arm64/boot/dts/apple/t600x-common.dtsi (revision d32c1530)

// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
 * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC
 *
 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
 *
 * Copyright The Asahi Linux Contributors
 */

/ {
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_e00>;
				};
				core1 {
					cpu = <&cpu_e01>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_p00>;
				};
				core1 {
					cpu = <&cpu_p01>;
				};
				core2 {
					cpu = <&cpu_p02>;
				};
				core3 {
					cpu = <&cpu_p03>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&cpu_p10>;
				};
				core1 {
					cpu = <&cpu_p11>;
				};
				core2 {
					cpu = <&cpu_p12>;
				};
				core3 {
					cpu = <&cpu_p13>;
				};
			};
		};

		cpu_e00: cpu@0 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
			operating-points-v2 = <&icestorm_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
		};

		cpu_e01: cpu@1 {
			compatible = "apple,icestorm";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_0>;
			i-cache-size = <0x20000>;
			d-cache-size = <0x10000>;
			operating-points-v2 = <&icestorm_opp>;
			capacity-dmips-mhz = <714>;
			performance-domains = <&cpufreq_e>;
		};

		cpu_p00: cpu@10100 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10100>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p01: cpu@10101 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10101>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p02: cpu@10102 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10102>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p03: cpu@10103 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10103>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_1>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p0>;
		};

		cpu_p10: cpu@10200 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10200>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		cpu_p11: cpu@10201 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10201>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		cpu_p12: cpu@10202 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10202>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		cpu_p13: cpu@10203 {
			compatible = "apple,firestorm";
			device_type = "cpu";
			reg = <0x0 0x10203>;
			enable-method = "spin-table";
			cpu-release-addr = <0 0>; /* To be filled by loader */
			next-level-cache = <&l2_cache_2>;
			i-cache-size = <0x30000>;
			d-cache-size = <0x20000>;
			operating-points-v2 = <&firestorm_opp>;
			capacity-dmips-mhz = <1024>;
			performance-domains = <&cpufreq_p1>;
		};

		l2_cache_0: l2-cache-0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0x400000>;
		};

		l2_cache_1: l2-cache-1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};

		l2_cache_2: l2-cache-2 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
			cache-size = <0xc00000>;
		};
	};

	icestorm_opp: opp-table-0 {
		compatible = "operating-points-v2";

		opp01 {
			opp-hz = /bits/ 64 <600000000>;
			opp-level = <1>;
			clock-latency-ns = <7500>;
		};
		opp02 {
			opp-hz = /bits/ 64 <972000000>;
			opp-level = <2>;
			clock-latency-ns = <23000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1332000000>;
			opp-level = <3>;
			clock-latency-ns = <29000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1704000000>;
			opp-level = <4>;
			clock-latency-ns = <40000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <2064000000>;
			opp-level = <5>;
			clock-latency-ns = <50000>;
		};
	};

	firestorm_opp: opp-table-1 {
		compatible = "operating-points-v2";

		opp01 {
			opp-hz = /bits/ 64 <600000000>;
			opp-level = <1>;
			clock-latency-ns = <8000>;
		};
		opp02 {
			opp-hz = /bits/ 64 <828000000>;
			opp-level = <2>;
			clock-latency-ns = <18000>;
		};
		opp03 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-level = <3>;
			clock-latency-ns = <19000>;
		};
		opp04 {
			opp-hz = /bits/ 64 <1296000000>;
			opp-level = <4>;
			clock-latency-ns = <23000>;
		};
		opp05 {
			opp-hz = /bits/ 64 <1524000000>;
			opp-level = <5>;
			clock-latency-ns = <24000>;
		};
		opp06 {
			opp-hz = /bits/ 64 <1752000000>;
			opp-level = <6>;
			clock-latency-ns = <28000>;
		};
		opp07 {
			opp-hz = /bits/ 64 <1980000000>;
			opp-level = <7>;
			clock-latency-ns = <31000>;
		};
		opp08 {
			opp-hz = /bits/ 64 <2208000000>;
			opp-level = <8>;
			clock-latency-ns = <45000>;
		};
		opp09 {
			opp-hz = /bits/ 64 <2448000000>;
			opp-level = <9>;
			clock-latency-ns = <49000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <2676000000>;
			opp-level = <10>;
			clock-latency-ns = <53000>;
		};
		opp11 {
			opp-hz = /bits/ 64 <2904000000>;
			opp-level = <11>;
			clock-latency-ns = <56000>;
		};
		opp12 {
			opp-hz = /bits/ 64 <3036000000>;
			opp-level = <12>;
			clock-latency-ns = <56000>;
		};
		/* Not available until CPU deep sleep is implemented
		opp13 {
			opp-hz = /bits/ 64 <3132000000>;
			opp-level = <13>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		opp14 {
			opp-hz = /bits/ 64 <3168000000>;
			opp-level = <14>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		opp15 {
			opp-hz = /bits/ 64 <3228000000>;
			opp-level = <15>;
			clock-latency-ns = <56000>;
			turbo-mode;
		};
		*/
	};

	pmu-e {
		compatible = "apple,icestorm-pmu";
		interrupt-parent = <&aic>;
		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu-p {
		compatible = "apple,firestorm-pmu";
		interrupt-parent = <&aic>;
		interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&aic>;
		interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
		interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
			     <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
	};

	clkref: clock-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "clkref";
	};

	/*
	 * This is a fabulated representation of the input clock
	 * to NCO since we don't know the true clock tree.
	 */
	nco_clkref: clock-ref-nco {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "nco_ref";
	};
};