1// SPDX-License-Identifier: GPL-2.0 2#include "juno-clocks.dtsi" 3#include "juno-motherboard.dtsi" 4 5/ { 6 /* 7 * Devices shared by all Juno boards 8 */ 9 dma-ranges = <0 0 0 0 0x100 0>; 10 11 memtimer: timer@2a810000 { 12 compatible = "arm,armv7-timer-mem"; 13 reg = <0x0 0x2a810000 0x0 0x10000>; 14 clock-frequency = <50000000>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 status = "disabled"; 19 frame@2a830000 { 20 frame-number = <1>; 21 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 22 reg = <0x0 0x2a830000 0x0 0x10000>; 23 }; 24 }; 25 26 mailbox: mhu@2b1f0000 { 27 compatible = "arm,mhu", "arm,primecell"; 28 reg = <0x0 0x2b1f0000 0x0 0x1000>; 29 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 31 interrupt-names = "mhu_lpri_rx", 32 "mhu_hpri_rx"; 33 #mbox-cells = <1>; 34 clocks = <&soc_refclk100mhz>; 35 clock-names = "apb_pclk"; 36 }; 37 38 smmu_pcie: iommu@2b500000 { 39 compatible = "arm,mmu-401", "arm,smmu-v1"; 40 reg = <0x0 0x2b500000 0x0 0x10000>; 41 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 43 #iommu-cells = <1>; 44 #global-interrupts = <1>; 45 dma-coherent; 46 status = "disabled"; 47 }; 48 49 smmu_etr: iommu@2b600000 { 50 compatible = "arm,mmu-401", "arm,smmu-v1"; 51 reg = <0x0 0x2b600000 0x0 0x10000>; 52 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 54 #iommu-cells = <1>; 55 #global-interrupts = <1>; 56 dma-coherent; 57 power-domains = <&scpi_devpd 0>; 58 }; 59 60 gic: interrupt-controller@2c010000 { 61 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 62 reg = <0x0 0x2c010000 0 0x1000>, 63 <0x0 0x2c02f000 0 0x2000>, 64 <0x0 0x2c04f000 0 0x2000>, 65 <0x0 0x2c06f000 0 0x2000>; 66 #address-cells = <2>; 67 #interrupt-cells = <3>; 68 #size-cells = <2>; 69 interrupt-controller; 70 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 71 ranges = <0 0 0 0x2c1c0000 0 0x40000>; 72 73 v2m_0: v2m@0 { 74 compatible = "arm,gic-v2m-frame"; 75 msi-controller; 76 reg = <0 0 0 0x10000>; 77 }; 78 79 v2m@10000 { 80 compatible = "arm,gic-v2m-frame"; 81 msi-controller; 82 reg = <0 0x10000 0 0x10000>; 83 }; 84 85 v2m@20000 { 86 compatible = "arm,gic-v2m-frame"; 87 msi-controller; 88 reg = <0 0x20000 0 0x10000>; 89 }; 90 91 v2m@30000 { 92 compatible = "arm,gic-v2m-frame"; 93 msi-controller; 94 reg = <0 0x30000 0 0x10000>; 95 }; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 104 }; 105 106 /* 107 * Juno TRMs specify the size for these coresight components as 64K. 108 * The actual size is just 4K though 64K is reserved. Access to the 109 * unmapped reserved region results in a DECERR response. 110 */ 111 etf@20010000 { /* etf0 */ 112 compatible = "arm,coresight-tmc", "arm,primecell"; 113 reg = <0 0x20010000 0 0x1000>; 114 115 clocks = <&soc_smc50mhz>; 116 clock-names = "apb_pclk"; 117 power-domains = <&scpi_devpd 0>; 118 119 in-ports { 120 port { 121 etf0_in_port: endpoint { 122 remote-endpoint = <&main_funnel_out_port>; 123 }; 124 }; 125 }; 126 127 out-ports { 128 port { 129 etf0_out_port: endpoint { 130 }; 131 }; 132 }; 133 }; 134 135 tpiu@20030000 { 136 compatible = "arm,coresight-tpiu", "arm,primecell"; 137 reg = <0 0x20030000 0 0x1000>; 138 139 clocks = <&soc_smc50mhz>; 140 clock-names = "apb_pclk"; 141 power-domains = <&scpi_devpd 0>; 142 in-ports { 143 port { 144 tpiu_in_port: endpoint { 145 remote-endpoint = <&replicator_out_port0>; 146 }; 147 }; 148 }; 149 }; 150 151 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 152 main_funnel: funnel@20040000 { 153 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 154 reg = <0 0x20040000 0 0x1000>; 155 156 clocks = <&soc_smc50mhz>; 157 clock-names = "apb_pclk"; 158 power-domains = <&scpi_devpd 0>; 159 160 out-ports { 161 port { 162 main_funnel_out_port: endpoint { 163 remote-endpoint = <&etf0_in_port>; 164 }; 165 }; 166 }; 167 168 main_funnel_in_ports: in-ports { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 port@0 { 173 reg = <0>; 174 main_funnel_in_port0: endpoint { 175 remote-endpoint = <&cluster0_funnel_out_port>; 176 }; 177 }; 178 179 port@1 { 180 reg = <1>; 181 main_funnel_in_port1: endpoint { 182 remote-endpoint = <&cluster1_funnel_out_port>; 183 }; 184 }; 185 }; 186 }; 187 188 etr@20070000 { 189 compatible = "arm,coresight-tmc", "arm,primecell"; 190 reg = <0 0x20070000 0 0x1000>; 191 iommus = <&smmu_etr 0>; 192 193 clocks = <&soc_smc50mhz>; 194 clock-names = "apb_pclk"; 195 power-domains = <&scpi_devpd 0>; 196 arm,scatter-gather; 197 in-ports { 198 port { 199 etr_in_port: endpoint { 200 remote-endpoint = <&replicator_out_port1>; 201 }; 202 }; 203 }; 204 }; 205 206 stm@20100000 { 207 compatible = "arm,coresight-stm", "arm,primecell"; 208 reg = <0 0x20100000 0 0x1000>, 209 <0 0x28000000 0 0x1000000>; 210 reg-names = "stm-base", "stm-stimulus-base"; 211 212 clocks = <&soc_smc50mhz>; 213 clock-names = "apb_pclk"; 214 power-domains = <&scpi_devpd 0>; 215 out-ports { 216 port { 217 stm_out_port: endpoint { 218 }; 219 }; 220 }; 221 }; 222 223 replicator@20120000 { 224 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 225 reg = <0 0x20120000 0 0x1000>; 226 227 clocks = <&soc_smc50mhz>; 228 clock-names = "apb_pclk"; 229 power-domains = <&scpi_devpd 0>; 230 231 out-ports { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 /* replicator output ports */ 236 port@0 { 237 reg = <0>; 238 replicator_out_port0: endpoint { 239 remote-endpoint = <&tpiu_in_port>; 240 }; 241 }; 242 243 port@1 { 244 reg = <1>; 245 replicator_out_port1: endpoint { 246 remote-endpoint = <&etr_in_port>; 247 }; 248 }; 249 }; 250 in-ports { 251 port { 252 replicator_in_port0: endpoint { 253 }; 254 }; 255 }; 256 }; 257 258 cpu_debug0: cpu-debug@22010000 { 259 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 260 reg = <0x0 0x22010000 0x0 0x1000>; 261 262 clocks = <&soc_smc50mhz>; 263 clock-names = "apb_pclk"; 264 power-domains = <&scpi_devpd 0>; 265 }; 266 267 etm0: etm@22040000 { 268 compatible = "arm,coresight-etm4x", "arm,primecell"; 269 reg = <0 0x22040000 0 0x1000>; 270 271 clocks = <&soc_smc50mhz>; 272 clock-names = "apb_pclk"; 273 power-domains = <&scpi_devpd 0>; 274 out-ports { 275 port { 276 cluster0_etm0_out_port: endpoint { 277 remote-endpoint = <&cluster0_funnel_in_port0>; 278 }; 279 }; 280 }; 281 }; 282 283 funnel@220c0000 { /* cluster0 funnel */ 284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 285 reg = <0 0x220c0000 0 0x1000>; 286 287 clocks = <&soc_smc50mhz>; 288 clock-names = "apb_pclk"; 289 power-domains = <&scpi_devpd 0>; 290 out-ports { 291 port { 292 cluster0_funnel_out_port: endpoint { 293 remote-endpoint = <&main_funnel_in_port0>; 294 }; 295 }; 296 }; 297 298 in-ports { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 302 port@0 { 303 reg = <0>; 304 cluster0_funnel_in_port0: endpoint { 305 remote-endpoint = <&cluster0_etm0_out_port>; 306 }; 307 }; 308 309 port@1 { 310 reg = <1>; 311 cluster0_funnel_in_port1: endpoint { 312 remote-endpoint = <&cluster0_etm1_out_port>; 313 }; 314 }; 315 }; 316 }; 317 318 cpu_debug1: cpu-debug@22110000 { 319 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 320 reg = <0x0 0x22110000 0x0 0x1000>; 321 322 clocks = <&soc_smc50mhz>; 323 clock-names = "apb_pclk"; 324 power-domains = <&scpi_devpd 0>; 325 }; 326 327 etm1: etm@22140000 { 328 compatible = "arm,coresight-etm4x", "arm,primecell"; 329 reg = <0 0x22140000 0 0x1000>; 330 331 clocks = <&soc_smc50mhz>; 332 clock-names = "apb_pclk"; 333 power-domains = <&scpi_devpd 0>; 334 out-ports { 335 port { 336 cluster0_etm1_out_port: endpoint { 337 remote-endpoint = <&cluster0_funnel_in_port1>; 338 }; 339 }; 340 }; 341 }; 342 343 cpu_debug2: cpu-debug@23010000 { 344 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 345 reg = <0x0 0x23010000 0x0 0x1000>; 346 347 clocks = <&soc_smc50mhz>; 348 clock-names = "apb_pclk"; 349 power-domains = <&scpi_devpd 0>; 350 }; 351 352 etm2: etm@23040000 { 353 compatible = "arm,coresight-etm4x", "arm,primecell"; 354 reg = <0 0x23040000 0 0x1000>; 355 356 clocks = <&soc_smc50mhz>; 357 clock-names = "apb_pclk"; 358 power-domains = <&scpi_devpd 0>; 359 out-ports { 360 port { 361 cluster1_etm0_out_port: endpoint { 362 remote-endpoint = <&cluster1_funnel_in_port0>; 363 }; 364 }; 365 }; 366 }; 367 368 funnel@230c0000 { /* cluster1 funnel */ 369 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 370 reg = <0 0x230c0000 0 0x1000>; 371 372 clocks = <&soc_smc50mhz>; 373 clock-names = "apb_pclk"; 374 power-domains = <&scpi_devpd 0>; 375 out-ports { 376 port { 377 cluster1_funnel_out_port: endpoint { 378 remote-endpoint = <&main_funnel_in_port1>; 379 }; 380 }; 381 }; 382 383 in-ports { 384 #address-cells = <1>; 385 #size-cells = <0>; 386 387 port@0 { 388 reg = <0>; 389 cluster1_funnel_in_port0: endpoint { 390 remote-endpoint = <&cluster1_etm0_out_port>; 391 }; 392 }; 393 394 port@1 { 395 reg = <1>; 396 cluster1_funnel_in_port1: endpoint { 397 remote-endpoint = <&cluster1_etm1_out_port>; 398 }; 399 }; 400 port@2 { 401 reg = <2>; 402 cluster1_funnel_in_port2: endpoint { 403 remote-endpoint = <&cluster1_etm2_out_port>; 404 }; 405 }; 406 port@3 { 407 reg = <3>; 408 cluster1_funnel_in_port3: endpoint { 409 remote-endpoint = <&cluster1_etm3_out_port>; 410 }; 411 }; 412 }; 413 }; 414 415 cpu_debug3: cpu-debug@23110000 { 416 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 417 reg = <0x0 0x23110000 0x0 0x1000>; 418 419 clocks = <&soc_smc50mhz>; 420 clock-names = "apb_pclk"; 421 power-domains = <&scpi_devpd 0>; 422 }; 423 424 etm3: etm@23140000 { 425 compatible = "arm,coresight-etm4x", "arm,primecell"; 426 reg = <0 0x23140000 0 0x1000>; 427 428 clocks = <&soc_smc50mhz>; 429 clock-names = "apb_pclk"; 430 power-domains = <&scpi_devpd 0>; 431 out-ports { 432 port { 433 cluster1_etm1_out_port: endpoint { 434 remote-endpoint = <&cluster1_funnel_in_port1>; 435 }; 436 }; 437 }; 438 }; 439 440 cpu_debug4: cpu-debug@23210000 { 441 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 442 reg = <0x0 0x23210000 0x0 0x1000>; 443 444 clocks = <&soc_smc50mhz>; 445 clock-names = "apb_pclk"; 446 power-domains = <&scpi_devpd 0>; 447 }; 448 449 etm4: etm@23240000 { 450 compatible = "arm,coresight-etm4x", "arm,primecell"; 451 reg = <0 0x23240000 0 0x1000>; 452 453 clocks = <&soc_smc50mhz>; 454 clock-names = "apb_pclk"; 455 power-domains = <&scpi_devpd 0>; 456 out-ports { 457 port { 458 cluster1_etm2_out_port: endpoint { 459 remote-endpoint = <&cluster1_funnel_in_port2>; 460 }; 461 }; 462 }; 463 }; 464 465 cpu_debug5: cpu-debug@23310000 { 466 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 467 reg = <0x0 0x23310000 0x0 0x1000>; 468 469 clocks = <&soc_smc50mhz>; 470 clock-names = "apb_pclk"; 471 power-domains = <&scpi_devpd 0>; 472 }; 473 474 etm5: etm@23340000 { 475 compatible = "arm,coresight-etm4x", "arm,primecell"; 476 reg = <0 0x23340000 0 0x1000>; 477 478 clocks = <&soc_smc50mhz>; 479 clock-names = "apb_pclk"; 480 power-domains = <&scpi_devpd 0>; 481 out-ports { 482 port { 483 cluster1_etm3_out_port: endpoint { 484 remote-endpoint = <&cluster1_funnel_in_port3>; 485 }; 486 }; 487 }; 488 }; 489 490 sram: sram@2e000000 { 491 compatible = "arm,juno-sram-ns", "mmio-sram"; 492 reg = <0x0 0x2e000000 0x0 0x8000>; 493 494 #address-cells = <1>; 495 #size-cells = <1>; 496 ranges = <0 0x0 0x2e000000 0x8000>; 497 498 cpu_scp_lpri: scp-shmem@0 { 499 compatible = "arm,juno-scp-shmem"; 500 reg = <0x0 0x200>; 501 }; 502 503 cpu_scp_hpri: scp-shmem@200 { 504 compatible = "arm,juno-scp-shmem"; 505 reg = <0x200 0x200>; 506 }; 507 }; 508 509 pcie_ctlr: pcie@40000000 { 510 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 511 device_type = "pci"; 512 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 513 bus-range = <0 255>; 514 linux,pci-domain = <0>; 515 #address-cells = <3>; 516 #size-cells = <2>; 517 dma-coherent; 518 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 519 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 520 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 521 #interrupt-cells = <1>; 522 interrupt-map-mask = <0 0 0 7>; 523 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 524 <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 525 <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 526 <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 527 msi-parent = <&v2m_0>; 528 status = "disabled"; 529 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 530 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 531 }; 532 533 scpi { 534 compatible = "arm,scpi"; 535 mboxes = <&mailbox 1>; 536 shmem = <&cpu_scp_hpri>; 537 538 clocks { 539 compatible = "arm,scpi-clocks"; 540 541 scpi_dvfs: scpi-dvfs { 542 compatible = "arm,scpi-dvfs-clocks"; 543 #clock-cells = <1>; 544 clock-indices = <0>, <1>, <2>; 545 clock-output-names = "atlclk", "aplclk","gpuclk"; 546 }; 547 scpi_clk: scpi-clk { 548 compatible = "arm,scpi-variable-clocks"; 549 #clock-cells = <1>; 550 clock-indices = <3>; 551 clock-output-names = "pxlclk"; 552 }; 553 }; 554 555 scpi_devpd: scpi-power-domains { 556 compatible = "arm,scpi-power-domains"; 557 num-domains = <2>; 558 #power-domain-cells = <1>; 559 }; 560 561 scpi_sensors0: sensors { 562 compatible = "arm,scpi-sensors"; 563 #thermal-sensor-cells = <1>; 564 }; 565 }; 566 567 thermal-zones { 568 pmic { 569 polling-delay = <1000>; 570 polling-delay-passive = <100>; 571 thermal-sensors = <&scpi_sensors0 0>; 572 }; 573 574 soc { 575 polling-delay = <1000>; 576 polling-delay-passive = <100>; 577 thermal-sensors = <&scpi_sensors0 3>; 578 }; 579 580 big_cluster_thermal_zone: big-cluster { 581 polling-delay = <1000>; 582 polling-delay-passive = <100>; 583 thermal-sensors = <&scpi_sensors0 21>; 584 status = "disabled"; 585 }; 586 587 little_cluster_thermal_zone: little-cluster { 588 polling-delay = <1000>; 589 polling-delay-passive = <100>; 590 thermal-sensors = <&scpi_sensors0 22>; 591 status = "disabled"; 592 }; 593 594 gpu0_thermal_zone: gpu0 { 595 polling-delay = <1000>; 596 polling-delay-passive = <100>; 597 thermal-sensors = <&scpi_sensors0 23>; 598 status = "disabled"; 599 }; 600 601 gpu1_thermal_zone: gpu1 { 602 polling-delay = <1000>; 603 polling-delay-passive = <100>; 604 thermal-sensors = <&scpi_sensors0 24>; 605 status = "disabled"; 606 }; 607 }; 608 609 smmu_dma: iommu@7fb00000 { 610 compatible = "arm,mmu-401", "arm,smmu-v1"; 611 reg = <0x0 0x7fb00000 0x0 0x10000>; 612 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 614 #iommu-cells = <1>; 615 #global-interrupts = <1>; 616 dma-coherent; 617 status = "disabled"; 618 }; 619 620 smmu_hdlcd1: iommu@7fb10000 { 621 compatible = "arm,mmu-401", "arm,smmu-v1"; 622 reg = <0x0 0x7fb10000 0x0 0x10000>; 623 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 625 #iommu-cells = <1>; 626 #global-interrupts = <1>; 627 }; 628 629 smmu_hdlcd0: iommu@7fb20000 { 630 compatible = "arm,mmu-401", "arm,smmu-v1"; 631 reg = <0x0 0x7fb20000 0x0 0x10000>; 632 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 634 #iommu-cells = <1>; 635 #global-interrupts = <1>; 636 }; 637 638 smmu_usb: iommu@7fb30000 { 639 compatible = "arm,mmu-401", "arm,smmu-v1"; 640 reg = <0x0 0x7fb30000 0x0 0x10000>; 641 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 643 #iommu-cells = <1>; 644 #global-interrupts = <1>; 645 dma-coherent; 646 }; 647 648 dma@7ff00000 { 649 compatible = "arm,pl330", "arm,primecell"; 650 reg = <0x0 0x7ff00000 0 0x1000>; 651 #dma-cells = <1>; 652 #dma-channels = <8>; 653 #dma-requests = <32>; 654 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 663 iommus = <&smmu_dma 0>, 664 <&smmu_dma 1>, 665 <&smmu_dma 2>, 666 <&smmu_dma 3>, 667 <&smmu_dma 4>, 668 <&smmu_dma 5>, 669 <&smmu_dma 6>, 670 <&smmu_dma 7>, 671 <&smmu_dma 8>; 672 clocks = <&soc_faxiclk>; 673 clock-names = "apb_pclk"; 674 }; 675 676 hdlcd@7ff50000 { 677 compatible = "arm,hdlcd"; 678 reg = <0 0x7ff50000 0 0x1000>; 679 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 680 iommus = <&smmu_hdlcd1 0>; 681 clocks = <&scpi_clk 3>; 682 clock-names = "pxlclk"; 683 684 port { 685 hdlcd1_output: endpoint { 686 remote-endpoint = <&tda998x_1_input>; 687 }; 688 }; 689 }; 690 691 hdlcd@7ff60000 { 692 compatible = "arm,hdlcd"; 693 reg = <0 0x7ff60000 0 0x1000>; 694 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 695 iommus = <&smmu_hdlcd0 0>; 696 clocks = <&scpi_clk 3>; 697 clock-names = "pxlclk"; 698 699 port { 700 hdlcd0_output: endpoint { 701 remote-endpoint = <&tda998x_0_input>; 702 }; 703 }; 704 }; 705 706 soc_uart0: uart@7ff80000 { 707 compatible = "arm,pl011", "arm,primecell"; 708 reg = <0x0 0x7ff80000 0x0 0x1000>; 709 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 711 clock-names = "uartclk", "apb_pclk"; 712 }; 713 714 i2c@7ffa0000 { 715 compatible = "snps,designware-i2c"; 716 reg = <0x0 0x7ffa0000 0x0 0x1000>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 720 clock-frequency = <400000>; 721 i2c-sda-hold-time-ns = <500>; 722 clocks = <&soc_smc50mhz>; 723 724 hdmi-transmitter@70 { 725 compatible = "nxp,tda998x"; 726 reg = <0x70>; 727 port { 728 tda998x_0_input: endpoint { 729 remote-endpoint = <&hdlcd0_output>; 730 }; 731 }; 732 }; 733 734 hdmi-transmitter@71 { 735 compatible = "nxp,tda998x"; 736 reg = <0x71>; 737 port { 738 tda998x_1_input: endpoint { 739 remote-endpoint = <&hdlcd1_output>; 740 }; 741 }; 742 }; 743 }; 744 745 ohci@7ffb0000 { 746 compatible = "generic-ohci"; 747 reg = <0x0 0x7ffb0000 0x0 0x10000>; 748 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 749 iommus = <&smmu_usb 0>; 750 clocks = <&soc_usb48mhz>; 751 }; 752 753 ehci@7ffc0000 { 754 compatible = "generic-ehci"; 755 reg = <0x0 0x7ffc0000 0x0 0x10000>; 756 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 757 iommus = <&smmu_usb 0>; 758 clocks = <&soc_usb48mhz>; 759 }; 760 761 memory-controller@7ffd0000 { 762 compatible = "arm,pl354", "arm,primecell"; 763 reg = <0 0x7ffd0000 0 0x1000>; 764 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&soc_smc50mhz>; 767 clock-names = "apb_pclk"; 768 }; 769 770 memory@80000000 { 771 device_type = "memory"; 772 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 773 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 774 <0x00000008 0x80000000 0x1 0x80000000>; 775 }; 776 777 smb@8000000 { 778 compatible = "simple-bus"; 779 #address-cells = <2>; 780 #size-cells = <1>; 781 ranges = <0 0 0 0x08000000 0x04000000>, 782 <1 0 0 0x14000000 0x04000000>, 783 <2 0 0 0x18000000 0x04000000>, 784 <3 0 0 0x1c000000 0x04000000>, 785 <4 0 0 0x0c000000 0x04000000>, 786 <5 0 0 0x10000000 0x04000000>; 787 788 #interrupt-cells = <1>; 789 interrupt-map-mask = <0 0 15>; 790 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 791 <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 792 <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 793 <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 794 <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 795 <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 796 <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 797 <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 798 <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 799 <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 800 <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 801 <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 802 <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 803 }; 804 805 site2: tlx@60000000 { 806 compatible = "simple-bus"; 807 #address-cells = <1>; 808 #size-cells = <1>; 809 ranges = <0 0 0x60000000 0x10000000>; 810 #interrupt-cells = <1>; 811 interrupt-map-mask = <0 0>; 812 interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 813 }; 814}; 815