1/* 2 * ARM Juno Platform motherboard peripherals 3 * 4 * Copyright (c) 2013-2014 ARM Ltd 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 * 8 */ 9 10/ { 11 smb@8000000 { 12 mb_clk24mhz: clk24mhz { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <24000000>; 16 clock-output-names = "juno_mb:clk24mhz"; 17 }; 18 19 mb_clk25mhz: clk25mhz { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <25000000>; 23 clock-output-names = "juno_mb:clk25mhz"; 24 }; 25 26 v2m_refclk1mhz: refclk1mhz { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <1000000>; 30 clock-output-names = "juno_mb:refclk1mhz"; 31 }; 32 33 v2m_refclk32khz: refclk32khz { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32768>; 37 clock-output-names = "juno_mb:refclk32khz"; 38 }; 39 40 motherboard { 41 compatible = "arm,vexpress,v2p-p1", "simple-bus"; 42 #address-cells = <2>; /* SMB chipselect number and offset */ 43 #size-cells = <1>; 44 #interrupt-cells = <1>; 45 ranges; 46 model = "V2M-Juno"; 47 arm,hbi = <0x252>; 48 arm,vexpress,site = <0>; 49 arm,v2m-memory-map = "rs1"; 50 51 mb_fixed_3v3: mcc-sb-3v3 { 52 compatible = "regulator-fixed"; 53 regulator-name = "MCC_SB_3V3"; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 regulator-always-on; 57 }; 58 59 gpio-keys { 60 compatible = "gpio-keys"; 61 62 power-button { 63 debounce-interval = <50>; 64 wakeup-source; 65 linux,code = <116>; 66 label = "POWER"; 67 gpios = <&iofpga_gpio0 0 0x4>; 68 }; 69 home-button { 70 debounce-interval = <50>; 71 wakeup-source; 72 linux,code = <102>; 73 label = "HOME"; 74 gpios = <&iofpga_gpio0 1 0x4>; 75 }; 76 rlock-button { 77 debounce-interval = <50>; 78 wakeup-source; 79 linux,code = <152>; 80 label = "RLOCK"; 81 gpios = <&iofpga_gpio0 2 0x4>; 82 }; 83 vol-up-button { 84 debounce-interval = <50>; 85 wakeup-source; 86 linux,code = <115>; 87 label = "VOL+"; 88 gpios = <&iofpga_gpio0 3 0x4>; 89 }; 90 vol-down-button { 91 debounce-interval = <50>; 92 wakeup-source; 93 linux,code = <114>; 94 label = "VOL-"; 95 gpios = <&iofpga_gpio0 4 0x4>; 96 }; 97 nmi-button { 98 debounce-interval = <50>; 99 wakeup-source; 100 linux,code = <99>; 101 label = "NMI"; 102 gpios = <&iofpga_gpio0 5 0x4>; 103 }; 104 }; 105 106 flash@0,00000000 { 107 /* 2 * 32MiB NOR Flash memory mounted on CS0 */ 108 compatible = "arm,vexpress-flash", "cfi-flash"; 109 linux,part-probe = "afs"; 110 reg = <0 0x00000000 0x04000000>; 111 bank-width = <4>; 112 /* 113 * Unfortunately, accessing the flash disturbs 114 * the CPU idle states (suspend) and CPU 115 * hotplug of the platform. For this reason, 116 * flash hardware access is disabled by default. 117 */ 118 status = "disabled"; 119 }; 120 121 ethernet@2,00000000 { 122 compatible = "smsc,lan9118", "smsc,lan9115"; 123 reg = <2 0x00000000 0x10000>; 124 interrupts = <3>; 125 phy-mode = "mii"; 126 reg-io-width = <4>; 127 smsc,irq-active-high; 128 smsc,irq-push-pull; 129 clocks = <&mb_clk25mhz>; 130 vdd33a-supply = <&mb_fixed_3v3>; 131 vddvario-supply = <&mb_fixed_3v3>; 132 }; 133 134 iofpga@3,00000000 { 135 compatible = "simple-bus"; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges = <0 3 0 0x200000>; 139 140 v2m_sysctl: sysctl@20000 { 141 compatible = "arm,sp810", "arm,primecell"; 142 reg = <0x020000 0x1000>; 143 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; 144 clock-names = "refclk", "timclk", "apb_pclk"; 145 #clock-cells = <1>; 146 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 147 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; 148 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; 149 }; 150 151 apbregs@10000 { 152 compatible = "syscon", "simple-mfd"; 153 reg = <0x010000 0x1000>; 154 155 led0 { 156 compatible = "register-bit-led"; 157 offset = <0x08>; 158 mask = <0x01>; 159 label = "vexpress:0"; 160 linux,default-trigger = "heartbeat"; 161 default-state = "on"; 162 }; 163 led1 { 164 compatible = "register-bit-led"; 165 offset = <0x08>; 166 mask = <0x02>; 167 label = "vexpress:1"; 168 linux,default-trigger = "mmc0"; 169 default-state = "off"; 170 }; 171 led2 { 172 compatible = "register-bit-led"; 173 offset = <0x08>; 174 mask = <0x04>; 175 label = "vexpress:2"; 176 linux,default-trigger = "cpu0"; 177 default-state = "off"; 178 }; 179 led3 { 180 compatible = "register-bit-led"; 181 offset = <0x08>; 182 mask = <0x08>; 183 label = "vexpress:3"; 184 linux,default-trigger = "cpu1"; 185 default-state = "off"; 186 }; 187 led4 { 188 compatible = "register-bit-led"; 189 offset = <0x08>; 190 mask = <0x10>; 191 label = "vexpress:4"; 192 linux,default-trigger = "cpu2"; 193 default-state = "off"; 194 }; 195 led5 { 196 compatible = "register-bit-led"; 197 offset = <0x08>; 198 mask = <0x20>; 199 label = "vexpress:5"; 200 linux,default-trigger = "cpu3"; 201 default-state = "off"; 202 }; 203 led6 { 204 compatible = "register-bit-led"; 205 offset = <0x08>; 206 mask = <0x40>; 207 label = "vexpress:6"; 208 default-state = "off"; 209 }; 210 led7 { 211 compatible = "register-bit-led"; 212 offset = <0x08>; 213 mask = <0x80>; 214 label = "vexpress:7"; 215 default-state = "off"; 216 }; 217 }; 218 219 mmci@50000 { 220 compatible = "arm,pl180", "arm,primecell"; 221 reg = <0x050000 0x1000>; 222 interrupts = <5>; 223 /* cd-gpios = <&v2m_mmc_gpios 0 0>; 224 wp-gpios = <&v2m_mmc_gpios 1 0>; */ 225 max-frequency = <12000000>; 226 vmmc-supply = <&mb_fixed_3v3>; 227 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 228 clock-names = "mclk", "apb_pclk"; 229 }; 230 231 kmi@60000 { 232 compatible = "arm,pl050", "arm,primecell"; 233 reg = <0x060000 0x1000>; 234 interrupts = <8>; 235 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 236 clock-names = "KMIREFCLK", "apb_pclk"; 237 }; 238 239 kmi@70000 { 240 compatible = "arm,pl050", "arm,primecell"; 241 reg = <0x070000 0x1000>; 242 interrupts = <8>; 243 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 244 clock-names = "KMIREFCLK", "apb_pclk"; 245 }; 246 247 wdt@f0000 { 248 compatible = "arm,sp805", "arm,primecell"; 249 reg = <0x0f0000 0x10000>; 250 interrupts = <7>; 251 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 252 clock-names = "wdogclk", "apb_pclk"; 253 }; 254 255 v2m_timer01: timer@110000 { 256 compatible = "arm,sp804", "arm,primecell"; 257 reg = <0x110000 0x10000>; 258 interrupts = <9>; 259 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; 260 clock-names = "timclken1", "timclken2", "apb_pclk"; 261 }; 262 263 v2m_timer23: timer@120000 { 264 compatible = "arm,sp804", "arm,primecell"; 265 reg = <0x120000 0x10000>; 266 interrupts = <9>; 267 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; 268 clock-names = "timclken1", "timclken2", "apb_pclk"; 269 }; 270 271 rtc@170000 { 272 compatible = "arm,pl031", "arm,primecell"; 273 reg = <0x170000 0x10000>; 274 interrupts = <0>; 275 clocks = <&soc_smc50mhz>; 276 clock-names = "apb_pclk"; 277 }; 278 279 iofpga_gpio0: gpio@1d0000 { 280 compatible = "arm,pl061", "arm,primecell"; 281 reg = <0x1d0000 0x1000>; 282 interrupts = <6>; 283 clocks = <&soc_smc50mhz>; 284 clock-names = "apb_pclk"; 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 }; 290 }; 291 }; 292 }; 293}; 294