1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3#include <dt-bindings/interrupt-controller/irq.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/phy/phy.h>
6#include <dt-bindings/soc/bcm-pmb.h>
7
8/dts-v1/;
9
10/ {
11	interrupt-parent = <&gic>;
12
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	aliases {
17		serial0 = &uart0;
18	};
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			device_type = "cpu";
30			compatible = "brcm,brahma-b53";
31			reg = <0x0>;
32			enable-method = "spin-table";
33			cpu-release-addr = <0x0 0xfff8>;
34			next-level-cache = <&l2>;
35		};
36
37		cpu1: cpu@1 {
38			device_type = "cpu";
39			compatible = "brcm,brahma-b53";
40			reg = <0x1>;
41			enable-method = "spin-table";
42			cpu-release-addr = <0x0 0xfff8>;
43			next-level-cache = <&l2>;
44		};
45
46		cpu2: cpu@2 {
47			device_type = "cpu";
48			compatible = "brcm,brahma-b53";
49			reg = <0x2>;
50			enable-method = "spin-table";
51			cpu-release-addr = <0x0 0xfff8>;
52			next-level-cache = <&l2>;
53		};
54
55		cpu3: cpu@3 {
56			device_type = "cpu";
57			compatible = "brcm,brahma-b53";
58			reg = <0x3>;
59			enable-method = "spin-table";
60			cpu-release-addr = <0x0 0xfff8>;
61			next-level-cache = <&l2>;
62		};
63
64		l2: l2-cache0 {
65			compatible = "cache";
66			cache-level = <2>;
67		};
68	};
69
70	axi@81000000 {
71		compatible = "simple-bus";
72		#address-cells = <1>;
73		#size-cells = <1>;
74		ranges = <0x00 0x00 0x81000000 0x4000>;
75
76		gic: interrupt-controller@1000 {
77			compatible = "arm,gic-400";
78			#interrupt-cells = <3>;
79			#address-cells = <0>;
80			interrupt-controller;
81			reg = <0x1000 0x1000>,
82			      <0x2000 0x2000>;
83		};
84	};
85
86	timer {
87		compatible = "arm,armv8-timer";
88		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
92	};
93
94	pmu {
95		compatible = "arm,cortex-a53-pmu";
96		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
97			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
98			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
99			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
100		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
101	};
102
103	clocks {
104		periph_clk: periph_clk {
105			compatible = "fixed-clock";
106			#clock-cells = <0>;
107			clock-frequency = <50000000>;
108			clock-output-names = "periph";
109		};
110	};
111
112	soc {
113		compatible = "simple-bus";
114		#address-cells = <1>;
115		#size-cells = <1>;
116		ranges = <0x00 0x00 0x80000000 0x281000>;
117
118		enet: ethernet@2000 {
119			compatible = "brcm,bcm4908-enet";
120			reg = <0x2000 0x1000>;
121
122			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
123				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
124			interrupt-names = "rx", "tx";
125		};
126
127		usb_phy: usb-phy@c200 {
128			compatible = "brcm,bcm4908-usb-phy";
129			reg = <0xc200 0x100>;
130			reg-names = "ctrl";
131			power-domains = <&pmb BCM_PMB_HOST_USB>;
132			dr_mode = "host";
133			brcm,has-xhci;
134			brcm,has-eohci;
135			#phy-cells = <1>;
136			status = "disabled";
137		};
138
139		ehci: usb@c300 {
140			compatible = "generic-ehci";
141			reg = <0xc300 0x100>;
142			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
143			phys = <&usb_phy PHY_TYPE_USB2>;
144			status = "disabled";
145		};
146
147		ohci: usb@c400 {
148			compatible = "generic-ohci";
149			reg = <0xc400 0x100>;
150			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
151			phys = <&usb_phy PHY_TYPE_USB2>;
152			status = "disabled";
153		};
154
155		xhci: usb@d000 {
156			compatible = "generic-xhci";
157			reg = <0xd000 0x8c8>;
158			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
159			phys = <&usb_phy PHY_TYPE_USB3>;
160			status = "disabled";
161		};
162
163		bus@80000 {
164			compatible = "simple-bus";
165			#size-cells = <1>;
166			#address-cells = <1>;
167			ranges = <0 0x80000 0x50000>;
168
169			ethernet-switch@0 {
170				compatible = "brcm,bcm4908-switch";
171				reg = <0x0 0x40000>,
172				      <0x40000 0x110>,
173				      <0x40340 0x30>,
174				      <0x40380 0x30>,
175				      <0x40600 0x34>,
176				      <0x40800 0x208>;
177				reg-names = "core", "reg", "intrl2_0",
178					    "intrl2_1", "fcb", "acb";
179				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
180					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
181				brcm,num-gphy = <5>;
182				brcm,num-rgmii-ports = <2>;
183
184				#address-cells = <1>;
185				#size-cells = <0>;
186
187				ports: ports {
188					#address-cells = <1>;
189					#size-cells = <0>;
190
191					port@0 {
192						reg = <0>;
193						phy-mode = "internal";
194						phy-handle = <&phy8>;
195					};
196
197					port@1 {
198						reg = <1>;
199						phy-mode = "internal";
200						phy-handle = <&phy9>;
201					};
202
203					port@2 {
204						reg = <2>;
205						phy-mode = "internal";
206						phy-handle = <&phy10>;
207					};
208
209					port@3 {
210						reg = <3>;
211						phy-mode = "internal";
212						phy-handle = <&phy11>;
213					};
214
215					port@8 {
216						reg = <8>;
217						phy-mode = "internal";
218						ethernet = <&enet>;
219
220						fixed-link {
221							speed = <1000>;
222							full-duplex;
223						};
224					};
225				};
226			};
227
228			mdio: mdio@405c0 {
229				compatible = "brcm,unimac-mdio";
230				reg = <0x405c0 0x8>;
231				reg-names = "mdio";
232				#size-cells = <0>;
233				#address-cells = <1>;
234
235				phy8: ethernet-phy@8 {
236					reg = <8>;
237				};
238
239				phy9: ethernet-phy@9 {
240					reg = <9>;
241				};
242
243				phy10: ethernet-phy@a {
244					reg = <10>;
245				};
246
247				phy11: ethernet-phy@b {
248					reg = <11>;
249				};
250
251				phy12: ethernet-phy@c {
252					reg = <12>;
253				};
254			};
255		};
256
257		procmon: syscon@280000 {
258			compatible = "simple-bus";
259			reg = <0x280000 0x1000>;
260			ranges;
261
262			#address-cells = <1>;
263			#size-cells = <1>;
264
265			pmb: power-controller@2800c0 {
266				compatible = "brcm,bcm4908-pmb";
267				reg = <0x2800c0 0x40>;
268				#power-domain-cells = <1>;
269			};
270		};
271	};
272
273	bus@ff800000 {
274		compatible = "simple-bus";
275		#address-cells = <1>;
276		#size-cells = <1>;
277		ranges = <0x00 0x00 0xff800000 0x3000>;
278
279		twd: timer-mfd@400 {
280			compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
281			reg = <0x400 0x4c>;
282			ranges = <0x0 0x400 0x4c>;
283
284			#address-cells = <1>;
285			#size-cells = <1>;
286
287			timer@0 {
288				compatible = "brcm,bcm63138-timer";
289				reg = <0x0 0x28>;
290			};
291
292			watchdog@28 {
293				compatible = "brcm,bcm6345-wdt";
294				reg = <0x28 0x8>;
295			};
296		};
297
298		gpio0: gpio-controller@500 {
299			compatible = "brcm,bcm6345-gpio";
300			reg-names = "dirout", "dat";
301			reg = <0x500 0x28>, <0x528 0x28>;
302
303			#gpio-cells = <2>;
304			gpio-controller;
305		};
306
307		pinctrl@560 {
308			compatible = "brcm,bcm4908-pinctrl";
309			reg = <0x560 0x10>;
310
311			pins_led_0_a: led_0-a-pins {
312				function = "led_0";
313				groups = "led_0_grp_a";
314			};
315
316			pins_led_1_a: led_1-a-pins {
317				function = "led_1";
318				groups = "led_1_grp_a";
319			};
320
321			pins_led_2_a: led_2-a-pins {
322				function = "led_2";
323				groups = "led_2_grp_a";
324			};
325
326			pins_led_3_a: led_3-a-pins {
327				function = "led_3";
328				groups = "led_3_grp_a";
329			};
330
331			pins_led_4_a: led_4-a-pins {
332				function = "led_4";
333				groups = "led_4_grp_a";
334			};
335
336			pins_led_5_a: led_5-a-pins {
337				function = "led_5";
338				groups = "led_5_grp_a";
339			};
340
341			pins_led_6_a: led_6-a-pins {
342				function = "led_6";
343				groups = "led_6_grp_a";
344			};
345
346			pins_led_7_a: led_7-a-pins {
347				function = "led_7";
348				groups = "led_7_grp_a";
349			};
350
351			pins_led_8_a: led_8-a-pins {
352				function = "led_8";
353				groups = "led_8_grp_a";
354			};
355
356			pins_led_9_a: led_9-a-pins {
357				function = "led_9";
358				groups = "led_9_grp_a";
359			};
360
361			pins_led_10_a: led_10-a-pins {
362				function = "led_10";
363				groups = "led_10_grp_a";
364			};
365
366			pins_led_11_a: led_11-a-pins {
367				function = "led_11";
368				groups = "led_11_grp_a";
369			};
370
371			pins_led_12_a: led_12-a-pins {
372				function = "led_12";
373				groups = "led_12_grp_a";
374			};
375
376			pins_led_13_a: led_13-a-pins {
377				function = "led_13";
378				groups = "led_13_grp_a";
379			};
380
381			pins_led_14_a: led_14-a-pins {
382				function = "led_14";
383				groups = "led_14_grp_a";
384			};
385
386			pins_led_15_a: led_15-a-pins {
387				function = "led_15";
388				groups = "led_15_grp_a";
389			};
390
391			pins_led_16_a: led_16-a-pins {
392				function = "led_16";
393				groups = "led_16_grp_a";
394			};
395
396			pins_led_17_a: led_17-a-pins {
397				function = "led_17";
398				groups = "led_17_grp_a";
399			};
400
401			pins_led_18_a: led_18-a-pins {
402				function = "led_18";
403				groups = "led_18_grp_a";
404			};
405
406			pins_led_19_a: led_19-a-pins {
407				function = "led_19";
408				groups = "led_19_grp_a";
409			};
410
411			pins_led_20_a: led_20-a-pins {
412				function = "led_20";
413				groups = "led_20_grp_a";
414			};
415
416			pins_led_21_a: led_21-a-pins {
417				function = "led_21";
418				groups = "led_21_grp_a";
419			};
420
421			pins_led_22_a: led_22-a-pins {
422				function = "led_22";
423				groups = "led_22_grp_a";
424			};
425
426			pins_led_23_a: led_23-a-pins {
427				function = "led_23";
428				groups = "led_23_grp_a";
429			};
430
431			pins_led_24_a: led_24-a-pins {
432				function = "led_24";
433				groups = "led_24_grp_a";
434			};
435
436			pins_led_25_a: led_25-a-pins {
437				function = "led_25";
438				groups = "led_25_grp_a";
439			};
440
441			pins_led_26_a: led_26-a-pins {
442				function = "led_26";
443				groups = "led_26_grp_a";
444			};
445
446			pins_led_27_a: led_27-a-pins {
447				function = "led_27";
448				groups = "led_27_grp_a";
449			};
450
451			pins_led_28_a: led_28-a-pins {
452				function = "led_28";
453				groups = "led_28_grp_a";
454			};
455
456			pins_led_29_a: led_29-a-pins {
457				function = "led_29";
458				groups = "led_29_grp_a";
459			};
460
461			pins_led_30_a: led_30-a-pins {
462				function = "led_30";
463				groups = "led_30_grp_a";
464			};
465
466			pins_led_31_a: led_31-a-pins {
467				function = "led_31";
468				groups = "led_31_grp_a";
469			};
470
471			pins_hs_uart: hs_uart-pins {
472				function = "hs_uart";
473				groups = "hs_uart_grp";
474			};
475
476			pins_i2c_a: i2c-a-pins {
477				function = "i2c";
478				groups = "i2c_grp_a";
479			};
480
481			pins_i2c_b: i2c-b-pins {
482				function = "i2c";
483				groups = "i2c_grp_b";
484			};
485
486			pins_i2s: i2s-pins {
487				function = "i2s";
488				groups = "i2s_grp";
489			};
490
491			pins_nand_ctrl: nand_ctrl-pins {
492				function = "nand_ctrl";
493				groups = "nand_ctrl_grp";
494			};
495
496			pins_nand_data: nand_data-pins {
497				function = "nand_data";
498				groups = "nand_data_grp";
499			};
500
501			pins_emmc_ctrl: emmc_ctrl-pins {
502				function = "emmc_ctrl";
503				groups = "emmc_ctrl_grp";
504			};
505
506			pins_usb0_pwr: usb0_pwr-pins {
507				function = "usb0_pwr";
508				groups = "usb0_pwr_grp";
509			};
510
511			pins_usb1_pwr: usb1_pwr-pins {
512				function = "usb1_pwr";
513				groups = "usb1_pwr_grp";
514			};
515		};
516
517		uart0: serial@640 {
518			compatible = "brcm,bcm6345-uart";
519			reg = <0x640 0x18>;
520			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
521			clocks = <&periph_clk>;
522			clock-names = "refclk";
523			status = "okay";
524		};
525
526		leds: leds@800 {
527			compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
528			reg = <0x800 0xdc>;
529
530			#address-cells = <1>;
531			#size-cells = <0>;
532		};
533
534		nand-controller@1800 {
535			#address-cells = <1>;
536			#size-cells = <0>;
537			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
538			reg = <0x1800 0x600>, <0x2000 0x10>;
539			reg-names = "nand", "nand-int-base";
540			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
541			interrupt-names = "nand";
542			status = "okay";
543
544			nandcs: nand@0 {
545				compatible = "brcm,nandcs";
546				reg = <0>;
547			};
548		};
549
550		i2c@2100 {
551			compatible = "brcm,brcmper-i2c";
552			reg = <0x2100 0x58>;
553			clock-frequency = <97500>;
554			pinctrl-names = "default";
555			pinctrl-0 = <&pins_i2c_a>;
556			status = "disabled";
557		};
558
559		misc@2600 {
560			compatible = "brcm,misc", "simple-mfd";
561			reg = <0x2600 0xe4>;
562
563			#address-cells = <1>;
564			#size-cells = <1>;
565			ranges = <0x00 0x2600 0xe4>;
566
567			reset-controller@2644 {
568				compatible = "brcm,bcm4908-misc-pcie-reset";
569				reg = <0x44 0x04>;
570				#reset-cells = <1>;
571			};
572		};
573	};
574
575	reboot {
576		compatible = "syscon-reboot";
577		regmap = <&twd>;
578		offset = <0x34>;
579		mask = <1>;
580	};
581};
582