1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/dma/fsl-edma.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10 11dma_ipg_clk: clock-dma-ipg { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <120000000>; 15 clock-output-names = "dma_ipg_clk"; 16}; 17 18dma_subsys: bus@5a000000 { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 23 24 lpspi0: spi@5a000000 { 25 compatible = "fsl,imx7ulp-spi"; 26 reg = <0x5a000000 0x10000>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-parent = <&gic>; 31 clocks = <&spi0_lpcg IMX_LPCG_CLK_0>, 32 <&spi0_lpcg IMX_LPCG_CLK_4>; 33 clock-names = "per", "ipg"; 34 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; 35 assigned-clock-rates = <60000000>; 36 power-domains = <&pd IMX_SC_R_SPI_0>; 37 status = "disabled"; 38 }; 39 40 lpspi1: spi@5a010000 { 41 compatible = "fsl,imx7ulp-spi"; 42 reg = <0x5a010000 0x10000>; 43 #address-cells = <1>; 44 #size-cells = <0>; 45 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 46 interrupt-parent = <&gic>; 47 clocks = <&spi1_lpcg IMX_LPCG_CLK_0>, 48 <&spi1_lpcg IMX_LPCG_CLK_4>; 49 clock-names = "per", "ipg"; 50 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; 51 assigned-clock-rates = <60000000>; 52 power-domains = <&pd IMX_SC_R_SPI_1>; 53 status = "disabled"; 54 }; 55 56 lpspi2: spi@5a020000 { 57 compatible = "fsl,imx7ulp-spi"; 58 reg = <0x5a020000 0x10000>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-parent = <&gic>; 63 clocks = <&spi2_lpcg IMX_LPCG_CLK_0>, 64 <&spi2_lpcg IMX_LPCG_CLK_4>; 65 clock-names = "per", "ipg"; 66 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; 67 assigned-clock-rates = <60000000>; 68 power-domains = <&pd IMX_SC_R_SPI_2>; 69 status = "disabled"; 70 }; 71 72 lpspi3: spi@5a030000 { 73 compatible = "fsl,imx7ulp-spi"; 74 reg = <0x5a030000 0x10000>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 78 interrupt-parent = <&gic>; 79 clocks = <&spi3_lpcg IMX_LPCG_CLK_0>, 80 <&spi3_lpcg IMX_LPCG_CLK_4>; 81 clock-names = "per", "ipg"; 82 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; 83 assigned-clock-rates = <60000000>; 84 power-domains = <&pd IMX_SC_R_SPI_3>; 85 status = "disabled"; 86 }; 87 88 lpuart0: serial@5a060000 { 89 reg = <0x5a060000 0x1000>; 90 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 91 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 92 <&uart0_lpcg IMX_LPCG_CLK_0>; 93 clock-names = "ipg", "baud"; 94 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 95 assigned-clock-rates = <80000000>; 96 power-domains = <&pd IMX_SC_R_UART_0>; 97 dma-names = "rx", "tx"; 98 dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>; 99 status = "disabled"; 100 }; 101 102 lpuart1: serial@5a070000 { 103 reg = <0x5a070000 0x1000>; 104 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 106 <&uart1_lpcg IMX_LPCG_CLK_0>; 107 clock-names = "ipg", "baud"; 108 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; 109 assigned-clock-rates = <80000000>; 110 power-domains = <&pd IMX_SC_R_UART_1>; 111 dma-names = "rx", "tx"; 112 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>; 113 status = "disabled"; 114 }; 115 116 lpuart2: serial@5a080000 { 117 reg = <0x5a080000 0x1000>; 118 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 120 <&uart2_lpcg IMX_LPCG_CLK_0>; 121 clock-names = "ipg", "baud"; 122 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; 123 assigned-clock-rates = <80000000>; 124 power-domains = <&pd IMX_SC_R_UART_2>; 125 dma-names = "rx", "tx"; 126 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; 127 status = "disabled"; 128 }; 129 130 lpuart3: serial@5a090000 { 131 reg = <0x5a090000 0x1000>; 132 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 134 <&uart3_lpcg IMX_LPCG_CLK_0>; 135 clock-names = "ipg", "baud"; 136 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; 137 assigned-clock-rates = <80000000>; 138 power-domains = <&pd IMX_SC_R_UART_3>; 139 dma-names = "rx", "tx"; 140 dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; 141 status = "disabled"; 142 }; 143 144 adma_pwm: pwm@5a190000 { 145 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 146 reg = <0x5a190000 0x1000>; 147 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&adma_pwm_lpcg IMX_LPCG_CLK_4>, 149 <&adma_pwm_lpcg IMX_LPCG_CLK_0>; 150 clock-names = "ipg", "per"; 151 assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; 152 assigned-clock-rates = <24000000>; 153 #pwm-cells = <3>; 154 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; 155 }; 156 157 edma2: dma-controller@5a1f0000 { 158 compatible = "fsl,imx8qm-edma"; 159 reg = <0x5a1f0000 0x170000>; 160 #dma-cells = <3>; 161 dma-channels = <16>; 162 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 178 power-domains = <&pd IMX_SC_R_DMA_2_CH0>, 179 <&pd IMX_SC_R_DMA_2_CH1>, 180 <&pd IMX_SC_R_DMA_2_CH2>, 181 <&pd IMX_SC_R_DMA_2_CH3>, 182 <&pd IMX_SC_R_DMA_2_CH4>, 183 <&pd IMX_SC_R_DMA_2_CH5>, 184 <&pd IMX_SC_R_DMA_2_CH6>, 185 <&pd IMX_SC_R_DMA_2_CH7>, 186 <&pd IMX_SC_R_DMA_2_CH8>, 187 <&pd IMX_SC_R_DMA_2_CH9>, 188 <&pd IMX_SC_R_DMA_2_CH10>, 189 <&pd IMX_SC_R_DMA_2_CH11>, 190 <&pd IMX_SC_R_DMA_2_CH12>, 191 <&pd IMX_SC_R_DMA_2_CH13>, 192 <&pd IMX_SC_R_DMA_2_CH14>, 193 <&pd IMX_SC_R_DMA_2_CH15>; 194 }; 195 196 spi0_lpcg: clock-controller@5a400000 { 197 compatible = "fsl,imx8qxp-lpcg"; 198 reg = <0x5a400000 0x10000>; 199 #clock-cells = <1>; 200 clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, 201 <&dma_ipg_clk>; 202 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 203 clock-output-names = "spi0_lpcg_clk", 204 "spi0_lpcg_ipg_clk"; 205 power-domains = <&pd IMX_SC_R_SPI_0>; 206 }; 207 208 spi1_lpcg: clock-controller@5a410000 { 209 compatible = "fsl,imx8qxp-lpcg"; 210 reg = <0x5a410000 0x10000>; 211 #clock-cells = <1>; 212 clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, 213 <&dma_ipg_clk>; 214 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 215 clock-output-names = "spi1_lpcg_clk", 216 "spi1_lpcg_ipg_clk"; 217 power-domains = <&pd IMX_SC_R_SPI_1>; 218 }; 219 220 spi2_lpcg: clock-controller@5a420000 { 221 compatible = "fsl,imx8qxp-lpcg"; 222 reg = <0x5a420000 0x10000>; 223 #clock-cells = <1>; 224 clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, 225 <&dma_ipg_clk>; 226 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 227 clock-output-names = "spi2_lpcg_clk", 228 "spi2_lpcg_ipg_clk"; 229 power-domains = <&pd IMX_SC_R_SPI_2>; 230 }; 231 232 spi3_lpcg: clock-controller@5a430000 { 233 compatible = "fsl,imx8qxp-lpcg"; 234 reg = <0x5a430000 0x10000>; 235 #clock-cells = <1>; 236 clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, 237 <&dma_ipg_clk>; 238 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 239 clock-output-names = "spi3_lpcg_clk", 240 "spi3_lpcg_ipg_clk"; 241 power-domains = <&pd IMX_SC_R_SPI_3>; 242 }; 243 244 uart0_lpcg: clock-controller@5a460000 { 245 compatible = "fsl,imx8qxp-lpcg"; 246 reg = <0x5a460000 0x10000>; 247 #clock-cells = <1>; 248 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 249 <&dma_ipg_clk>; 250 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 251 clock-output-names = "uart0_lpcg_baud_clk", 252 "uart0_lpcg_ipg_clk"; 253 power-domains = <&pd IMX_SC_R_UART_0>; 254 }; 255 256 uart1_lpcg: clock-controller@5a470000 { 257 compatible = "fsl,imx8qxp-lpcg"; 258 reg = <0x5a470000 0x10000>; 259 #clock-cells = <1>; 260 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 261 <&dma_ipg_clk>; 262 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 263 clock-output-names = "uart1_lpcg_baud_clk", 264 "uart1_lpcg_ipg_clk"; 265 power-domains = <&pd IMX_SC_R_UART_1>; 266 }; 267 268 uart2_lpcg: clock-controller@5a480000 { 269 compatible = "fsl,imx8qxp-lpcg"; 270 reg = <0x5a480000 0x10000>; 271 #clock-cells = <1>; 272 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 273 <&dma_ipg_clk>; 274 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 275 clock-output-names = "uart2_lpcg_baud_clk", 276 "uart2_lpcg_ipg_clk"; 277 power-domains = <&pd IMX_SC_R_UART_2>; 278 }; 279 280 uart3_lpcg: clock-controller@5a490000 { 281 compatible = "fsl,imx8qxp-lpcg"; 282 reg = <0x5a490000 0x10000>; 283 #clock-cells = <1>; 284 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 285 <&dma_ipg_clk>; 286 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 287 clock-output-names = "uart3_lpcg_baud_clk", 288 "uart3_lpcg_ipg_clk"; 289 power-domains = <&pd IMX_SC_R_UART_3>; 290 }; 291 292 adma_pwm_lpcg: clock-controller@5a590000 { 293 compatible = "fsl,imx8qxp-lpcg"; 294 reg = <0x5a590000 0x10000>; 295 #clock-cells = <1>; 296 clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, 297 <&dma_ipg_clk>; 298 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 299 clock-output-names = "adma_pwm_lpcg_clk", 300 "adma_pwm_lpcg_ipg_clk"; 301 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; 302 }; 303 304 i2c0: i2c@5a800000 { 305 reg = <0x5a800000 0x4000>; 306 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, 308 <&i2c0_lpcg IMX_LPCG_CLK_4>; 309 clock-names = "per", "ipg"; 310 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 311 assigned-clock-rates = <24000000>; 312 power-domains = <&pd IMX_SC_R_I2C_0>; 313 status = "disabled"; 314 }; 315 316 i2c1: i2c@5a810000 { 317 reg = <0x5a810000 0x4000>; 318 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, 320 <&i2c1_lpcg IMX_LPCG_CLK_4>; 321 clock-names = "per", "ipg"; 322 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 323 assigned-clock-rates = <24000000>; 324 power-domains = <&pd IMX_SC_R_I2C_1>; 325 status = "disabled"; 326 }; 327 328 i2c2: i2c@5a820000 { 329 reg = <0x5a820000 0x4000>; 330 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, 332 <&i2c2_lpcg IMX_LPCG_CLK_4>; 333 clock-names = "per", "ipg"; 334 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 335 assigned-clock-rates = <24000000>; 336 power-domains = <&pd IMX_SC_R_I2C_2>; 337 status = "disabled"; 338 }; 339 340 i2c3: i2c@5a830000 { 341 reg = <0x5a830000 0x4000>; 342 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, 344 <&i2c3_lpcg IMX_LPCG_CLK_4>; 345 clock-names = "per", "ipg"; 346 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 347 assigned-clock-rates = <24000000>; 348 power-domains = <&pd IMX_SC_R_I2C_3>; 349 status = "disabled"; 350 }; 351 352 adc0: adc@5a880000 { 353 compatible = "nxp,imx8qxp-adc"; 354 #io-channel-cells = <1>; 355 reg = <0x5a880000 0x10000>; 356 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-parent = <&gic>; 358 clocks = <&adc0_lpcg IMX_LPCG_CLK_0>, 359 <&adc0_lpcg IMX_LPCG_CLK_4>; 360 clock-names = "per", "ipg"; 361 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; 362 assigned-clock-rates = <24000000>; 363 power-domains = <&pd IMX_SC_R_ADC_0>; 364 status = "disabled"; 365 }; 366 367 adc1: adc@5a890000 { 368 compatible = "nxp,imx8qxp-adc"; 369 #io-channel-cells = <1>; 370 reg = <0x5a890000 0x10000>; 371 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 372 interrupt-parent = <&gic>; 373 clocks = <&adc1_lpcg IMX_LPCG_CLK_0>, 374 <&adc1_lpcg IMX_LPCG_CLK_4>; 375 clock-names = "per", "ipg"; 376 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; 377 assigned-clock-rates = <24000000>; 378 power-domains = <&pd IMX_SC_R_ADC_1>; 379 status = "disabled"; 380 }; 381 382 flexcan1: can@5a8d0000 { 383 compatible = "fsl,imx8qm-flexcan"; 384 reg = <0x5a8d0000 0x10000>; 385 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 386 interrupt-parent = <&gic>; 387 clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 388 <&can0_lpcg IMX_LPCG_CLK_0>; 389 clock-names = "ipg", "per"; 390 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 391 assigned-clock-rates = <40000000>; 392 power-domains = <&pd IMX_SC_R_CAN_0>; 393 /* SLSlice[4] */ 394 fsl,clk-source = /bits/ 8 <0>; 395 fsl,scu-index = /bits/ 8 <0>; 396 status = "disabled"; 397 }; 398 399 flexcan2: can@5a8e0000 { 400 compatible = "fsl,imx8qm-flexcan"; 401 reg = <0x5a8e0000 0x10000>; 402 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-parent = <&gic>; 404 /* CAN0 clock and PD is shared among all CAN instances as 405 * CAN1 shares CAN0's clock and to enable CAN0's clock it 406 * has to be powered on. 407 */ 408 clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 409 <&can0_lpcg IMX_LPCG_CLK_0>; 410 clock-names = "ipg", "per"; 411 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 412 assigned-clock-rates = <40000000>; 413 power-domains = <&pd IMX_SC_R_CAN_1>; 414 /* SLSlice[4] */ 415 fsl,clk-source = /bits/ 8 <0>; 416 fsl,scu-index = /bits/ 8 <1>; 417 status = "disabled"; 418 }; 419 420 flexcan3: can@5a8f0000 { 421 compatible = "fsl,imx8qm-flexcan"; 422 reg = <0x5a8f0000 0x10000>; 423 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 424 interrupt-parent = <&gic>; 425 /* CAN0 clock and PD is shared among all CAN instances as 426 * CAN2 shares CAN0's clock and to enable CAN0's clock it 427 * has to be powered on. 428 */ 429 clocks = <&can0_lpcg IMX_LPCG_CLK_4>, 430 <&can0_lpcg IMX_LPCG_CLK_0>; 431 clock-names = "ipg", "per"; 432 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 433 assigned-clock-rates = <40000000>; 434 power-domains = <&pd IMX_SC_R_CAN_2>; 435 /* SLSlice[4] */ 436 fsl,clk-source = /bits/ 8 <0>; 437 fsl,scu-index = /bits/ 8 <2>; 438 status = "disabled"; 439 }; 440 441 edma3: dma-controller@5a9f0000 { 442 compatible = "fsl,imx8qm-edma"; 443 reg = <0x5a9f0000 0x90000>; 444 #dma-cells = <3>; 445 dma-channels = <8>; 446 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 454 power-domains = <&pd IMX_SC_R_DMA_3_CH0>, 455 <&pd IMX_SC_R_DMA_3_CH1>, 456 <&pd IMX_SC_R_DMA_3_CH2>, 457 <&pd IMX_SC_R_DMA_3_CH3>, 458 <&pd IMX_SC_R_DMA_3_CH4>, 459 <&pd IMX_SC_R_DMA_3_CH5>, 460 <&pd IMX_SC_R_DMA_3_CH6>, 461 <&pd IMX_SC_R_DMA_3_CH7>; 462 }; 463 464 i2c0_lpcg: clock-controller@5ac00000 { 465 compatible = "fsl,imx8qxp-lpcg"; 466 reg = <0x5ac00000 0x10000>; 467 #clock-cells = <1>; 468 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 469 <&dma_ipg_clk>; 470 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 471 clock-output-names = "i2c0_lpcg_clk", 472 "i2c0_lpcg_ipg_clk"; 473 power-domains = <&pd IMX_SC_R_I2C_0>; 474 }; 475 476 i2c1_lpcg: clock-controller@5ac10000 { 477 compatible = "fsl,imx8qxp-lpcg"; 478 reg = <0x5ac10000 0x10000>; 479 #clock-cells = <1>; 480 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 481 <&dma_ipg_clk>; 482 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 483 clock-output-names = "i2c1_lpcg_clk", 484 "i2c1_lpcg_ipg_clk"; 485 power-domains = <&pd IMX_SC_R_I2C_1>; 486 }; 487 488 i2c2_lpcg: clock-controller@5ac20000 { 489 compatible = "fsl,imx8qxp-lpcg"; 490 reg = <0x5ac20000 0x10000>; 491 #clock-cells = <1>; 492 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 493 <&dma_ipg_clk>; 494 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 495 clock-output-names = "i2c2_lpcg_clk", 496 "i2c2_lpcg_ipg_clk"; 497 power-domains = <&pd IMX_SC_R_I2C_2>; 498 }; 499 500 i2c3_lpcg: clock-controller@5ac30000 { 501 compatible = "fsl,imx8qxp-lpcg"; 502 reg = <0x5ac30000 0x10000>; 503 #clock-cells = <1>; 504 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 505 <&dma_ipg_clk>; 506 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 507 clock-output-names = "i2c3_lpcg_clk", 508 "i2c3_lpcg_ipg_clk"; 509 power-domains = <&pd IMX_SC_R_I2C_3>; 510 }; 511 512 adc0_lpcg: clock-controller@5ac80000 { 513 compatible = "fsl,imx8qxp-lpcg"; 514 reg = <0x5ac80000 0x10000>; 515 #clock-cells = <1>; 516 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, 517 <&dma_ipg_clk>; 518 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 519 clock-output-names = "adc0_lpcg_clk", 520 "adc0_lpcg_ipg_clk"; 521 power-domains = <&pd IMX_SC_R_ADC_0>; 522 }; 523 524 adc1_lpcg: clock-controller@5ac90000 { 525 compatible = "fsl,imx8qxp-lpcg"; 526 reg = <0x5ac90000 0x10000>; 527 #clock-cells = <1>; 528 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, 529 <&dma_ipg_clk>; 530 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 531 clock-output-names = "adc1_lpcg_clk", 532 "adc1_lpcg_ipg_clk"; 533 power-domains = <&pd IMX_SC_R_ADC_1>; 534 }; 535 536 can0_lpcg: clock-controller@5acd0000 { 537 compatible = "fsl,imx8qxp-lpcg"; 538 reg = <0x5acd0000 0x10000>; 539 #clock-cells = <1>; 540 clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, 541 <&dma_ipg_clk>, <&dma_ipg_clk>; 542 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 543 clock-output-names = "can0_lpcg_pe_clk", 544 "can0_lpcg_ipg_clk", 545 "can0_lpcg_chi_clk"; 546 power-domains = <&pd IMX_SC_R_CAN_0>; 547 }; 548}; 549