1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10dma_subsys: bus@5a000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 15 16 dma_ipg_clk: clock-dma-ipg { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <120000000>; 20 clock-output-names = "dma_ipg_clk"; 21 }; 22 23 lpspi0: spi@5a000000 { 24 compatible = "fsl,imx7ulp-spi"; 25 reg = <0x5a000000 0x10000>; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-parent = <&gic>; 30 clocks = <&spi0_lpcg 0>, 31 <&spi0_lpcg 1>; 32 clock-names = "per", "ipg"; 33 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; 34 assigned-clock-rates = <60000000>; 35 power-domains = <&pd IMX_SC_R_SPI_0>; 36 status = "disabled"; 37 }; 38 39 lpspi1: spi@5a010000 { 40 compatible = "fsl,imx7ulp-spi"; 41 reg = <0x5a010000 0x10000>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 45 interrupt-parent = <&gic>; 46 clocks = <&spi1_lpcg 0>, 47 <&spi1_lpcg 1>; 48 clock-names = "per", "ipg"; 49 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; 50 assigned-clock-rates = <60000000>; 51 power-domains = <&pd IMX_SC_R_SPI_1>; 52 status = "disabled"; 53 }; 54 55 lpspi2: spi@5a020000 { 56 compatible = "fsl,imx7ulp-spi"; 57 reg = <0x5a020000 0x10000>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-parent = <&gic>; 62 clocks = <&spi2_lpcg 0>, 63 <&spi2_lpcg 1>; 64 clock-names = "per", "ipg"; 65 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; 66 assigned-clock-rates = <60000000>; 67 power-domains = <&pd IMX_SC_R_SPI_2>; 68 status = "disabled"; 69 }; 70 71 lpspi3: spi@5a030000 { 72 compatible = "fsl,imx7ulp-spi"; 73 reg = <0x5a030000 0x10000>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-parent = <&gic>; 78 clocks = <&spi3_lpcg 0>, 79 <&spi3_lpcg 1>; 80 clock-names = "per", "ipg"; 81 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; 82 assigned-clock-rates = <60000000>; 83 power-domains = <&pd IMX_SC_R_SPI_3>; 84 status = "disabled"; 85 }; 86 87 lpuart0: serial@5a060000 { 88 reg = <0x5a060000 0x1000>; 89 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 91 <&uart0_lpcg IMX_LPCG_CLK_0>; 92 clock-names = "ipg", "baud"; 93 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 94 assigned-clock-rates = <80000000>; 95 power-domains = <&pd IMX_SC_R_UART_0>; 96 status = "disabled"; 97 }; 98 99 lpuart1: serial@5a070000 { 100 reg = <0x5a070000 0x1000>; 101 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 103 <&uart1_lpcg IMX_LPCG_CLK_0>; 104 clock-names = "ipg", "baud"; 105 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; 106 assigned-clock-rates = <80000000>; 107 power-domains = <&pd IMX_SC_R_UART_1>; 108 status = "disabled"; 109 }; 110 111 lpuart2: serial@5a080000 { 112 reg = <0x5a080000 0x1000>; 113 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 115 <&uart2_lpcg IMX_LPCG_CLK_0>; 116 clock-names = "ipg", "baud"; 117 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; 118 assigned-clock-rates = <80000000>; 119 power-domains = <&pd IMX_SC_R_UART_2>; 120 status = "disabled"; 121 }; 122 123 lpuart3: serial@5a090000 { 124 reg = <0x5a090000 0x1000>; 125 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 127 <&uart3_lpcg IMX_LPCG_CLK_0>; 128 clock-names = "ipg", "baud"; 129 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; 130 assigned-clock-rates = <80000000>; 131 power-domains = <&pd IMX_SC_R_UART_3>; 132 status = "disabled"; 133 }; 134 135 spi0_lpcg: clock-controller@5a400000 { 136 compatible = "fsl,imx8qxp-lpcg"; 137 reg = <0x5a400000 0x10000>; 138 #clock-cells = <1>; 139 clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, 140 <&dma_ipg_clk>; 141 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 142 clock-output-names = "spi0_lpcg_clk", 143 "spi0_lpcg_ipg_clk"; 144 power-domains = <&pd IMX_SC_R_SPI_0>; 145 }; 146 147 spi1_lpcg: clock-controller@5a410000 { 148 compatible = "fsl,imx8qxp-lpcg"; 149 reg = <0x5a410000 0x10000>; 150 #clock-cells = <1>; 151 clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, 152 <&dma_ipg_clk>; 153 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 154 clock-output-names = "spi1_lpcg_clk", 155 "spi1_lpcg_ipg_clk"; 156 power-domains = <&pd IMX_SC_R_SPI_1>; 157 }; 158 159 spi2_lpcg: clock-controller@5a420000 { 160 compatible = "fsl,imx8qxp-lpcg"; 161 reg = <0x5a420000 0x10000>; 162 #clock-cells = <1>; 163 clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, 164 <&dma_ipg_clk>; 165 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 166 clock-output-names = "spi2_lpcg_clk", 167 "spi2_lpcg_ipg_clk"; 168 power-domains = <&pd IMX_SC_R_SPI_2>; 169 }; 170 171 spi3_lpcg: clock-controller@5a430000 { 172 compatible = "fsl,imx8qxp-lpcg"; 173 reg = <0x5a430000 0x10000>; 174 #clock-cells = <1>; 175 clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, 176 <&dma_ipg_clk>; 177 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 178 clock-output-names = "spi3_lpcg_clk", 179 "spi3_lpcg_ipg_clk"; 180 power-domains = <&pd IMX_SC_R_SPI_3>; 181 }; 182 183 uart0_lpcg: clock-controller@5a460000 { 184 compatible = "fsl,imx8qxp-lpcg"; 185 reg = <0x5a460000 0x10000>; 186 #clock-cells = <1>; 187 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 188 <&dma_ipg_clk>; 189 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 190 clock-output-names = "uart0_lpcg_baud_clk", 191 "uart0_lpcg_ipg_clk"; 192 power-domains = <&pd IMX_SC_R_UART_0>; 193 }; 194 195 uart1_lpcg: clock-controller@5a470000 { 196 compatible = "fsl,imx8qxp-lpcg"; 197 reg = <0x5a470000 0x10000>; 198 #clock-cells = <1>; 199 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 200 <&dma_ipg_clk>; 201 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 202 clock-output-names = "uart1_lpcg_baud_clk", 203 "uart1_lpcg_ipg_clk"; 204 power-domains = <&pd IMX_SC_R_UART_1>; 205 }; 206 207 uart2_lpcg: clock-controller@5a480000 { 208 compatible = "fsl,imx8qxp-lpcg"; 209 reg = <0x5a480000 0x10000>; 210 #clock-cells = <1>; 211 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 212 <&dma_ipg_clk>; 213 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 214 clock-output-names = "uart2_lpcg_baud_clk", 215 "uart2_lpcg_ipg_clk"; 216 power-domains = <&pd IMX_SC_R_UART_2>; 217 }; 218 219 uart3_lpcg: clock-controller@5a490000 { 220 compatible = "fsl,imx8qxp-lpcg"; 221 reg = <0x5a490000 0x10000>; 222 #clock-cells = <1>; 223 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 224 <&dma_ipg_clk>; 225 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 226 clock-output-names = "uart3_lpcg_baud_clk", 227 "uart3_lpcg_ipg_clk"; 228 power-domains = <&pd IMX_SC_R_UART_3>; 229 }; 230 231 i2c0: i2c@5a800000 { 232 reg = <0x5a800000 0x4000>; 233 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, 235 <&i2c0_lpcg IMX_LPCG_CLK_4>; 236 clock-names = "per", "ipg"; 237 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 238 assigned-clock-rates = <24000000>; 239 power-domains = <&pd IMX_SC_R_I2C_0>; 240 status = "disabled"; 241 }; 242 243 i2c1: i2c@5a810000 { 244 reg = <0x5a810000 0x4000>; 245 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, 247 <&i2c1_lpcg IMX_LPCG_CLK_4>; 248 clock-names = "per", "ipg"; 249 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 250 assigned-clock-rates = <24000000>; 251 power-domains = <&pd IMX_SC_R_I2C_1>; 252 status = "disabled"; 253 }; 254 255 i2c2: i2c@5a820000 { 256 reg = <0x5a820000 0x4000>; 257 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, 259 <&i2c2_lpcg IMX_LPCG_CLK_4>; 260 clock-names = "per", "ipg"; 261 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 262 assigned-clock-rates = <24000000>; 263 power-domains = <&pd IMX_SC_R_I2C_2>; 264 status = "disabled"; 265 }; 266 267 i2c3: i2c@5a830000 { 268 reg = <0x5a830000 0x4000>; 269 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, 271 <&i2c3_lpcg IMX_LPCG_CLK_4>; 272 clock-names = "per", "ipg"; 273 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 274 assigned-clock-rates = <24000000>; 275 power-domains = <&pd IMX_SC_R_I2C_3>; 276 status = "disabled"; 277 }; 278 279 adc0: adc@5a880000 { 280 compatible = "nxp,imx8qxp-adc"; 281 #io-channel-cells = <1>; 282 reg = <0x5a880000 0x10000>; 283 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-parent = <&gic>; 285 clocks = <&adc0_lpcg 0>, 286 <&adc0_lpcg 1>; 287 clock-names = "per", "ipg"; 288 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; 289 assigned-clock-rates = <24000000>; 290 power-domains = <&pd IMX_SC_R_ADC_0>; 291 status = "disabled"; 292 }; 293 294 adc1: adc@5a890000 { 295 compatible = "nxp,imx8qxp-adc"; 296 #io-channel-cells = <1>; 297 reg = <0x5a890000 0x10000>; 298 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-parent = <&gic>; 300 clocks = <&adc1_lpcg 0>, 301 <&adc1_lpcg 1>; 302 clock-names = "per", "ipg"; 303 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; 304 assigned-clock-rates = <24000000>; 305 power-domains = <&pd IMX_SC_R_ADC_1>; 306 status = "disabled"; 307 }; 308 309 flexcan1: can@5a8d0000 { 310 compatible = "fsl,imx8qm-flexcan"; 311 reg = <0x5a8d0000 0x10000>; 312 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 313 interrupt-parent = <&gic>; 314 clocks = <&can0_lpcg 1>, 315 <&can0_lpcg 0>; 316 clock-names = "ipg", "per"; 317 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 318 assigned-clock-rates = <40000000>; 319 power-domains = <&pd IMX_SC_R_CAN_0>; 320 /* SLSlice[4] */ 321 fsl,clk-source = /bits/ 8 <0>; 322 fsl,scu-index = /bits/ 8 <0>; 323 status = "disabled"; 324 }; 325 326 flexcan2: can@5a8e0000 { 327 compatible = "fsl,imx8qm-flexcan"; 328 reg = <0x5a8e0000 0x10000>; 329 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 330 interrupt-parent = <&gic>; 331 /* CAN0 clock and PD is shared among all CAN instances as 332 * CAN1 shares CAN0's clock and to enable CAN0's clock it 333 * has to be powered on. 334 */ 335 clocks = <&can0_lpcg 1>, 336 <&can0_lpcg 0>; 337 clock-names = "ipg", "per"; 338 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 339 assigned-clock-rates = <40000000>; 340 power-domains = <&pd IMX_SC_R_CAN_1>; 341 /* SLSlice[4] */ 342 fsl,clk-source = /bits/ 8 <0>; 343 fsl,scu-index = /bits/ 8 <1>; 344 status = "disabled"; 345 }; 346 347 flexcan3: can@5a8f0000 { 348 compatible = "fsl,imx8qm-flexcan"; 349 reg = <0x5a8f0000 0x10000>; 350 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-parent = <&gic>; 352 /* CAN0 clock and PD is shared among all CAN instances as 353 * CAN2 shares CAN0's clock and to enable CAN0's clock it 354 * has to be powered on. 355 */ 356 clocks = <&can0_lpcg 1>, 357 <&can0_lpcg 0>; 358 clock-names = "ipg", "per"; 359 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 360 assigned-clock-rates = <40000000>; 361 power-domains = <&pd IMX_SC_R_CAN_2>; 362 /* SLSlice[4] */ 363 fsl,clk-source = /bits/ 8 <0>; 364 fsl,scu-index = /bits/ 8 <2>; 365 status = "disabled"; 366 }; 367 368 i2c0_lpcg: clock-controller@5ac00000 { 369 compatible = "fsl,imx8qxp-lpcg"; 370 reg = <0x5ac00000 0x10000>; 371 #clock-cells = <1>; 372 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 373 <&dma_ipg_clk>; 374 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 375 clock-output-names = "i2c0_lpcg_clk", 376 "i2c0_lpcg_ipg_clk"; 377 power-domains = <&pd IMX_SC_R_I2C_0>; 378 }; 379 380 i2c1_lpcg: clock-controller@5ac10000 { 381 compatible = "fsl,imx8qxp-lpcg"; 382 reg = <0x5ac10000 0x10000>; 383 #clock-cells = <1>; 384 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 385 <&dma_ipg_clk>; 386 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 387 clock-output-names = "i2c1_lpcg_clk", 388 "i2c1_lpcg_ipg_clk"; 389 power-domains = <&pd IMX_SC_R_I2C_1>; 390 }; 391 392 i2c2_lpcg: clock-controller@5ac20000 { 393 compatible = "fsl,imx8qxp-lpcg"; 394 reg = <0x5ac20000 0x10000>; 395 #clock-cells = <1>; 396 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 397 <&dma_ipg_clk>; 398 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 399 clock-output-names = "i2c2_lpcg_clk", 400 "i2c2_lpcg_ipg_clk"; 401 power-domains = <&pd IMX_SC_R_I2C_2>; 402 }; 403 404 i2c3_lpcg: clock-controller@5ac30000 { 405 compatible = "fsl,imx8qxp-lpcg"; 406 reg = <0x5ac30000 0x10000>; 407 #clock-cells = <1>; 408 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 409 <&dma_ipg_clk>; 410 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 411 clock-output-names = "i2c3_lpcg_clk", 412 "i2c3_lpcg_ipg_clk"; 413 power-domains = <&pd IMX_SC_R_I2C_3>; 414 }; 415 416 adc0_lpcg: clock-controller@5ac80000 { 417 compatible = "fsl,imx8qxp-lpcg"; 418 reg = <0x5ac80000 0x10000>; 419 #clock-cells = <1>; 420 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, 421 <&dma_ipg_clk>; 422 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 423 clock-output-names = "adc0_lpcg_clk", 424 "adc0_lpcg_ipg_clk"; 425 power-domains = <&pd IMX_SC_R_ADC_0>; 426 }; 427 428 adc1_lpcg: clock-controller@5ac90000 { 429 compatible = "fsl,imx8qxp-lpcg"; 430 reg = <0x5ac90000 0x10000>; 431 #clock-cells = <1>; 432 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, 433 <&dma_ipg_clk>; 434 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 435 clock-output-names = "adc1_lpcg_clk", 436 "adc1_lpcg_ipg_clk"; 437 power-domains = <&pd IMX_SC_R_ADC_1>; 438 }; 439 440 can0_lpcg: clock-controller@5acd0000 { 441 compatible = "fsl,imx8qxp-lpcg"; 442 reg = <0x5acd0000 0x10000>; 443 #clock-cells = <1>; 444 clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, 445 <&dma_ipg_clk>, <&dma_ipg_clk>; 446 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 447 clock-output-names = "can0_lpcg_pe_clk", 448 "can0_lpcg_ipg_clk", 449 "can0_lpcg_chi_clk"; 450 power-domains = <&pd IMX_SC_R_CAN_0>; 451 }; 452}; 453