1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6&lsio_gpio0 {
7	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
8	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
9};
10
11&lsio_gpio1 {
12	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
13	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
14};
15
16&lsio_gpio2 {
17	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
18	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
19};
20
21&lsio_gpio3 {
22	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
23	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
24};
25
26&lsio_gpio4 {
27	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
28	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
29};
30
31&lsio_gpio5 {
32	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
33	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
34};
35
36&lsio_gpio6 {
37	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
38	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
39};
40
41&lsio_gpio7 {
42	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
43	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
44};
45
46&lsio_mu0 {
47	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
48	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
49};
50
51&lsio_mu1 {
52	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
53	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
54};
55
56&lsio_mu2 {
57	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
58	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
59};
60
61&lsio_mu3 {
62	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
63	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
64};
65
66&lsio_mu4 {
67	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
68	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
69};
70
71&lsio_mu5 {
72	compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
73	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
74};
75