1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Fabio Estevam <festevam@denx.de>
4 */
5
6/dts-v1/;
7
8#include "imx8mm-tqma8mqml.dtsi"
9
10/ {
11	model = "Cloos i.MX8MM PHG board";
12	compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
13
14	aliases {
15		mmc0 = &usdhc3;
16		mmc1 = &usdhc2;
17	};
18
19	chosen {
20		stdout-path = &uart2;
21	};
22
23	beeper {
24		compatible = "gpio-beeper";
25		pinctrl-0 = <&pinctrl_beeper>;
26		gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
27	};
28
29	leds {
30		compatible = "gpio-leds";
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_gpio_led>;
33
34		led-0 {
35			label = "status1";
36			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
37		};
38
39		led-1 {
40			label = "status2";
41			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
42		};
43
44		led-2 {
45			label = "status3";
46			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
47		};
48
49		led-3 {
50			label = "run";
51			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
52		};
53
54		led-4 {
55			label = "powerled";
56			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
57		};
58	};
59
60	reg_usb_otg_vbus: regulator-usb-otg-vbus {
61		compatible = "regulator-fixed";
62		pinctrl-names = "default";
63		pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
64		regulator-name = "usb_otg_vbus";
65		regulator-min-microvolt = <5000000>;
66		regulator-max-microvolt = <5000000>;
67		gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
68		enable-active-high;
69	};
70
71	reg_usdhc2_vmmc: regulator-vmmc {
72		compatible = "regulator-fixed";
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
75		regulator-name = "VSD_3V3";
76		regulator-min-microvolt = <3300000>;
77		regulator-max-microvolt = <3300000>;
78		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		startup-delay-us = <100>;
81		off-on-delay-us = <12000>;
82	};
83
84	panel {
85		compatible = "panel-lvds";
86		width-mm = <170>;
87		height-mm = <28>;
88		data-mapping = "jeida-18";
89
90		panel-timing {
91			clock-frequency = <49500000>;
92			hactive = <800>;
93			hback-porch = <48>;
94			hfront-porch = <312>;
95			hsync-len = <40>;
96			vactive = <600>;
97			vback-porch = <19>;
98			vfront-porch = <61>;
99			vsync-len = <20>;
100			hsync-active = <0>;
101			vsync-active = <0>;
102			de-active = <1>;
103			pixelclk-active = <1>;
104		};
105
106		port {
107			panel_out_bridge: endpoint {
108				remote-endpoint = <&bridge_out_panel>;
109			};
110		};
111	};
112};
113
114&ecspi1 {
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_ecspi1>;
117	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
118	status = "okay";
119};
120
121&fec1 {
122	pinctrl-names = "default";
123	pinctrl-0 = <&pinctrl_fec1>;
124	phy-mode = "rgmii-id";
125	phy-handle = <&ethphy0>;
126	fsl,magic-packet;
127	status = "okay";
128
129	mdio {
130		#address-cells = <1>;
131		#size-cells = <0>;
132
133		ethphy0: ethernet-phy@0 {
134			reg = <0>;
135			compatible = "ethernet-phy-ieee802.3-c22";
136		};
137	};
138};
139
140&i2c2 {
141	clock-frequency = <100000>;
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_i2c2>;
144	status = "okay";
145
146	bridge@2c {
147		compatible = "ti,sn65dsi83";
148		reg = <0x2c>;
149		enable-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
150		pinctrl-names = "default";
151		pinctrl-0 = <&pinctrl_dsi_bridge>;
152
153		ports {
154			#address-cells = <1>;
155			#size-cells = <0>;
156
157			port@0 {
158				reg = <0>;
159
160				bridge_in_dsi: endpoint {
161					remote-endpoint = <&dsi_out_bridge>;
162					data-lanes = <1 2 3 4>;
163				};
164			};
165
166			port@2 {
167				reg = <2>;
168
169				bridge_out_panel: endpoint {
170					remote-endpoint = <&panel_out_bridge>;
171				};
172			};
173		};
174	};
175};
176
177&lcdif {
178	status = "okay";
179};
180
181&mipi_dsi {
182	samsung,esc-clock-frequency = <10000000>;
183	status = "okay";
184
185	ports {
186		port@1 {
187			reg = <1>;
188
189			dsi_out_bridge: endpoint {
190				data-lanes = <1 2>;
191				lane-polarities = <1 0 0 0 0>;
192				remote-endpoint = <&bridge_in_dsi>;
193			};
194		};
195	};
196};
197
198
199&uart2 {
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_uart2>;
202	status = "okay";
203};
204
205&usbphynop1 {
206	power-domains = <&pgc_otg1>;
207};
208
209&usbphynop2 {
210	power-domains = <&pgc_otg2>;
211};
212
213&usbotg1 {
214	dr_mode = "host";
215	vbus-supply = <&reg_usb_otg_vbus>;
216	status = "okay";
217};
218
219&usbotg2 {
220	dr_mode = "host";
221	status = "okay";
222};
223
224&usdhc2 {
225	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
226	assigned-clock-rates = <400000000>;
227	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
228	pinctrl-names = "default", "state_100mhz", "state_200mhz";
229	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
230	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
231	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
232	bus-width = <4>;
233	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
234	disable-wp;
235	no-mmc;
236	no-sdio;
237	sd-uhs-sdr104;
238	sd-uhs-ddr50;
239	vmmc-supply = <&reg_usdhc2_vmmc>;
240	status = "okay";
241};
242
243&iomuxc {
244	pinctrl_beeper: beepergrp {
245		fsl,pins = <
246			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x19
247		>;
248	};
249
250	pinctrl_dsi_bridge: dsibridgeggrp {
251		fsl,pins = <
252			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3		0x19
253		>;
254	};
255
256	pinctrl_ecspi1: ecspi1grp {
257		fsl,pins = <
258			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82
259			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82
260			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82
261			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19
262		>;
263	};
264
265	pinctrl_fec1: fec1grp {
266		fsl,pins = <
267			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002
268			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002
269			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x14
270			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x14
271			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x14
272			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x14
273			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x90
274			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x90
275			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x90
276			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x90
277			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x14
278			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x90
279			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90
280			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14
281			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x10
282		>;
283	};
284
285	pinctrl_gpio_led: gpioledgrp {
286		fsl,pins = <
287			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
288			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
289			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
290			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
291			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x19
292		>;
293	};
294
295	pinctrl_i2c2: i2c2grp {
296		fsl,pins = <
297			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
298			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
299		>;
300	};
301
302	pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
303		fsl,pins = <
304			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2		0x119
305		>;
306	};
307
308	pinctrl_uart2: uart2grp {
309		fsl,pins = <
310			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140
311			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140
312		>;
313	};
314
315	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
316		fsl,pins = <
317			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x1c4
318		>;
319	};
320
321	pinctrl_usdhc2: usdhc2grp {
322		fsl,pins = <
323			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
324			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
325			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
326			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
327			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
328			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
329		>;
330	};
331
332	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
333		fsl,pins = <
334			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
335			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
336			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
337			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
338			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
339			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
340		>;
341	};
342
343	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
344		fsl,pins = <
345			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
346			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
347			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
348			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
349			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
350			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
351		>;
352	};
353};
354