1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12 13#include "imx8mm.dtsi" 14 15/ { 16 model = "Gateworks Venice GW7901 i.MX8MM board"; 17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm"; 18 19 aliases { 20 ethernet0 = &fec1; 21 ethernet1 = &lan1; 22 ethernet2 = &lan2; 23 ethernet3 = &lan3; 24 ethernet4 = &lan4; 25 usb0 = &usbotg1; 26 usb1 = &usbotg2; 27 }; 28 29 chosen { 30 stdout-path = &uart2; 31 }; 32 33 memory@40000000 { 34 device_type = "memory"; 35 reg = <0x0 0x40000000 0 0x80000000>; 36 }; 37 38 gpio-keys { 39 compatible = "gpio-keys"; 40 41 key-user-pb { 42 label = "user_pb"; 43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 44 linux,code = <BTN_0>; 45 }; 46 47 key-user-pb1x { 48 label = "user_pb1x"; 49 linux,code = <BTN_1>; 50 interrupt-parent = <&gsc>; 51 interrupts = <0>; 52 }; 53 54 key-erased { 55 label = "key_erased"; 56 linux,code = <BTN_2>; 57 interrupt-parent = <&gsc>; 58 interrupts = <1>; 59 }; 60 61 key-eeprom-wp { 62 label = "eeprom_wp"; 63 linux,code = <BTN_3>; 64 interrupt-parent = <&gsc>; 65 interrupts = <2>; 66 }; 67 68 key-tamper { 69 label = "tamper"; 70 linux,code = <BTN_4>; 71 interrupt-parent = <&gsc>; 72 interrupts = <5>; 73 }; 74 75 switch-hold { 76 label = "switch_hold"; 77 linux,code = <BTN_5>; 78 interrupt-parent = <&gsc>; 79 interrupts = <7>; 80 }; 81 }; 82 83 led-controller { 84 compatible = "gpio-leds"; 85 86 led-0 { 87 function = LED_FUNCTION_STATUS; 88 color = <LED_COLOR_ID_RED>; 89 label = "led01_red"; 90 gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>; 91 default-state = "off"; 92 }; 93 94 led-1 { 95 function = LED_FUNCTION_STATUS; 96 color = <LED_COLOR_ID_GREEN>; 97 label = "led01_grn"; 98 gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 102 led-2 { 103 function = LED_FUNCTION_STATUS; 104 color = <LED_COLOR_ID_RED>; 105 label = "led02_red"; 106 gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>; 107 default-state = "off"; 108 }; 109 110 led-3 { 111 function = LED_FUNCTION_STATUS; 112 color = <LED_COLOR_ID_GREEN>; 113 label = "led02_grn"; 114 gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>; 115 default-state = "off"; 116 }; 117 118 led-4 { 119 function = LED_FUNCTION_STATUS; 120 color = <LED_COLOR_ID_RED>; 121 label = "led03_red"; 122 gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>; 123 default-state = "off"; 124 }; 125 126 led-5 { 127 function = LED_FUNCTION_STATUS; 128 color = <LED_COLOR_ID_GREEN>; 129 label = "led03_grn"; 130 gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>; 131 default-state = "off"; 132 }; 133 134 led-6 { 135 function = LED_FUNCTION_STATUS; 136 color = <LED_COLOR_ID_RED>; 137 label = "led04_red"; 138 gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>; 139 default-state = "off"; 140 }; 141 142 led-7 { 143 function = LED_FUNCTION_STATUS; 144 color = <LED_COLOR_ID_GREEN>; 145 label = "led04_grn"; 146 gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>; 147 default-state = "off"; 148 }; 149 150 led-8 { 151 function = LED_FUNCTION_STATUS; 152 color = <LED_COLOR_ID_RED>; 153 label = "led05_red"; 154 gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>; 155 default-state = "off"; 156 }; 157 158 led-9 { 159 function = LED_FUNCTION_STATUS; 160 color = <LED_COLOR_ID_GREEN>; 161 label = "led05_grn"; 162 gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 166 led-a { 167 function = LED_FUNCTION_STATUS; 168 color = <LED_COLOR_ID_RED>; 169 label = "led06_red"; 170 gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>; 171 default-state = "off"; 172 }; 173 174 led-b { 175 function = LED_FUNCTION_STATUS; 176 color = <LED_COLOR_ID_GREEN>; 177 label = "led06_grn"; 178 gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>; 179 default-state = "off"; 180 }; 181 }; 182 183 pcie0_refclk: pcie0-refclk { 184 compatible = "fixed-clock"; 185 #clock-cells = <0>; 186 clock-frequency = <100000000>; 187 }; 188 189 reg_3p3v: regulator-3p3v { 190 compatible = "regulator-fixed"; 191 regulator-name = "3P3V"; 192 regulator-min-microvolt = <3300000>; 193 regulator-max-microvolt = <3300000>; 194 }; 195 196 regulator-ioexp { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_reg_ioexp>; 199 compatible = "regulator-fixed"; 200 regulator-name = "ioexp"; 201 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 202 enable-active-high; 203 startup-delay-us = <100>; 204 regulator-min-microvolt = <3300000>; 205 regulator-max-microvolt = <3300000>; 206 regulator-always-on; 207 }; 208 209 regulator-isouart { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_reg_isouart>; 212 compatible = "regulator-fixed"; 213 regulator-name = "iso_uart"; 214 gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; 215 startup-delay-us = <100>; 216 regulator-min-microvolt = <3300000>; 217 regulator-max-microvolt = <3300000>; 218 regulator-always-on; 219 }; 220 221 reg_usb2_vbus: regulator-usb2 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_reg_usb2>; 224 compatible = "regulator-fixed"; 225 regulator-name = "usb_usb2_vbus"; 226 gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; 227 enable-active-high; 228 regulator-min-microvolt = <5000000>; 229 regulator-max-microvolt = <5000000>; 230 }; 231 232 reg_wifi: regulator-wifi { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_reg_wl>; 235 compatible = "regulator-fixed"; 236 regulator-name = "wifi"; 237 gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; 238 enable-active-high; 239 startup-delay-us = <100>; 240 regulator-min-microvolt = <3300000>; 241 regulator-max-microvolt = <3300000>; 242 }; 243}; 244 245&A53_0 { 246 cpu-supply = <&buck2>; 247}; 248 249&A53_1 { 250 cpu-supply = <&buck2>; 251}; 252 253&A53_2 { 254 cpu-supply = <&buck2>; 255}; 256 257&A53_3 { 258 cpu-supply = <&buck2>; 259}; 260 261&ddrc { 262 operating-points-v2 = <&ddrc_opp_table>; 263 264 ddrc_opp_table: opp-table { 265 compatible = "operating-points-v2"; 266 267 opp-25000000 { 268 opp-hz = /bits/ 64 <25000000>; 269 }; 270 271 opp-100000000 { 272 opp-hz = /bits/ 64 <100000000>; 273 }; 274 275 opp-750000000 { 276 opp-hz = /bits/ 64 <750000000>; 277 }; 278 }; 279}; 280 281&disp_blk_ctrl { 282 status = "disabled"; 283}; 284 285&ecspi1 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_spi1>; 288 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 289 <&gpio4 24 GPIO_ACTIVE_LOW>; 290 status = "okay"; 291 292 flash@0 { 293 compatible = "jedec,spi-nor"; 294 reg = <0>; 295 spi-max-frequency = <40000000>; 296 status = "okay"; 297 }; 298 299 tpm@1 { 300 compatible = "tcg,tpm_tis-spi"; 301 reg = <0x1>; 302 spi-max-frequency = <36000000>; 303 }; 304}; 305 306&fec1 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_fec1>; 309 phy-mode = "rgmii-id"; 310 local-mac-address = [00 00 00 00 00 00]; 311 status = "okay"; 312 313 fixed-link { 314 speed = <1000>; 315 full-duplex; 316 }; 317}; 318 319&gpio1 { 320 gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", 321 "", "uart1_rs232#", "dig1_in", "dig1_out", 322 "", "", "", "", "", "", "", "", 323 "", "", "", "", "", "", "", "", 324 "", "", "", "", "", "", "", ""; 325}; 326 327&gpio4 { 328 gpio-line-names = "", "", "", "", 329 "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#", 330 "uart3_rs485#", "", "", "", "", "", "", "", 331 "", "", "", "", "", "", "", "", 332 "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; 333}; 334 335&gpio5 { 336 gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", 337 "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", 338 "", "", "", "", "", "", "", "", 339 "", "", "", "", "", "", "", ""; 340}; 341 342&gpu_2d { 343 status = "disabled"; 344}; 345 346&gpu_3d { 347 status = "disabled"; 348}; 349 350&i2c1 { 351 clock-frequency = <100000>; 352 pinctrl-names = "default", "gpio"; 353 pinctrl-0 = <&pinctrl_i2c1>; 354 pinctrl-1 = <&pinctrl_i2c1_gpio>; 355 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 356 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 357 status = "okay"; 358 359 gsc: gsc@20 { 360 compatible = "gw,gsc"; 361 reg = <0x20>; 362 pinctrl-0 = <&pinctrl_gsc>; 363 interrupt-parent = <&gpio4>; 364 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 365 interrupt-controller; 366 #interrupt-cells = <1>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 370 adc { 371 compatible = "gw,gsc-adc"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 375 channel@6 { 376 gw,mode = <0>; 377 reg = <0x06>; 378 label = "temp"; 379 }; 380 381 channel@8 { 382 gw,mode = <3>; 383 reg = <0x08>; 384 label = "vdd_bat"; 385 }; 386 387 channel@82 { 388 gw,mode = <2>; 389 reg = <0x82>; 390 label = "vin_aux1"; 391 gw,voltage-divider-ohms = <22100 1000>; 392 }; 393 394 channel@84 { 395 gw,mode = <2>; 396 reg = <0x84>; 397 label = "vin_aux2"; 398 gw,voltage-divider-ohms = <22100 1000>; 399 }; 400 401 channel@86 { 402 gw,mode = <2>; 403 reg = <0x86>; 404 label = "vdd_vin"; 405 gw,voltage-divider-ohms = <22100 1000>; 406 }; 407 408 channel@88 { 409 gw,mode = <2>; 410 reg = <0x88>; 411 label = "vdd_3p3"; 412 gw,voltage-divider-ohms = <10000 10000>; 413 }; 414 415 channel@8c { 416 gw,mode = <2>; 417 reg = <0x8c>; 418 label = "vdd_2p5"; 419 gw,voltage-divider-ohms = <10000 10000>; 420 }; 421 422 channel@8e { 423 gw,mode = <2>; 424 reg = <0x8e>; 425 label = "vdd_0p95"; 426 }; 427 428 channel@90 { 429 gw,mode = <2>; 430 reg = <0x90>; 431 label = "vdd_soc"; 432 }; 433 434 channel@92 { 435 gw,mode = <2>; 436 reg = <0x92>; 437 label = "vdd_arm"; 438 }; 439 440 channel@98 { 441 gw,mode = <2>; 442 reg = <0x98>; 443 label = "vdd_1p8"; 444 }; 445 446 channel@9a { 447 gw,mode = <2>; 448 reg = <0x9a>; 449 label = "vdd_1p2"; 450 }; 451 452 channel@9c { 453 gw,mode = <2>; 454 reg = <0x9c>; 455 label = "vdd_dram"; 456 }; 457 458 channel@a2 { 459 gw,mode = <2>; 460 reg = <0xa2>; 461 label = "vdd_gsc"; 462 gw,voltage-divider-ohms = <10000 10000>; 463 }; 464 }; 465 }; 466 467 gpio: gpio@23 { 468 compatible = "nxp,pca9555"; 469 reg = <0x23>; 470 gpio-controller; 471 #gpio-cells = <2>; 472 interrupt-parent = <&gsc>; 473 interrupts = <4>; 474 }; 475 476 eeprom@50 { 477 compatible = "atmel,24c02"; 478 reg = <0x50>; 479 pagesize = <16>; 480 }; 481 482 eeprom@51 { 483 compatible = "atmel,24c02"; 484 reg = <0x51>; 485 pagesize = <16>; 486 }; 487 488 eeprom@52 { 489 compatible = "atmel,24c02"; 490 reg = <0x52>; 491 pagesize = <16>; 492 }; 493 494 eeprom@53 { 495 compatible = "atmel,24c02"; 496 reg = <0x53>; 497 pagesize = <16>; 498 }; 499 500 rtc@68 { 501 compatible = "dallas,ds1672"; 502 reg = <0x68>; 503 }; 504}; 505 506&i2c2 { 507 clock-frequency = <400000>; 508 pinctrl-names = "default", "gpio"; 509 pinctrl-0 = <&pinctrl_i2c2>; 510 pinctrl-1 = <&pinctrl_i2c2_gpio>; 511 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 512 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 513 status = "okay"; 514 515 pmic@4b { 516 compatible = "rohm,bd71847"; 517 reg = <0x4b>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pinctrl_pmic>; 520 interrupt-parent = <&gpio3>; 521 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 522 rohm,reset-snvs-powered; 523 #clock-cells = <0>; 524 clocks = <&osc_32k>; 525 clock-output-names = "clk-32k-out"; 526 527 regulators { 528 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 529 BUCK1 { 530 regulator-name = "buck1"; 531 regulator-min-microvolt = <700000>; 532 regulator-max-microvolt = <1300000>; 533 regulator-boot-on; 534 regulator-always-on; 535 regulator-ramp-delay = <1250>; 536 }; 537 538 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 539 buck2: BUCK2 { 540 regulator-name = "buck2"; 541 regulator-min-microvolt = <700000>; 542 regulator-max-microvolt = <1300000>; 543 regulator-boot-on; 544 regulator-always-on; 545 regulator-ramp-delay = <1250>; 546 rohm,dvs-run-voltage = <1000000>; 547 rohm,dvs-idle-voltage = <900000>; 548 }; 549 550 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 551 BUCK3 { 552 regulator-name = "buck3"; 553 regulator-min-microvolt = <700000>; 554 regulator-max-microvolt = <1350000>; 555 regulator-boot-on; 556 regulator-always-on; 557 }; 558 559 /* vdd_3p3 */ 560 BUCK4 { 561 regulator-name = "buck4"; 562 regulator-min-microvolt = <3000000>; 563 regulator-max-microvolt = <3300000>; 564 regulator-boot-on; 565 regulator-always-on; 566 }; 567 568 /* vdd_1p8 */ 569 BUCK5 { 570 regulator-name = "buck5"; 571 regulator-min-microvolt = <1605000>; 572 regulator-max-microvolt = <1995000>; 573 regulator-boot-on; 574 regulator-always-on; 575 }; 576 577 /* vdd_dram */ 578 BUCK6 { 579 regulator-name = "buck6"; 580 regulator-min-microvolt = <800000>; 581 regulator-max-microvolt = <1400000>; 582 regulator-boot-on; 583 regulator-always-on; 584 }; 585 586 /* nvcc_snvs_1p8 */ 587 LDO1 { 588 regulator-name = "ldo1"; 589 regulator-min-microvolt = <1600000>; 590 regulator-max-microvolt = <1900000>; 591 regulator-boot-on; 592 regulator-always-on; 593 }; 594 595 /* vdd_snvs_0p8 */ 596 LDO2 { 597 regulator-name = "ldo2"; 598 regulator-min-microvolt = <800000>; 599 regulator-max-microvolt = <900000>; 600 regulator-boot-on; 601 regulator-always-on; 602 }; 603 604 /* vdda_1p8 */ 605 LDO3 { 606 regulator-name = "ldo3"; 607 regulator-min-microvolt = <1800000>; 608 regulator-max-microvolt = <3300000>; 609 regulator-boot-on; 610 regulator-always-on; 611 }; 612 613 LDO4 { 614 regulator-name = "ldo4"; 615 regulator-min-microvolt = <900000>; 616 regulator-max-microvolt = <1800000>; 617 regulator-boot-on; 618 regulator-always-on; 619 }; 620 621 LDO6 { 622 regulator-name = "ldo6"; 623 regulator-min-microvolt = <900000>; 624 regulator-max-microvolt = <1800000>; 625 regulator-boot-on; 626 regulator-always-on; 627 }; 628 }; 629 }; 630}; 631 632&i2c3 { 633 clock-frequency = <400000>; 634 pinctrl-names = "default", "gpio"; 635 pinctrl-0 = <&pinctrl_i2c3>; 636 pinctrl-1 = <&pinctrl_i2c3_gpio>; 637 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 638 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 639 status = "okay"; 640 641 leds_gpio: gpio@20 { 642 compatible = "nxp,pca9555"; 643 reg = <0x20>; 644 gpio-controller; 645 #gpio-cells = <2>; 646 }; 647 648 switch: switch@5f { 649 compatible = "microchip,ksz9897"; 650 reg = <0x5f>; 651 pinctrl-0 = <&pinctrl_ksz>; 652 interrupt-parent = <&gpio4>; 653 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 654 655 ports { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 lan1: port@0 { 660 reg = <0>; 661 label = "lan1"; 662 phy-mode = "internal"; 663 local-mac-address = [00 00 00 00 00 00]; 664 }; 665 666 lan2: port@1 { 667 reg = <1>; 668 label = "lan2"; 669 phy-mode = "internal"; 670 local-mac-address = [00 00 00 00 00 00]; 671 }; 672 673 lan3: port@2 { 674 reg = <2>; 675 label = "lan3"; 676 phy-mode = "internal"; 677 local-mac-address = [00 00 00 00 00 00]; 678 }; 679 680 lan4: port@3 { 681 reg = <3>; 682 label = "lan4"; 683 phy-mode = "internal"; 684 local-mac-address = [00 00 00 00 00 00]; 685 }; 686 687 port@5 { 688 reg = <5>; 689 ethernet = <&fec1>; 690 phy-mode = "rgmii-id"; 691 692 fixed-link { 693 speed = <1000>; 694 full-duplex; 695 }; 696 }; 697 }; 698 }; 699 700 crypto@60 { 701 compatible = "atmel,atecc508a"; 702 reg = <0x60>; 703 }; 704}; 705 706&i2c4 { 707 clock-frequency = <400000>; 708 pinctrl-names = "default", "gpio"; 709 pinctrl-0 = <&pinctrl_i2c4>; 710 pinctrl-1 = <&pinctrl_i2c4_gpio>; 711 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 712 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 713 status = "okay"; 714}; 715 716&pcie_phy { 717 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 718 fsl,clkreq-unsupported; 719 clocks = <&pcie0_refclk>; 720 clock-names = "ref"; 721 status = "okay"; 722}; 723 724&pcie0 { 725 pinctrl-names = "default"; 726 pinctrl-0 = <&pinctrl_pcie0>; 727 reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; 728 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 729 <&clk IMX8MM_CLK_PCIE1_AUX>; 730 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 731 <&clk IMX8MM_CLK_PCIE1_CTRL>; 732 assigned-clock-rates = <10000000>, <250000000>; 733 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 734 <&clk IMX8MM_SYS_PLL2_250M>; 735 status = "okay"; 736}; 737 738&pgc_gpu { 739 status = "disabled"; 740}; 741 742&pgc_gpumix { 743 status = "disabled"; 744}; 745 746&pgc_mipi { 747 status = "disabled"; 748}; 749 750&uart1 { 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 753 rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 754 cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 755 dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 756 dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 757 dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 758 status = "okay"; 759}; 760 761/* console */ 762&uart2 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_uart2>; 765 status = "okay"; 766}; 767 768&uart3 { 769 pinctrl-names = "default"; 770 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 771 cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 772 rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 773 status = "okay"; 774}; 775 776&uart4 { 777 pinctrl-names = "default"; 778 pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; 779 cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 780 rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 781 status = "okay"; 782}; 783 784&usbotg1 { 785 dr_mode = "host"; 786 disable-over-current; 787 status = "okay"; 788}; 789 790&usbotg2 { 791 dr_mode = "host"; 792 vbus-supply = <®_usb2_vbus>; 793 over-current-active-low; 794 status = "okay"; 795}; 796 797/* SDIO WiFi */ 798&usdhc1 { 799 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 800 pinctrl-0 = <&pinctrl_usdhc1>; 801 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 802 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 803 bus-width = <4>; 804 non-removable; 805 vmmc-supply = <®_wifi>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "okay"; 809 810 wifi@0 { 811 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; 812 reg = <0>; 813 }; 814}; 815 816/* microSD */ 817&usdhc2 { 818 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 819 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 820 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 821 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 822 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 823 bus-width = <4>; 824 vmmc-supply = <®_3p3v>; 825 status = "okay"; 826}; 827 828/* eMMC */ 829&usdhc3 { 830 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 831 pinctrl-0 = <&pinctrl_usdhc3>; 832 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 833 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 834 bus-width = <8>; 835 non-removable; 836 status = "okay"; 837}; 838 839&wdog1 { 840 pinctrl-names = "default"; 841 pinctrl-0 = <&pinctrl_wdog>; 842 fsl,ext-reset-output; 843 status = "okay"; 844}; 845 846&iomuxc { 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_hog>; 849 850 pinctrl_hog: hoggrp { 851 fsl,pins = < 852 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */ 853 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */ 854 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */ 855 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */ 856 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */ 857 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */ 858 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */ 859 MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */ 860 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */ 861 >; 862 }; 863 864 pinctrl_fec1: fec1grp { 865 fsl,pins = < 866 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 867 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 868 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 869 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 870 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 871 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 872 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 873 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 874 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 875 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 876 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 877 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 878 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 879 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 880 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */ 881 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */ 882 >; 883 }; 884 885 pinctrl_gsc: gscgrp { 886 fsl,pins = < 887 MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159 888 >; 889 }; 890 891 pinctrl_i2c1: i2c1grp { 892 fsl,pins = < 893 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 894 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 895 >; 896 }; 897 898 pinctrl_i2c1_gpio: i2c1gpiogrp { 899 fsl,pins = < 900 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 901 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 902 >; 903 }; 904 905 pinctrl_i2c2: i2c2grp { 906 fsl,pins = < 907 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 908 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 909 >; 910 }; 911 912 pinctrl_i2c2_gpio: i2c2gpiogrp { 913 fsl,pins = < 914 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 915 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 916 >; 917 }; 918 919 pinctrl_i2c3: i2c3grp { 920 fsl,pins = < 921 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 922 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 923 >; 924 }; 925 926 pinctrl_i2c3_gpio: i2c3gpiogrp { 927 fsl,pins = < 928 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 929 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 930 >; 931 }; 932 933 pinctrl_i2c4: i2c4grp { 934 fsl,pins = < 935 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 936 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 937 >; 938 }; 939 940 pinctrl_i2c4_gpio: i2c4gpiogrp { 941 fsl,pins = < 942 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 943 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 944 >; 945 }; 946 947 pinctrl_ksz: kszgrp { 948 fsl,pins = < 949 MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 950 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */ 951 >; 952 }; 953 954 pinctrl_pcie0: pciegrp { 955 fsl,pins = < 956 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ 957 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 958 >; 959 }; 960 961 pinctrl_pmic: pmicgrp { 962 fsl,pins = < 963 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 964 >; 965 }; 966 967 pinctrl_reg_isouart: regisouartgrp { 968 fsl,pins = < 969 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 970 >; 971 }; 972 973 pinctrl_reg_ioexp: regioexpgrp { 974 fsl,pins = < 975 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 976 >; 977 }; 978 979 pinctrl_reg_wl: regwlgrp { 980 fsl,pins = < 981 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041 982 >; 983 }; 984 985 pinctrl_reg_usb2: regusb1grp { 986 fsl,pins = < 987 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x41 988 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 989 MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x140 990 >; 991 }; 992 993 pinctrl_spi1: spi1grp { 994 fsl,pins = < 995 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 996 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 997 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 998 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140 999 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 1000 >; 1001 }; 1002 1003 pinctrl_uart1: uart1grp { 1004 fsl,pins = < 1005 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 1006 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 1007 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 1008 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 1009 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140 1010 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140 1011 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140 1012 >; 1013 }; 1014 1015 pinctrl_uart1_gpio: uart1gpiogrp { 1016 fsl,pins = < 1017 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */ 1018 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */ 1019 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */ 1020 >; 1021 }; 1022 1023 pinctrl_uart2: uart2grp { 1024 fsl,pins = < 1025 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 1026 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 1027 >; 1028 }; 1029 1030 pinctrl_uart3: uart3grp { 1031 fsl,pins = < 1032 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 1033 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 1034 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 1035 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 1036 >; 1037 }; 1038 1039 pinctrl_uart3_gpio: uart3gpiogrp { 1040 fsl,pins = < 1041 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */ 1042 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */ 1043 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */ 1044 >; 1045 }; 1046 1047 pinctrl_uart4: uart4grp { 1048 fsl,pins = < 1049 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 1050 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 1051 MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140 1052 MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140 1053 >; 1054 }; 1055 1056 pinctrl_uart4_gpio: uart4gpiogrp { 1057 fsl,pins = < 1058 1059 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */ 1060 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */ 1061 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */ 1062 >; 1063 }; 1064 1065 pinctrl_usdhc1: usdhc1grp { 1066 fsl,pins = < 1067 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 1068 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 1069 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 1070 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 1071 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 1072 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 1073 >; 1074 }; 1075 1076 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1077 fsl,pins = < 1078 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 1079 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 1080 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 1081 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 1082 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 1083 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 1084 >; 1085 }; 1086 1087 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1088 fsl,pins = < 1089 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 1090 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 1091 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 1092 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 1093 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 1094 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 1095 >; 1096 }; 1097 1098 pinctrl_usdhc2: usdhc2grp { 1099 fsl,pins = < 1100 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 1101 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 1102 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 1103 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 1104 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 1105 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 1106 >; 1107 }; 1108 1109 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1110 fsl,pins = < 1111 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 1112 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 1113 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 1114 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 1115 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 1116 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 1117 >; 1118 }; 1119 1120 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1121 fsl,pins = < 1122 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 1123 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 1124 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 1125 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 1126 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 1127 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 1128 >; 1129 }; 1130 1131 pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 1132 fsl,pins = < 1133 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 1134 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 1135 >; 1136 }; 1137 1138 pinctrl_usdhc3: usdhc3grp { 1139 fsl,pins = < 1140 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 1141 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 1142 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 1143 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 1144 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 1145 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 1146 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 1147 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 1148 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 1149 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 1150 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 1151 >; 1152 }; 1153 1154 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1155 fsl,pins = < 1156 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 1157 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 1158 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 1159 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 1160 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 1161 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 1162 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 1163 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 1164 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 1165 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 1166 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 1167 >; 1168 }; 1169 1170 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1171 fsl,pins = < 1172 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 1173 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 1174 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 1175 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 1176 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 1177 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 1178 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 1179 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 1180 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 1181 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1182 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1183 >; 1184 }; 1185 1186 pinctrl_wdog: wdoggrp { 1187 fsl,pins = < 1188 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1189 >; 1190 }; 1191}; 1192