1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/phy/phy-imx8-pcie.h>
13
14#include "imx8mm.dtsi"
15
16/ {
17	model = "Gateworks Venice GW7902 i.MX8MM board";
18	compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
19
20	aliases {
21		ethernet1 = &eth1;
22		usb0 = &usbotg1;
23		usb1 = &usbotg2;
24	};
25
26	chosen {
27		stdout-path = &uart2;
28	};
29
30	memory@40000000 {
31		device_type = "memory";
32		reg = <0x0 0x40000000 0 0x80000000>;
33	};
34
35	can20m: can20m {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-frequency = <20000000>;
39		clock-output-names = "can20m";
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44
45		key-user-pb {
46			label = "user_pb";
47			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48			linux,code = <BTN_0>;
49		};
50
51		key-user-pb1x {
52			label = "user_pb1x";
53			linux,code = <BTN_1>;
54			interrupt-parent = <&gsc>;
55			interrupts = <0>;
56		};
57
58		key-erased {
59			label = "key_erased";
60			linux,code = <BTN_2>;
61			interrupt-parent = <&gsc>;
62			interrupts = <1>;
63		};
64
65		key-eeprom-wp {
66			label = "eeprom_wp";
67			linux,code = <BTN_3>;
68			interrupt-parent = <&gsc>;
69			interrupts = <2>;
70		};
71
72		key-tamper {
73			label = "tamper";
74			linux,code = <BTN_4>;
75			interrupt-parent = <&gsc>;
76			interrupts = <5>;
77		};
78
79		switch-hold {
80			label = "switch_hold";
81			linux,code = <BTN_5>;
82			interrupt-parent = <&gsc>;
83			interrupts = <7>;
84		};
85	};
86
87	led-controller {
88		compatible = "gpio-leds";
89		pinctrl-names = "default";
90		pinctrl-0 = <&pinctrl_gpio_leds>;
91
92		led-0 {
93			function = LED_FUNCTION_STATUS;
94			color = <LED_COLOR_ID_GREEN>;
95			label = "panel1";
96			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
97			default-state = "off";
98		};
99
100		led-1 {
101			function = LED_FUNCTION_STATUS;
102			color = <LED_COLOR_ID_GREEN>;
103			label = "panel2";
104			gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
105			default-state = "off";
106		};
107
108		led-2 {
109			function = LED_FUNCTION_STATUS;
110			color = <LED_COLOR_ID_GREEN>;
111			label = "panel3";
112			gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
113			default-state = "off";
114		};
115
116		led-3 {
117			function = LED_FUNCTION_STATUS;
118			color = <LED_COLOR_ID_GREEN>;
119			label = "panel4";
120			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
121			default-state = "off";
122		};
123
124		led-4 {
125			function = LED_FUNCTION_STATUS;
126			color = <LED_COLOR_ID_GREEN>;
127			label = "panel5";
128			gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
129			default-state = "off";
130		};
131	};
132
133	pcie0_refclk: pcie0-refclk {
134		compatible = "fixed-clock";
135		#clock-cells = <0>;
136		clock-frequency = <100000000>;
137	};
138
139	pps {
140		compatible = "pps-gpio";
141		pinctrl-names = "default";
142		pinctrl-0 = <&pinctrl_pps>;
143		gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
144		status = "okay";
145	};
146
147	reg_3p3v: regulator-3p3v {
148		compatible = "regulator-fixed";
149		regulator-name = "3P3V";
150		regulator-min-microvolt = <3300000>;
151		regulator-max-microvolt = <3300000>;
152		regulator-always-on;
153	};
154
155	reg_usb1_vbus: regulator-usb1 {
156		compatible = "regulator-fixed";
157		pinctrl-names = "default";
158		pinctrl-0 = <&pinctrl_reg_usb1>;
159		regulator-name = "usb_usb1_vbus";
160		gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
161		enable-active-high;
162		regulator-min-microvolt = <5000000>;
163		regulator-max-microvolt = <5000000>;
164	};
165
166	reg_wifi: regulator-wifi {
167		compatible = "regulator-fixed";
168		pinctrl-names = "default";
169		pinctrl-0 = <&pinctrl_reg_wl>;
170		regulator-name = "wifi";
171		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
172		enable-active-high;
173		startup-delay-us = <100>;
174		regulator-min-microvolt = <3300000>;
175		regulator-max-microvolt = <3300000>;
176	};
177};
178
179&A53_0 {
180	cpu-supply = <&buck2>;
181};
182
183&A53_1 {
184	cpu-supply = <&buck2>;
185};
186
187&A53_2 {
188	cpu-supply = <&buck2>;
189};
190
191&A53_3 {
192	cpu-supply = <&buck2>;
193};
194
195&ddrc {
196	operating-points-v2 = <&ddrc_opp_table>;
197
198	ddrc_opp_table: opp-table {
199		compatible = "operating-points-v2";
200
201		opp-25M {
202			opp-hz = /bits/ 64 <25000000>;
203		};
204
205		opp-100M {
206			opp-hz = /bits/ 64 <100000000>;
207		};
208
209		opp-750M {
210			opp-hz = /bits/ 64 <750000000>;
211		};
212	};
213};
214
215&ecspi1 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_spi1>;
218	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
219	status = "okay";
220
221	can@0 {
222		compatible = "microchip,mcp2515";
223		reg = <0>;
224		clocks = <&can20m>;
225		interrupt-parent = <&gpio2>;
226		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
227		spi-max-frequency = <10000000>;
228	};
229};
230
231/* off-board header */
232&ecspi2 {
233	pinctrl-names = "default";
234	pinctrl-0 = <&pinctrl_spi2>;
235	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
236	status = "okay";
237};
238
239&fec1 {
240	pinctrl-names = "default";
241	pinctrl-0 = <&pinctrl_fec1>;
242	phy-mode = "rgmii-id";
243	phy-handle = <&ethphy0>;
244	local-mac-address = [00 00 00 00 00 00];
245	status = "okay";
246
247	mdio {
248		#address-cells = <1>;
249		#size-cells = <0>;
250
251		ethphy0: ethernet-phy@0 {
252			compatible = "ethernet-phy-ieee802.3-c22";
253			reg = <0>;
254			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
255			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
256			tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
257			rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
258		};
259	};
260};
261
262&gpio1 {
263	gpio-line-names = "", "", "", "", "", "", "", "",
264		"", "", "", "", "", "m2_reset", "", "m2_wdis#",
265		"", "", "", "", "", "", "", "",
266		"", "", "", "", "", "", "", "";
267};
268
269&gpio2 {
270	gpio-line-names = "", "", "", "", "", "", "", "",
271		"uart2_en#", "", "", "", "", "", "", "",
272		"", "", "", "", "", "", "", "",
273		"", "", "", "", "", "", "", "";
274};
275
276&gpio3 {
277	gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
278		"", "", "", "", "", "", "", "",
279		"", "", "", "", "", "", "", "",
280		"", "", "", "", "", "", "", "";
281};
282
283&gpio4 {
284	gpio-line-names = "", "", "", "", "", "", "", "",
285		"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
286		"", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
287		"", "uart1_term", "uart1_half", "app_gpio2",
288		"mipi_gpio1", "", "", "";
289};
290
291&gpio5 {
292	gpio-line-names = "", "", "", "mipi_gpio4",
293		"mipi_gpio3", "mipi_gpio2", "", "",
294		"", "", "", "", "", "", "", "",
295		"", "", "", "", "", "", "", "",
296		"", "", "", "", "", "", "", "";
297};
298
299&i2c1 {
300	clock-frequency = <100000>;
301	pinctrl-names = "default";
302	pinctrl-0 = <&pinctrl_i2c1>;
303	status = "okay";
304
305	gsc: gsc@20 {
306		compatible = "gw,gsc";
307		reg = <0x20>;
308		pinctrl-0 = <&pinctrl_gsc>;
309		interrupt-parent = <&gpio2>;
310		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
311		interrupt-controller;
312		#interrupt-cells = <1>;
313
314		adc {
315			compatible = "gw,gsc-adc";
316			#address-cells = <1>;
317			#size-cells = <0>;
318
319			channel@6 {
320				gw,mode = <0>;
321				reg = <0x06>;
322				label = "temp";
323			};
324
325			channel@8 {
326				gw,mode = <1>;
327				reg = <0x08>;
328				label = "vdd_bat";
329			};
330
331			channel@82 {
332				gw,mode = <2>;
333				reg = <0x82>;
334				label = "vin";
335				gw,voltage-divider-ohms = <22100 1000>;
336				gw,voltage-offset-microvolt = <700000>;
337			};
338
339			channel@84 {
340				gw,mode = <2>;
341				reg = <0x84>;
342				label = "vin_4p0";
343				gw,voltage-divider-ohms = <10000 10000>;
344			};
345
346			channel@86 {
347				gw,mode = <2>;
348				reg = <0x86>;
349				label = "vdd_3p3";
350				gw,voltage-divider-ohms = <10000 10000>;
351			};
352
353			channel@88 {
354				gw,mode = <2>;
355				reg = <0x88>;
356				label = "vdd_0p9";
357			};
358
359			channel@8c {
360				gw,mode = <2>;
361				reg = <0x8c>;
362				label = "vdd_soc";
363			};
364
365			channel@8e {
366				gw,mode = <2>;
367				reg = <0x8e>;
368				label = "vdd_arm";
369			};
370
371			channel@90 {
372				gw,mode = <2>;
373				reg = <0x90>;
374				label = "vdd_1p8";
375			};
376
377			channel@92 {
378				gw,mode = <2>;
379				reg = <0x92>;
380				label = "vdd_dram";
381			};
382
383			channel@98 {
384				gw,mode = <2>;
385				reg = <0x98>;
386				label = "vdd_1p0";
387			};
388
389			channel@9a {
390				gw,mode = <2>;
391				reg = <0x9a>;
392				label = "vdd_2p5";
393				gw,voltage-divider-ohms = <10000 10000>;
394			};
395
396			channel@9c {
397				gw,mode = <2>;
398				reg = <0x9c>;
399				label = "vdd_5p0";
400				gw,voltage-divider-ohms = <10000 10000>;
401			};
402
403			channel@a2 {
404				gw,mode = <2>;
405				reg = <0xa2>;
406				label = "vdd_gsc";
407				gw,voltage-divider-ohms = <10000 10000>;
408			};
409		};
410	};
411
412	gpio: gpio@23 {
413		compatible = "nxp,pca9555";
414		reg = <0x23>;
415		gpio-controller;
416		#gpio-cells = <2>;
417		interrupt-parent = <&gsc>;
418		interrupts = <4>;
419	};
420
421	pmic@4b {
422		compatible = "rohm,bd71847";
423		reg = <0x4b>;
424		pinctrl-names = "default";
425		pinctrl-0 = <&pinctrl_pmic>;
426		interrupt-parent = <&gpio3>;
427		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
428		rohm,reset-snvs-powered;
429		#clock-cells = <0>;
430		clocks = <&osc_32k 0>;
431		clock-output-names = "clk-32k-out";
432
433		regulators {
434			/* vdd_soc: 0.805-0.900V (typ=0.8V) */
435			BUCK1 {
436				regulator-name = "buck1";
437				regulator-min-microvolt = <700000>;
438				regulator-max-microvolt = <1300000>;
439				regulator-boot-on;
440				regulator-always-on;
441				regulator-ramp-delay = <1250>;
442			};
443
444			/* vdd_arm: 0.805-1.0V (typ=0.9V) */
445			buck2: BUCK2 {
446				regulator-name = "buck2";
447				regulator-min-microvolt = <700000>;
448				regulator-max-microvolt = <1300000>;
449				regulator-boot-on;
450				regulator-always-on;
451				regulator-ramp-delay = <1250>;
452				rohm,dvs-run-voltage = <1000000>;
453				rohm,dvs-idle-voltage = <900000>;
454			};
455
456			/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
457			BUCK3 {
458				regulator-name = "buck3";
459				regulator-min-microvolt = <700000>;
460				regulator-max-microvolt = <1350000>;
461				regulator-boot-on;
462				regulator-always-on;
463			};
464
465			/* vdd_3p3 */
466			BUCK4 {
467				regulator-name = "buck4";
468				regulator-min-microvolt = <3000000>;
469				regulator-max-microvolt = <3300000>;
470				regulator-boot-on;
471				regulator-always-on;
472			};
473
474			/* vdd_1p8 */
475			BUCK5 {
476				regulator-name = "buck5";
477				regulator-min-microvolt = <1605000>;
478				regulator-max-microvolt = <1995000>;
479				regulator-boot-on;
480				regulator-always-on;
481			};
482
483			/* vdd_dram */
484			BUCK6 {
485				regulator-name = "buck6";
486				regulator-min-microvolt = <800000>;
487				regulator-max-microvolt = <1400000>;
488				regulator-boot-on;
489				regulator-always-on;
490			};
491
492			/* nvcc_snvs_1p8 */
493			LDO1 {
494				regulator-name = "ldo1";
495				regulator-min-microvolt = <1600000>;
496				regulator-max-microvolt = <1900000>;
497				regulator-boot-on;
498				regulator-always-on;
499			};
500
501			/* vdd_snvs_0p8 */
502			LDO2 {
503				regulator-name = "ldo2";
504				regulator-min-microvolt = <800000>;
505				regulator-max-microvolt = <900000>;
506				regulator-boot-on;
507				regulator-always-on;
508			};
509
510			/* vdda_1p8 */
511			LDO3 {
512				regulator-name = "ldo3";
513				regulator-min-microvolt = <1800000>;
514				regulator-max-microvolt = <3300000>;
515				regulator-boot-on;
516				regulator-always-on;
517			};
518
519			LDO4 {
520				regulator-name = "ldo4";
521				regulator-min-microvolt = <900000>;
522				regulator-max-microvolt = <1800000>;
523				regulator-boot-on;
524				regulator-always-on;
525			};
526
527			LDO6 {
528				regulator-name = "ldo6";
529				regulator-min-microvolt = <900000>;
530				regulator-max-microvolt = <1800000>;
531				regulator-boot-on;
532				regulator-always-on;
533			};
534		};
535	};
536
537	eeprom@50 {
538		compatible = "atmel,24c02";
539		reg = <0x50>;
540		pagesize = <16>;
541	};
542
543	eeprom@51 {
544		compatible = "atmel,24c02";
545		reg = <0x51>;
546		pagesize = <16>;
547	};
548
549	eeprom@52 {
550		compatible = "atmel,24c02";
551		reg = <0x52>;
552		pagesize = <16>;
553	};
554
555	eeprom@53 {
556		compatible = "atmel,24c02";
557		reg = <0x53>;
558		pagesize = <16>;
559	};
560
561	rtc@68 {
562		compatible = "dallas,ds1672";
563		reg = <0x68>;
564	};
565};
566
567&i2c2 {
568	clock-frequency = <400000>;
569	pinctrl-names = "default";
570	pinctrl-0 = <&pinctrl_i2c2>;
571	status = "okay";
572
573	accelerometer@19 {
574		compatible = "st,lis2de12";
575		pinctrl-names = "default";
576		pinctrl-0 = <&pinctrl_accel>;
577		reg = <0x19>;
578		st,drdy-int-pin = <1>;
579		interrupt-parent = <&gpio1>;
580		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
581		interrupt-names = "INT1";
582	};
583};
584
585/* off-board header */
586&i2c3 {
587	clock-frequency = <400000>;
588	pinctrl-names = "default";
589	pinctrl-0 = <&pinctrl_i2c3>;
590	status = "okay";
591};
592
593/* off-board header */
594&i2c4 {
595	clock-frequency = <400000>;
596	pinctrl-names = "default";
597	pinctrl-0 = <&pinctrl_i2c4>;
598	status = "okay";
599};
600
601&pcie_phy {
602	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
603	fsl,clkreq-unsupported;
604	clocks = <&pcie0_refclk>;
605	clock-names = "ref";
606	status = "okay";
607};
608
609&pcie0 {
610	pinctrl-names = "default";
611	pinctrl-0 = <&pinctrl_pcie0>;
612	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
613	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
614		 <&pcie0_refclk>;
615	clock-names = "pcie", "pcie_aux", "pcie_bus";
616	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
617			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
618	assigned-clock-rates = <10000000>, <250000000>;
619	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
620				 <&clk IMX8MM_SYS_PLL2_250M>;
621	status = "okay";
622
623	pcie@0,0 {
624		reg = <0x0000 0 0 0 0>;
625		#address-cells = <1>;
626		#size-cells = <0>;
627
628		eth1: pcie@1,0 {
629			reg = <0x0000 0 0 0 0>;
630			#address-cells = <1>;
631			#size-cells = <0>;
632
633			local-mac-address = [00 00 00 00 00 00];
634		};
635	};
636};
637
638/* off-board header */
639&sai3 {
640	pinctrl-names = "default";
641	pinctrl-0 = <&pinctrl_sai3>;
642	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
643	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
644	assigned-clock-rates = <24576000>;
645	status = "okay";
646};
647
648/* RS232/RS485/RS422 selectable */
649&uart1 {
650	pinctrl-names = "default";
651	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
652	rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
653	cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
654	uart-has-rtscts;
655	status = "okay";
656};
657
658/* RS232 console */
659&uart2 {
660	pinctrl-names = "default";
661	pinctrl-0 = <&pinctrl_uart2>;
662	status = "okay";
663};
664
665/* bluetooth HCI */
666&uart3 {
667	pinctrl-names = "default";
668	pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
669	rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
670	cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
671	uart-has-rtscts;
672	status = "okay";
673
674	bluetooth {
675		compatible = "brcm,bcm4330-bt";
676		shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
677	};
678};
679
680/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
681&uart4 {
682	pinctrl-names = "default";
683	pinctrl-0 = <&pinctrl_uart4>;
684	rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
685	cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
686	dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
687	dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
688	dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
689	uart-has-rtscts;
690	status = "okay";
691};
692
693&usbotg1 {
694	dr_mode = "host";
695	vbus-supply = <&reg_usb1_vbus>;
696	disable-over-current;
697	status = "okay";
698};
699
700&usbotg2 {
701	dr_mode = "host";
702	disable-over-current;
703	status = "okay";
704};
705
706/* SDIO WiFi */
707&usdhc2 {
708	pinctrl-names = "default";
709	pinctrl-0 = <&pinctrl_usdhc2>;
710	bus-width = <4>;
711	non-removable;
712	vmmc-supply = <&reg_wifi>;
713	status = "okay";
714};
715
716/* eMMC */
717&usdhc3 {
718	pinctrl-names = "default", "state_100mhz", "state_200mhz";
719	pinctrl-0 = <&pinctrl_usdhc3>;
720	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
721	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
722	bus-width = <8>;
723	non-removable;
724	status = "okay";
725};
726
727&wdog1 {
728	pinctrl-names = "default";
729	pinctrl-0 = <&pinctrl_wdog>;
730	fsl,ext-reset-output;
731	status = "okay";
732};
733
734&iomuxc {
735	pinctrl-names = "default";
736	pinctrl-0 = <&pinctrl_hog>;
737
738	pinctrl_hog: hoggrp {
739		fsl,pins = <
740			MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1	0x40000159 /* M2_GDIS# */
741			MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x40000041 /* M2_RESET */
742			MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7	0x40000119 /* M2_OFF# */
743			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x40000159 /* M2_WDIS# */
744			MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14	0x40000041 /* AMP GPIO1 */
745			MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12	0x40000041 /* AMP GPIO2 */
746			MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11	0x40000041 /* AMP GPIO3 */
747			MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20	0x40000041 /* AMP_GPIO4 */
748			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x40000041 /* APP GPIO1 */
749			MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27	0x40000041 /* APP GPIO2 */
750			MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8	0x40000041 /* UART2_EN# */
751			MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x40000041 /* MIPI_GPIO1 */
752			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x40000041 /* MIPI_GPIO2 */
753			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x40000041 /* MIPI_GPIO3/PWM2 */
754			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* MIPI_GPIO4/PWM3 */
755		>;
756	};
757
758	pinctrl_accel: accelgrp {
759		fsl,pins = <
760			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x159
761		>;
762	};
763
764	pinctrl_fec1: fec1grp {
765		fsl,pins = <
766			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
767			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
768			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
769			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
770			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
771			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
772			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
773			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
774			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
775			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
776			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
777			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
778			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
779			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
780			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19 /* RST# */
781			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x19 /* IRQ# */
782			MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN	0x141
783			MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT	0x141
784		>;
785	};
786
787	pinctrl_gsc: gscgrp {
788		fsl,pins = <
789			MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x40
790		>;
791	};
792
793	pinctrl_i2c1: i2c1grp {
794		fsl,pins = <
795			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
796			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
797		>;
798	};
799
800	pinctrl_i2c2: i2c2grp {
801		fsl,pins = <
802			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
803			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
804		>;
805	};
806
807	pinctrl_i2c3: i2c3grp {
808		fsl,pins = <
809			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
810			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
811		>;
812	};
813
814	pinctrl_i2c4: i2c4grp {
815		fsl,pins = <
816			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
817			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
818		>;
819	};
820
821	pinctrl_gpio_leds: gpioledgrp {
822		fsl,pins = <
823			MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21	0x19
824			MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x19
825			MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x19
826			MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20	0x19
827			MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x19
828		>;
829	};
830
831	pinctrl_pcie0: pciegrp {
832		fsl,pins = <
833			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x41
834		>;
835	};
836
837	pinctrl_pmic: pmicgrp {
838		fsl,pins = <
839			MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8	0x41
840		>;
841	};
842
843	pinctrl_pps: ppsgrp {
844		fsl,pins = <
845			MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x141 /* PPS */
846		>;
847	};
848
849	pinctrl_reg_wl: regwlgrp {
850		fsl,pins = <
851			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41 /* WLAN_WLON */
852		>;
853	};
854
855	pinctrl_reg_usb1: regusb1grp {
856		fsl,pins = <
857			MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7	0x41
858		>;
859	};
860
861	pinctrl_sai3: sai3grp {
862		fsl,pins = <
863			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK	0xd6
864			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
865			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
866			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
867			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
868		>;
869	};
870
871	pinctrl_spi1: spi1grp {
872		fsl,pins = <
873			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x82
874			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x82
875			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x82
876			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x40
877			MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3	0x140 /* CAN_IRQ# */
878		>;
879	};
880
881	pinctrl_spi2: spi2grp {
882		fsl,pins = <
883			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
884			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
885			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
886			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x40 /* SS0 */
887		>;
888	};
889
890	pinctrl_uart1: uart1grp {
891		fsl,pins = <
892			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
893			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
894			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10	0x140 /* RTS */
895			MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24	0x140 /* CTS */
896		>;
897	};
898
899	pinctrl_uart1_gpio: uart1gpiogrp {
900		fsl,pins = <
901			MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26	0x40000110 /* HALF */
902			MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25	0x40000110 /* TERM */
903			MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23	0x40000110 /* RS485 */
904		>;
905	};
906
907	pinctrl_uart2: uart2grp {
908		fsl,pins = <
909			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
910			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
911		>;
912	};
913
914	pinctrl_uart3_gpio: uart3_gpiogrp {
915		fsl,pins = <
916			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41 /* BT_EN# */
917		>;
918	};
919
920	pinctrl_uart3: uart3grp {
921		fsl,pins = <
922			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
923			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
924			MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x140 /* CTS */
925			MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1		0x140 /* RTS */
926		>;
927	};
928
929	pinctrl_uart4: uart4grp {
930		fsl,pins = <
931			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
932			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
933			MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1		0x140 /* CTS */
934			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x140 /* RTS */
935			MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3	0x140 /* DTR */
936			MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4	0x140 /* DSR */
937			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x140 /* DCD */
938			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x140 /* RI */
939			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x140 /* GNSS_PPS */
940			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x141 /* GNSS_GASP */
941		>;
942	};
943
944	pinctrl_usdhc2: usdhc2grp {
945		fsl,pins = <
946			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
947			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
948			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
949			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
950			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
951			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
952		>;
953	};
954
955	pinctrl_usdhc3: usdhc3grp {
956		fsl,pins = <
957			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
958			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
959			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
960			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
961			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
962			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
963			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
964			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
965			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
966			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
967			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
968		>;
969	};
970
971	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
972		fsl,pins = <
973			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
974			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
975			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
976			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
977			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
978			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
979			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
980			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
981			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
982			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
983			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
984		>;
985	};
986
987	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
988		fsl,pins = <
989			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
990			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
991			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
992			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
993			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
994			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
995			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
996			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
997			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
998			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
999			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
1000		>;
1001	};
1002
1003	pinctrl_wdog: wdoggrp {
1004		fsl,pins = <
1005			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
1006		>;
1007	};
1008};
1009