1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include "dt-bindings/phy/phy-imx8-pcie.h" 7#include "dt-bindings/pwm/pwm.h" 8#include "imx8mm.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 aliases { 16 rtc0 = &rtc_i2c; 17 rtc1 = &snvs_rtc; 18 }; 19 20 backlight: backlight { 21 compatible = "pwm-backlight"; 22 brightness-levels = <0 45 63 88 119 158 203 255>; 23 default-brightness-level = <4>; 24 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 25 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 26 pinctrl-names = "default"; 27 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 28 power-supply = <®_3p3v>; 29 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 30 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; 31 status = "disabled"; 32 }; 33 34 /* Fixed clock dedicated to SPI CAN controller */ 35 clk40m: oscillator { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <40000000>; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinctrl_gpio_keys>; 45 46 key-wakeup { 47 debounce-interval = <10>; 48 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 49 gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 50 label = "Wake-Up"; 51 linux,code = <KEY_WAKEUP>; 52 wakeup-source; 53 }; 54 }; 55 56 hdmi_connector: hdmi-connector { 57 compatible = "hdmi-connector"; 58 ddc-i2c-bus = <&i2c2>; 59 label = "hdmi"; 60 type = "a"; 61 status = "disabled"; 62 }; 63 64 panel_lvds: panel-lvds { 65 compatible = "panel-lvds"; 66 backlight = <&backlight>; 67 data-mapping = "vesa-24"; 68 status = "disabled"; 69 }; 70 71 /* Carrier Board Supplies */ 72 reg_1p8v: regulator-1p8v { 73 compatible = "regulator-fixed"; 74 regulator-max-microvolt = <1800000>; 75 regulator-min-microvolt = <1800000>; 76 regulator-name = "+V1.8_SW"; 77 }; 78 79 reg_3p3v: regulator-3p3v { 80 compatible = "regulator-fixed"; 81 regulator-max-microvolt = <3300000>; 82 regulator-min-microvolt = <3300000>; 83 regulator-name = "+V3.3_SW"; 84 }; 85 86 reg_5p0v: regulator-5p0v { 87 compatible = "regulator-fixed"; 88 regulator-max-microvolt = <5000000>; 89 regulator-min-microvolt = <5000000>; 90 regulator-name = "+V5_SW"; 91 }; 92 93 /* Non PMIC On-module Supplies */ 94 reg_ethphy: regulator-ethphy { 95 compatible = "regulator-fixed"; 96 enable-active-high; 97 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 98 off-on-delay = <500000>; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_reg_eth>; 101 regulator-boot-on; 102 regulator-max-microvolt = <3300000>; 103 regulator-min-microvolt = <3300000>; 104 regulator-name = "On-module +V3.3_ETH"; 105 startup-delay-us = <200000>; 106 }; 107 108 reg_usb_otg1_vbus: regulator-usb-otg1 { 109 compatible = "regulator-fixed"; 110 enable-active-high; 111 /* Verdin USB_1_EN (SODIMM 155) */ 112 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_reg_usb1_en>; 115 regulator-max-microvolt = <5000000>; 116 regulator-min-microvolt = <5000000>; 117 regulator-name = "USB_1_EN"; 118 }; 119 120 reg_usb_otg2_vbus: regulator-usb-otg2 { 121 compatible = "regulator-fixed"; 122 enable-active-high; 123 /* Verdin USB_2_EN (SODIMM 185) */ 124 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_reg_usb2_en>; 127 regulator-max-microvolt = <5000000>; 128 regulator-min-microvolt = <5000000>; 129 regulator-name = "USB_2_EN"; 130 }; 131 132 reg_usdhc2_vmmc: regulator-usdhc2 { 133 compatible = "regulator-fixed"; 134 enable-active-high; 135 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 136 gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 137 off-on-delay = <100000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 140 regulator-max-microvolt = <3300000>; 141 regulator-min-microvolt = <3300000>; 142 regulator-name = "+V3.3_SD"; 143 startup-delay-us = <2000>; 144 }; 145 146 reserved-memory { 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 /* Use the kernel configuration settings instead */ 152 /delete-node/ linux,cma; 153 }; 154}; 155 156&A53_0 { 157 cpu-supply = <®_vdd_arm>; 158}; 159 160&A53_1 { 161 cpu-supply = <®_vdd_arm>; 162}; 163 164&A53_2 { 165 cpu-supply = <®_vdd_arm>; 166}; 167 168&A53_3 { 169 cpu-supply = <®_vdd_arm>; 170}; 171 172&cpu_alert0 { 173 temperature = <95000>; 174}; 175 176&cpu_crit0 { 177 temperature = <105000>; 178}; 179 180&ddrc { 181 operating-points-v2 = <&ddrc_opp_table>; 182 183 ddrc_opp_table: opp-table { 184 compatible = "operating-points-v2"; 185 186 opp-25M { 187 opp-hz = /bits/ 64 <25000000>; 188 }; 189 190 opp-100M { 191 opp-hz = /bits/ 64 <100000000>; 192 }; 193 194 opp-750M { 195 opp-hz = /bits/ 64 <750000000>; 196 }; 197 }; 198}; 199 200/* Verdin SPI_1 */ 201&ecspi2 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_ecspi2>; 207}; 208 209/* Verdin CAN_1 (On-module) */ 210&ecspi3 { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_ecspi3>; 216 status = "okay"; 217 218 can1: can@0 { 219 compatible = "microchip,mcp251xfd"; 220 clocks = <&clk40m>; 221 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_can1_int>; 224 reg = <0>; 225 spi-max-frequency = <8500000>; 226 }; 227}; 228 229/* Verdin ETH_1 (On-module PHY) */ 230&fec1 { 231 fsl,magic-packet; 232 phy-handle = <ðphy0>; 233 phy-mode = "rgmii-id"; 234 phy-supply = <®_ethphy>; 235 pinctrl-names = "default", "sleep"; 236 pinctrl-0 = <&pinctrl_fec1>; 237 pinctrl-1 = <&pinctrl_fec1_sleep>; 238 239 mdio { 240 #address-cells = <1>; 241 #size-cells = <0>; 242 243 ethphy0: ethernet-phy@7 { 244 compatible = "ethernet-phy-ieee802.3-c22"; 245 interrupt-parent = <&gpio1>; 246 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 247 micrel,led-mode = <0>; 248 reg = <7>; 249 }; 250 }; 251}; 252 253/* Verdin QSPI_1 */ 254&flexspi { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_flexspi0>; 257}; 258 259&gpio1 { 260 gpio-line-names = "SODIMM_216", 261 "SODIMM_19", 262 "", 263 "", 264 "", 265 "", 266 "", 267 "", 268 "SODIMM_220", 269 "SODIMM_222", 270 "", 271 "SODIMM_218", 272 "SODIMM_155", 273 "SODIMM_157", 274 "SODIMM_185", 275 "SODIMM_187"; 276}; 277 278&gpio2 { 279 gpio-line-names = "", 280 "", 281 "", 282 "", 283 "", 284 "", 285 "", 286 "", 287 "", 288 "", 289 "", 290 "", 291 "SODIMM_84", 292 "SODIMM_78", 293 "SODIMM_74", 294 "SODIMM_80", 295 "SODIMM_82", 296 "SODIMM_70", 297 "SODIMM_72"; 298}; 299 300&gpio5 { 301 gpio-line-names = "SODIMM_131", 302 "", 303 "SODIMM_91", 304 "SODIMM_16", 305 "SODIMM_15", 306 "SODIMM_208", 307 "SODIMM_137", 308 "SODIMM_139", 309 "SODIMM_141", 310 "SODIMM_143", 311 "SODIMM_196", 312 "SODIMM_200", 313 "SODIMM_198", 314 "SODIMM_202", 315 "", 316 "", 317 "SODIMM_55", 318 "SODIMM_53", 319 "SODIMM_95", 320 "SODIMM_93", 321 "SODIMM_14", 322 "SODIMM_12", 323 "", 324 "", 325 "", 326 "", 327 "SODIMM_210", 328 "SODIMM_212", 329 "SODIMM_151", 330 "SODIMM_153"; 331 332 ctrl-sleep-moci-hog { 333 gpio-hog; 334 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 335 gpios = <1 GPIO_ACTIVE_HIGH>; 336 line-name = "CTRL_SLEEP_MOCI#"; 337 output-high; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 340 }; 341}; 342 343/* On-module I2C */ 344&i2c1 { 345 clock-frequency = <400000>; 346 pinctrl-names = "default", "gpio"; 347 pinctrl-0 = <&pinctrl_i2c1>; 348 pinctrl-1 = <&pinctrl_i2c1_gpio>; 349 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 350 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 351 status = "okay"; 352 353 pca9450: pmic@25 { 354 compatible = "nxp,pca9450a"; 355 interrupt-parent = <&gpio1>; 356 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 357 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_pmic>; 360 reg = <0x25>; 361 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 362 363 /* 364 * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC 365 * behind this PMIC. 366 */ 367 368 regulators { 369 reg_vdd_soc: BUCK1 { 370 nxp,dvs-run-voltage = <850000>; 371 nxp,dvs-standby-voltage = <800000>; 372 regulator-always-on; 373 regulator-boot-on; 374 regulator-max-microvolt = <850000>; 375 regulator-min-microvolt = <800000>; 376 regulator-name = "On-module +VDD_SOC (BUCK1)"; 377 regulator-ramp-delay = <3125>; 378 }; 379 380 reg_vdd_arm: BUCK2 { 381 nxp,dvs-run-voltage = <950000>; 382 nxp,dvs-standby-voltage = <850000>; 383 regulator-always-on; 384 regulator-boot-on; 385 regulator-max-microvolt = <1050000>; 386 regulator-min-microvolt = <805000>; 387 regulator-name = "On-module +VDD_ARM (BUCK2)"; 388 regulator-ramp-delay = <3125>; 389 }; 390 391 reg_vdd_dram: BUCK3 { 392 regulator-always-on; 393 regulator-boot-on; 394 regulator-max-microvolt = <1000000>; 395 regulator-min-microvolt = <805000>; 396 regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; 397 }; 398 399 reg_vdd_3v3: BUCK4 { 400 regulator-always-on; 401 regulator-boot-on; 402 regulator-max-microvolt = <3300000>; 403 regulator-min-microvolt = <3300000>; 404 regulator-name = "On-module +V3.3 (BUCK4)"; 405 }; 406 407 reg_vdd_1v8: BUCK5 { 408 regulator-always-on; 409 regulator-boot-on; 410 regulator-max-microvolt = <1800000>; 411 regulator-min-microvolt = <1800000>; 412 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 413 }; 414 415 reg_nvcc_dram: BUCK6 { 416 regulator-always-on; 417 regulator-boot-on; 418 regulator-max-microvolt = <1100000>; 419 regulator-min-microvolt = <1100000>; 420 regulator-name = "On-module +VDD_DDR (BUCK6)"; 421 }; 422 423 reg_nvcc_snvs: LDO1 { 424 regulator-always-on; 425 regulator-boot-on; 426 regulator-max-microvolt = <1800000>; 427 regulator-min-microvolt = <1800000>; 428 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 429 }; 430 431 reg_vdd_snvs: LDO2 { 432 regulator-always-on; 433 regulator-boot-on; 434 regulator-max-microvolt = <800000>; 435 regulator-min-microvolt = <800000>; 436 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 437 }; 438 439 reg_vdda: LDO3 { 440 regulator-always-on; 441 regulator-boot-on; 442 regulator-max-microvolt = <1800000>; 443 regulator-min-microvolt = <1800000>; 444 regulator-name = "On-module +V1.8A (LDO3)"; 445 }; 446 447 reg_vdd_phy: LDO4 { 448 regulator-always-on; 449 regulator-boot-on; 450 regulator-max-microvolt = <900000>; 451 regulator-min-microvolt = <900000>; 452 regulator-name = "On-module +V0.9_MIPI (LDO4)"; 453 }; 454 455 reg_nvcc_sd: LDO5 { 456 regulator-max-microvolt = <3300000>; 457 regulator-min-microvolt = <1800000>; 458 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 459 }; 460 }; 461 }; 462 463 rtc_i2c: rtc@32 { 464 compatible = "epson,rx8130"; 465 reg = <0x32>; 466 }; 467 468 adc@49 { 469 compatible = "ti,ads1015"; 470 reg = <0x49>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 474 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 475 channel@0 { 476 reg = <0>; 477 ti,datarate = <4>; 478 ti,gain = <2>; 479 }; 480 481 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 482 channel@1 { 483 reg = <1>; 484 ti,datarate = <4>; 485 ti,gain = <2>; 486 }; 487 488 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 489 channel@2 { 490 reg = <2>; 491 ti,datarate = <4>; 492 ti,gain = <2>; 493 }; 494 495 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 496 channel@3 { 497 reg = <3>; 498 ti,datarate = <4>; 499 ti,gain = <2>; 500 }; 501 502 /* Verdin I2C_1 ADC_4 */ 503 channel@4 { 504 reg = <4>; 505 ti,datarate = <4>; 506 ti,gain = <2>; 507 }; 508 509 /* Verdin I2C_1 ADC_3 */ 510 channel@5 { 511 reg = <5>; 512 ti,datarate = <4>; 513 ti,gain = <2>; 514 }; 515 516 /* Verdin I2C_1 ADC_2 */ 517 channel@6 { 518 reg = <6>; 519 ti,datarate = <4>; 520 ti,gain = <2>; 521 }; 522 523 /* Verdin I2C_1 ADC_1 */ 524 channel@7 { 525 reg = <7>; 526 ti,datarate = <4>; 527 ti,gain = <2>; 528 }; 529 }; 530 531 eeprom@50 { 532 compatible = "st,24c02"; 533 pagesize = <16>; 534 reg = <0x50>; 535 }; 536}; 537 538/* Verdin I2C_2_DSI */ 539&i2c2 { 540 clock-frequency = <10000>; 541 pinctrl-names = "default", "gpio"; 542 pinctrl-0 = <&pinctrl_i2c2>; 543 pinctrl-1 = <&pinctrl_i2c2_gpio>; 544 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 545 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 546 status = "disabled"; 547}; 548 549/* Verdin I2C_3_HDMI N/A */ 550 551/* Verdin I2C_4_CSI */ 552&i2c3 { 553 clock-frequency = <400000>; 554 pinctrl-names = "default", "gpio"; 555 pinctrl-0 = <&pinctrl_i2c3>; 556 pinctrl-1 = <&pinctrl_i2c3_gpio>; 557 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 558 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 559}; 560 561/* Verdin I2C_1 */ 562&i2c4 { 563 clock-frequency = <400000>; 564 pinctrl-names = "default", "gpio"; 565 pinctrl-0 = <&pinctrl_i2c4>; 566 pinctrl-1 = <&pinctrl_i2c4_gpio>; 567 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 568 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 569 570 gpio_expander_21: gpio-expander@21 { 571 compatible = "nxp,pcal6416"; 572 #gpio-cells = <2>; 573 gpio-controller; 574 reg = <0x21>; 575 vcc-supply = <®_3p3v>; 576 status = "disabled"; 577 }; 578 579 lvds_ti_sn65dsi84: bridge@2c { 580 compatible = "ti,sn65dsi84"; 581 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 582 /* Verdin GPIO_10_DSI (SODIMM 21) */ 583 enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 586 reg = <0x2c>; 587 status = "disabled"; 588 }; 589 590 /* Current measurement into module VCC */ 591 hwmon: hwmon@40 { 592 compatible = "ti,ina219"; 593 reg = <0x40>; 594 shunt-resistor = <10000>; 595 status = "disabled"; 596 }; 597 598 hdmi_lontium_lt8912: hdmi@48 { 599 compatible = "lontium,lt8912b"; 600 pinctrl-names = "default"; 601 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 602 reg = <0x48>; 603 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 604 /* Verdin GPIO_10_DSI (SODIMM 21) */ 605 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; 606 status = "disabled"; 607 }; 608 609 atmel_mxt_ts: touch@4a { 610 compatible = "atmel,maxtouch"; 611 /* 612 * Verdin GPIO_9_DSI 613 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) 614 */ 615 interrupt-parent = <&gpio3>; 616 interrupts = <15 IRQ_TYPE_EDGE_FALLING>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 619 reg = <0x4a>; 620 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 621 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 622 status = "disabled"; 623 }; 624 625 /* Temperature sensor on carrier board */ 626 hwmon_temp: sensor@4f { 627 compatible = "ti,tmp75c"; 628 reg = <0x4f>; 629 status = "disabled"; 630 }; 631 632 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 633 eeprom_display_adapter: eeprom@50 { 634 compatible = "st,24c02"; 635 pagesize = <16>; 636 reg = <0x50>; 637 status = "disabled"; 638 }; 639 640 /* EEPROM on carrier board */ 641 eeprom_carrier_board: eeprom@57 { 642 compatible = "st,24c02"; 643 pagesize = <16>; 644 reg = <0x57>; 645 status = "disabled"; 646 }; 647}; 648 649/* Verdin PCIE_1 */ 650&pcie0 { 651 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 652 <&clk IMX8MM_CLK_PCIE1_CTRL>; 653 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 654 <&clk IMX8MM_SYS_PLL2_250M>; 655 assigned-clock-rates = <10000000>, <250000000>; 656 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 657 <&clk IMX8MM_CLK_PCIE1_PHY>; 658 clock-names = "pcie", "pcie_aux", "pcie_bus"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pinctrl_pcie0>; 661 /* PCIE_1_RESET# (SODIMM 244) */ 662 reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 663}; 664 665&pcie_phy { 666 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 667 fsl,clkreq-unsupported; 668 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 669 fsl,tx-deemph-gen1 = <0x2d>; 670 fsl,tx-deemph-gen2 = <0xf>; 671}; 672 673/* Verdin PWM_3_DSI */ 674&pwm1 { 675 pinctrl-names = "default"; 676 pinctrl-0 = <&pinctrl_pwm_1>; 677 #pwm-cells = <3>; 678}; 679 680/* Verdin PWM_1 */ 681&pwm2 { 682 pinctrl-names = "default"; 683 pinctrl-0 = <&pinctrl_pwm_2>; 684 #pwm-cells = <3>; 685}; 686 687/* Verdin PWM_2 */ 688&pwm3 { 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pinctrl_pwm_3>; 691 #pwm-cells = <3>; 692}; 693 694/* Verdin I2S_1 */ 695&sai2 { 696 #sound-dai-cells = <0>; 697 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 698 assigned-clock-rates = <24576000>; 699 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pinctrl_sai2>; 702}; 703 704&snvs_pwrkey { 705 status = "okay"; 706}; 707 708/* Verdin UART_3, used as the Linux console */ 709&uart1 { 710 pinctrl-names = "default"; 711 pinctrl-0 = <&pinctrl_uart1>; 712}; 713 714/* Verdin UART_1 */ 715&uart2 { 716 pinctrl-names = "default"; 717 pinctrl-0 = <&pinctrl_uart2>; 718 uart-has-rtscts; 719}; 720 721/* Verdin UART_2 */ 722&uart3 { 723 pinctrl-names = "default"; 724 pinctrl-0 = <&pinctrl_uart3>; 725 uart-has-rtscts; 726}; 727 728/* 729 * Verdin UART_4 730 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS 731 */ 732&uart4 { 733 pinctrl-names = "default"; 734 pinctrl-0 = <&pinctrl_uart4>; 735}; 736 737/* Verdin USB_1 */ 738&usbotg1 { 739 adp-disable; 740 dr_mode = "otg"; 741 hnp-disable; 742 over-current-active-low; 743 samsung,picophy-dc-vol-level-adjust = <7>; 744 samsung,picophy-pre-emp-curr-control = <3>; 745 srp-disable; 746 vbus-supply = <®_usb_otg1_vbus>; 747}; 748 749/* Verdin USB_2 */ 750&usbotg2 { 751 dr_mode = "host"; 752 over-current-active-low; 753 samsung,picophy-dc-vol-level-adjust = <7>; 754 samsung,picophy-pre-emp-curr-control = <3>; 755 vbus-supply = <®_usb_otg2_vbus>; 756}; 757 758&usbphynop1 { 759 vcc-supply = <®_vdd_3v3>; 760}; 761 762&usbphynop2 { 763 power-domains = <&pgc_otg2>; 764 vcc-supply = <®_vdd_3v3>; 765}; 766 767/* On-module eMMC */ 768&usdhc1 { 769 bus-width = <8>; 770 keep-power-in-suspend; 771 non-removable; 772 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 773 pinctrl-0 = <&pinctrl_usdhc1>; 774 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 775 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 776 status = "okay"; 777}; 778 779/* Verdin SD_1 */ 780&usdhc2 { 781 bus-width = <4>; 782 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 783 disable-wp; 784 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 785 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 786 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 787 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 788 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 789 vmmc-supply = <®_usdhc2_vmmc>; 790}; 791 792&wdog1 { 793 fsl,ext-reset-output; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&pinctrl_wdog>; 796 status = "okay"; 797}; 798 799&iomuxc { 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 802 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 803 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 804 <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 805 <&pinctrl_pmic_tpm_ena>; 806 807 pinctrl_can1_int: can1intgrp { 808 fsl,pins = 809 <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */ 810 }; 811 812 pinctrl_can2_int: can2intgrp { 813 fsl,pins = 814 <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */ 815 }; 816 817 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 818 fsl,pins = 819 <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */ 820 }; 821 822 pinctrl_ecspi2: ecspi2grp { 823 fsl,pins = 824 <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */ 825 <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */ 826 <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */ 827 <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */ 828 }; 829 830 pinctrl_ecspi3: ecspi3grp { 831 fsl,pins = 832 <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */ 833 <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */ 834 <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */ 835 <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */ 836 <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */ 837 }; 838 839 pinctrl_fec1: fec1grp { 840 fsl,pins = 841 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 842 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 843 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 844 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 845 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 846 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 847 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 848 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 849 <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>, 850 <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>, 851 <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>, 852 <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>, 853 <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>, 854 <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>, 855 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>; 856 }; 857 858 pinctrl_fec1_sleep: fec1-sleepgrp { 859 fsl,pins = 860 <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>, 861 <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>, 862 <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>, 863 <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>, 864 <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>, 865 <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>, 866 <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>, 867 <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>, 868 <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>, 869 <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>, 870 <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>, 871 <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>, 872 <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>, 873 <MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>, 874 <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>; 875 }; 876 877 pinctrl_flexspi0: flexspi0grp { 878 fsl,pins = 879 <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */ 880 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */ 881 <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */ 882 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */ 883 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */ 884 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */ 885 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */ 886 <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */ 887 }; 888 889 pinctrl_gpio1: gpio1grp { 890 fsl,pins = 891 <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */ 892 }; 893 894 pinctrl_gpio2: gpio2grp { 895 fsl,pins = 896 <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */ 897 }; 898 899 pinctrl_gpio3: gpio3grp { 900 fsl,pins = 901 <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */ 902 }; 903 904 pinctrl_gpio4: gpio4grp { 905 fsl,pins = 906 <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */ 907 }; 908 909 pinctrl_gpio5: gpio5grp { 910 fsl,pins = 911 <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */ 912 }; 913 914 pinctrl_gpio6: gpio6grp { 915 fsl,pins = 916 <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */ 917 }; 918 919 pinctrl_gpio7: gpio7grp { 920 fsl,pins = 921 <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */ 922 }; 923 924 pinctrl_gpio8: gpio8grp { 925 fsl,pins = 926 <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */ 927 }; 928 929 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 930 pinctrl_gpio_9_dsi: gpio9dsigrp { 931 fsl,pins = 932 <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */ 933 }; 934 935 /* Verdin GPIO_10_DSI (pulled-up as active-low) */ 936 pinctrl_gpio_10_dsi: gpio10dsigrp { 937 fsl,pins = 938 <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */ 939 }; 940 941 pinctrl_gpio_hog1: gpiohog1grp { 942 fsl,pins = 943 <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */ 944 <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */ 945 <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */ 946 <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */ 947 <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */ 948 <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */ 949 <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */ 950 <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */ 951 <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */ 952 <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */ 953 <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */ 954 <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */ 955 <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */ 956 <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */ 957 <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */ 958 }; 959 960 pinctrl_gpio_hog2: gpiohog2grp { 961 fsl,pins = 962 <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */ 963 }; 964 965 pinctrl_gpio_hog3: gpiohog3grp { 966 fsl,pins = 967 <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */ 968 <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */ 969 }; 970 971 pinctrl_gpio_keys: gpiokeysgrp { 972 fsl,pins = 973 <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */ 974 }; 975 976 /* On-module I2C */ 977 pinctrl_i2c1: i2c1grp { 978 fsl,pins = 979 <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */ 980 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */ 981 }; 982 983 pinctrl_i2c1_gpio: i2c1gpiogrp { 984 fsl,pins = 985 <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */ 986 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */ 987 }; 988 989 /* Verdin I2C_4_CSI */ 990 pinctrl_i2c2: i2c2grp { 991 fsl,pins = 992 <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */ 993 <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */ 994 }; 995 996 pinctrl_i2c2_gpio: i2c2gpiogrp { 997 fsl,pins = 998 <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */ 999 <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */ 1000 }; 1001 1002 /* Verdin I2C_2_DSI */ 1003 pinctrl_i2c3: i2c3grp { 1004 fsl,pins = 1005 <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */ 1006 <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */ 1007 }; 1008 1009 pinctrl_i2c3_gpio: i2c3gpiogrp { 1010 fsl,pins = 1011 <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */ 1012 <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */ 1013 }; 1014 1015 /* Verdin I2C_1 */ 1016 pinctrl_i2c4: i2c4grp { 1017 fsl,pins = 1018 <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */ 1019 <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */ 1020 }; 1021 1022 pinctrl_i2c4_gpio: i2c4gpiogrp { 1023 fsl,pins = 1024 <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */ 1025 <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */ 1026 }; 1027 1028 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1029 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1030 fsl,pins = 1031 <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */ 1032 }; 1033 1034 /* Verdin I2S_2_D_OUT shared with SAI5 */ 1035 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1036 fsl,pins = 1037 <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */ 1038 }; 1039 1040 pinctrl_pcie0: pcie0grp { 1041 fsl,pins = 1042 <MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6>, /* SODIMM 244 */ 1043 /* PMIC_EN_PCIe_CLK, unused */ 1044 <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6>; 1045 }; 1046 1047 pinctrl_pmic: pmicirqgrp { 1048 fsl,pins = 1049 <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */ 1050 }; 1051 1052 /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ 1053 pinctrl_pwm_1: pwm1grp { 1054 fsl,pins = 1055 <MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6>; /* SODIMM 19 */ 1056 }; 1057 1058 pinctrl_pwm_2: pwm2grp { 1059 fsl,pins = 1060 <MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6>; /* SODIMM 15 */ 1061 }; 1062 1063 pinctrl_pwm_3: pwm3grp { 1064 fsl,pins = 1065 <MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6>; /* SODIMM 16 */ 1066 }; 1067 1068 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ 1069 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { 1070 fsl,pins = 1071 <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */ 1072 }; 1073 1074 pinctrl_reg_eth: regethgrp { 1075 fsl,pins = 1076 <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */ 1077 }; 1078 1079 pinctrl_reg_usb1_en: regusb1engrp { 1080 fsl,pins = 1081 <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */ 1082 }; 1083 1084 pinctrl_reg_usb2_en: regusb2engrp { 1085 fsl,pins = 1086 <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */ 1087 }; 1088 1089 pinctrl_sai2: sai2grp { 1090 fsl,pins = 1091 <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */ 1092 <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */ 1093 <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */ 1094 <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */ 1095 <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */ 1096 }; 1097 1098 pinctrl_sai5: sai5grp { 1099 fsl,pins = 1100 <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */ 1101 <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */ 1102 <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */ 1103 <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */ 1104 }; 1105 1106 /* control signal for optional ATTPM20P or SE050 */ 1107 pinctrl_pmic_tpm_ena: pmictpmenagrp { 1108 fsl,pins = 1109 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1110 }; 1111 1112 pinctrl_tsp: tspgrp { 1113 fsl,pins = 1114 <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */ 1115 <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */ 1116 <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */ 1117 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */ 1118 <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */ 1119 }; 1120 1121 pinctrl_uart1: uart1grp { 1122 fsl,pins = 1123 <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */ 1124 <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */ 1125 }; 1126 1127 pinctrl_uart2: uart2grp { 1128 fsl,pins = 1129 <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */ 1130 <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */ 1131 <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */ 1132 <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */ 1133 }; 1134 1135 pinctrl_uart3: uart3grp { 1136 fsl,pins = 1137 <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */ 1138 <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */ 1139 <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */ 1140 <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */ 1141 }; 1142 1143 pinctrl_uart4: uart4grp { 1144 fsl,pins = 1145 <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */ 1146 <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */ 1147 }; 1148 1149 pinctrl_usdhc1: usdhc1grp { 1150 fsl,pins = 1151 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190>, 1152 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0>, 1153 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0>, 1154 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0>, 1155 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0>, 1156 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>, 1157 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0>, 1158 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0>, 1159 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0>, 1160 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0>, 1161 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1162 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190>; 1163 }; 1164 1165 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1166 fsl,pins = 1167 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194>, 1168 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4>, 1169 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4>, 1170 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4>, 1171 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4>, 1172 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>, 1173 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4>, 1174 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4>, 1175 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4>, 1176 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4>, 1177 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1178 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194>; 1179 }; 1180 1181 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1182 fsl,pins = 1183 <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196>, 1184 <MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6>, 1185 <MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6>, 1186 <MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6>, 1187 <MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6>, 1188 <MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>, 1189 <MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6>, 1190 <MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6>, 1191 <MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6>, 1192 <MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6>, 1193 <MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d1>, 1194 <MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196>; 1195 }; 1196 1197 pinctrl_usdhc2_cd: usdhc2cdgrp { 1198 fsl,pins = 1199 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */ 1200 }; 1201 1202 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1203 fsl,pins = 1204 <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */ 1205 }; 1206 1207 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1208 fsl,pins = 1209 <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */ 1210 }; 1211 1212 /* 1213 * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the 1214 * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. 1215 */ 1216 pinctrl_usdhc2: usdhc2grp { 1217 fsl,pins = 1218 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1219 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */ 1220 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */ 1221 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */ 1222 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */ 1223 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */ 1224 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */ 1225 }; 1226 1227 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1228 fsl,pins = 1229 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1230 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>, 1231 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>, 1232 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>, 1233 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>, 1234 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>, 1235 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>; 1236 }; 1237 1238 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1239 fsl,pins = 1240 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>, 1241 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>, 1242 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>, 1243 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>, 1244 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>, 1245 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>, 1246 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>; 1247 }; 1248 1249 /* Avoid backfeeding with removed card power */ 1250 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1251 fsl,pins = 1252 <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>, 1253 <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>, 1254 <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>, 1255 <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>, 1256 <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>, 1257 <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>, 1258 <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>; 1259 }; 1260 1261 /* 1262 * On-module Wi-Fi/BT or type specific SDHC interface 1263 * (e.g. on X52 extension slot of Verdin Development Board) 1264 */ 1265 pinctrl_usdhc3: usdhc3grp { 1266 fsl,pins = 1267 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>, 1268 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>, 1269 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>, 1270 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>, 1271 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>, 1272 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>; 1273 }; 1274 1275 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1276 fsl,pins = 1277 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>, 1278 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>, 1279 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>, 1280 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>, 1281 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>, 1282 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>; 1283 }; 1284 1285 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1286 fsl,pins = 1287 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>, 1288 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>, 1289 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>, 1290 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>, 1291 <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>, 1292 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>; 1293 }; 1294 1295 pinctrl_wdog: wdoggrp { 1296 fsl,pins = 1297 <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */ 1298 }; 1299 1300 pinctrl_wifi_ctrl: wifictrlgrp { 1301 fsl,pins = 1302 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */ 1303 <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */ 1304 <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */ 1305 }; 1306 1307 pinctrl_wifi_i2s: bti2sgrp { 1308 fsl,pins = 1309 <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */ 1310 <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */ 1311 <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */ 1312 <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */ 1313 }; 1314 1315 pinctrl_wifi_pwr_en: wifipwrengrp { 1316 fsl,pins = 1317 <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */ 1318 }; 1319}; 1320