1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Collabora Ltd.
4 * Copyright 2021 BSH Hausgeraete GmbH
5 */
6
7/dts-v1/;
8
9#include "imx8mn.dtsi"
10#include "imx8mn-bsh-smm-s2-display.dtsi"
11
12/ {
13	chosen {
14		stdout-path = &uart4;
15	};
16
17	fec_supply: fec-supply-en {
18		compatible = "regulator-fixed";
19		vin-supply = <&buck4_reg>;
20		regulator-name = "tja1101_en";
21		regulator-min-microvolt = <3300000>;
22		regulator-max-microvolt = <3300000>;
23		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
24		enable-active-high;
25	};
26
27	usdhc2_pwrseq: usdhc2-pwrseq {
28		compatible = "mmc-pwrseq-simple";
29		pinctrl-names = "default";
30		pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
31		reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
32	};
33};
34
35&A53_0 {
36	cpu-supply = <&buck2_reg>;
37};
38
39&A53_1 {
40	cpu-supply = <&buck2_reg>;
41};
42
43&A53_2 {
44	cpu-supply = <&buck2_reg>;
45};
46
47&A53_3 {
48	cpu-supply = <&buck2_reg>;
49};
50
51&ecspi2 {
52	pinctrl-names = "default";
53	pinctrl-0 = <&pinctrl_espi2>;
54	status = "okay";
55};
56
57&fec1 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&pinctrl_fec1>;
60	phy-mode = "rmii";
61	phy-handle = <&ethphy0>;
62	phy-supply = <&fec_supply>;
63	fsl,magic-packet;
64	status = "okay";
65
66	mdio {
67		#address-cells = <1>;
68		#size-cells = <0>;
69
70		ethphy0: ethernet-phy@0 {
71			compatible = "ethernet-phy-ieee802.3-c22";
72			reg = <0>;
73			reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
74			reset-assert-us = <20>;
75			reset-deassert-us = <2000>;
76		};
77	};
78};
79
80&i2c1 {
81	clock-frequency = <400000>;
82	pinctrl-names = "default";
83	pinctrl-0 = <&pinctrl_i2c1>;
84	status = "okay";
85
86	bd71847: pmic@4b {
87		compatible = "rohm,bd71847";
88		reg = <0x4b>;
89		pinctrl-names = "default";
90		pinctrl-0 = <&pinctrl_pmic>;
91		interrupt-parent = <&gpio1>;
92		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
93		rohm,reset-snvs-powered;
94
95		#clock-cells = <0>;
96		clocks = <&osc_32k>;
97		clock-output-names = "clk-32k-out";
98
99		regulators {
100			buck1_reg: BUCK1 {
101				/* PMIC_BUCK1 - VDD_SOC */
102				regulator-name = "buck1";
103				regulator-min-microvolt = <700000>;
104				regulator-max-microvolt = <1300000>;
105				regulator-boot-on;
106				regulator-always-on;
107				regulator-ramp-delay = <1250>;
108			};
109
110			buck2_reg: BUCK2 {
111				/* PMIC_BUCK2 - VDD_ARM */
112				regulator-name = "buck2";
113				regulator-min-microvolt = <700000>;
114				regulator-max-microvolt = <1300000>;
115				regulator-boot-on;
116				regulator-always-on;
117				regulator-ramp-delay = <1250>;
118			};
119
120			buck3_reg: BUCK3 {
121				/* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
122				regulator-name = "buck3";
123				regulator-min-microvolt = <700000>;
124				regulator-max-microvolt = <1350000>;
125				regulator-boot-on;
126				regulator-always-on;
127			};
128
129			buck4_reg: BUCK4 {
130				/* PMIC_BUCK6 - VDD_3V3 */
131				regulator-name = "buck4";
132				regulator-min-microvolt = <3000000>;
133				regulator-max-microvolt = <3300000>;
134				regulator-boot-on;
135				regulator-always-on;
136			};
137
138			buck5_reg: BUCK5 {
139				/* PMIC_BUCK7 - VDD_1V8 */
140				regulator-name = "buck5";
141				regulator-min-microvolt = <1605000>;
142				regulator-max-microvolt = <1995000>;
143				regulator-boot-on;
144				regulator-always-on;
145			};
146
147			buck6_reg: BUCK6 {
148				/* PMIC_BUCK8 - NVCC_DRAM */
149				regulator-name = "buck6";
150				regulator-min-microvolt = <800000>;
151				regulator-max-microvolt = <1400000>;
152				regulator-boot-on;
153				regulator-always-on;
154			};
155
156			ldo1_reg: LDO1 {
157				/* PMIC_LDO1 - NVCC_SNVS_1V8 */
158				regulator-name = "ldo1";
159				regulator-min-microvolt = <1600000>;
160				regulator-max-microvolt = <1900000>;
161				regulator-boot-on;
162				regulator-always-on;
163			};
164
165			ldo2_reg: LDO2 {
166				/* PMIC_LDO2 - VDD_SNVS_0V8 */
167				regulator-name = "ldo2";
168				regulator-min-microvolt = <800000>;
169				regulator-max-microvolt = <900000>;
170				regulator-boot-on;
171				regulator-always-on;
172			};
173
174			ldo3_reg: LDO3 {
175				/* PMIC_LDO3 - VDDA_1V8 */
176				regulator-name = "ldo3";
177				regulator-min-microvolt = <1800000>;
178				regulator-max-microvolt = <3300000>;
179				regulator-boot-on;
180				regulator-always-on;
181			};
182
183			ldo4_reg: LDO4 {
184				/* PMIC_LDO4 - VDD_MIPI_0V9 */
185				regulator-name = "ldo4";
186				regulator-min-microvolt = <900000>;
187				regulator-max-microvolt = <1800000>;
188				regulator-boot-on;
189				regulator-always-on;
190			};
191
192			ldo6_reg: LDO6 {
193				/* PMIC_LDO6 - VDD_MIPI_1V2 */
194				regulator-name = "ldo6";
195				regulator-min-microvolt = <900000>;
196				regulator-max-microvolt = <1800000>;
197				regulator-boot-on;
198				regulator-always-on;
199			};
200		};
201	};
202};
203
204&i2c3 {
205	clock-frequency = <400000>;
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_i2c3>;
208	status = "okay";
209};
210
211&i2c4 {
212	clock-frequency = <400000>;
213	pinctrl-names = "default";
214	pinctrl-0 = <&pinctrl_i2c4>;
215	status = "okay";
216};
217
218&uart2 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_uart2>;
221	status = "okay";
222};
223
224&uart3 {
225	pinctrl-names = "default";
226	pinctrl-0 = <&pinctrl_uart3>;
227	assigned-clocks = <&clk IMX8MN_CLK_UART3>;
228	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
229	uart-has-rtscts;
230	status = "okay";
231
232	bluetooth {
233		compatible = "brcm,bcm43438-bt";
234		pinctrl-names = "default";
235		pinctrl-0 = <&pinctrl_bluetooth>;
236		shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
237		device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
238		host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
239		max-speed = <3000000>;
240	};
241};
242
243/* Console */
244&uart4 {
245	pinctrl-names = "default";
246	pinctrl-0 = <&pinctrl_uart4>;
247	status = "okay";
248};
249
250&usbotg1 {
251	dr_mode = "peripheral";
252	disable-over-current;
253	status = "okay";
254};
255
256&usdhc2 {
257	#address-cells = <1>;
258	#size-cells = <0>;
259	pinctrl-names = "default", "state_100mhz", "state_200mhz";
260	pinctrl-0 = <&pinctrl_usdhc2>;
261	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
262	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
263	mmc-pwrseq = <&usdhc2_pwrseq>;
264	bus-width = <4>;
265	non-removable;
266	status = "okay";
267
268	brcmf: bcrmf@1 {
269		compatible = "brcm,bcm4329-fmac";
270		reg = <1>;
271		pinctrl-names = "default";
272		pinctrl-0 = <&pinctrl_wlan>;
273		interrupt-parent = <&gpio1>;
274		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
275		interrupt-names = "host-wake";
276	};
277};
278
279&wdog1 {
280	pinctrl-names = "default";
281	pinctrl-0 = <&pinctrl_wdog>;
282	fsl,ext-reset-output;
283	status = "okay";
284};
285
286&iomuxc {
287	pinctrl_bluetooth: bluetoothgrp {
288		fsl,pins = <
289			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x044	/* BT_REG_ON */
290			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x046	/* BT_DEV_WAKE */
291			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x090	/* BT_HOST_WAKE */
292		>;
293	};
294
295	pinctrl_espi2: espi2grp {
296		fsl,pins = <
297			MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x082
298			MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x082
299			MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x082
300			MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0		0x040
301		>;
302	};
303
304	pinctrl_fec1: fec1grp {
305		fsl,pins = <
306			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x002
307			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x002
308			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x090
309			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x090
310			MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER		0x090
311			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x016
312			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x016
313			MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x016
314			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x016
315			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x090
316			MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER		0x016
317			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12		0x150	/* RMII_INT - ENET_INT */
318			MX8MN_IOMUXC_SD2_WP_GPIO2_IO20			0x150	/* RMII_EN - ENET_EN */
319			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x016	/* RMII_WAKE - GPIO_ENET_WAKE */
320			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x016	/* RMII_RESET - GPIO_ENET_RST */
321		>;
322	};
323
324	pinctrl_i2c1: i2c1grp {
325		fsl,pins = <
326			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL			0x400000c2
327			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA			0x400000c2
328		>;
329	};
330
331	pinctrl_i2c3: i2c3grp {
332		fsl,pins = <
333			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL			0x400000c2
334			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA			0x400000c2
335		>;
336	};
337
338	pinctrl_i2c4: i2c4grp {
339		fsl,pins = <
340			MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL			0x400000c2
341			MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA			0x400000c2
342		>;
343	};
344
345	pinctrl_pmic: pmicirqgrp {
346		fsl,pins = <
347			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x040
348		>;
349	};
350
351	pinctrl_uart2: uart2grp {
352		fsl,pins = <
353			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX		0x040
354			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX		0x040
355		>;
356	};
357
358	pinctrl_uart3: uart3grp {
359		fsl,pins = <
360			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX		0x040
361			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX		0x040
362			MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x040
363			MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x040
364		>;
365	};
366
367	pinctrl_uart4: uart4grp {
368		fsl,pins = <
369			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX		0x040
370			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX		0x040
371		>;
372	};
373
374	pinctrl_usdhc2: usdhc2grp {
375		fsl,pins = <
376			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x090
377			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d0
378			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d0
379			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d0
380			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d0
381			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d0
382		>;
383	};
384
385	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
386		fsl,pins = <
387			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x094
388			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d4
389			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d4
390			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d4
391			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d4
392			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d4
393		>;
394	};
395
396	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
397		fsl,pins = <
398			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK			0x096
399			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD			0x0d6
400			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x0d6
401			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x0d6
402			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x0d6
403			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x0d6
404		>;
405	};
406
407	pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
408		fsl,pins = <
409			MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27		0x040	/* WL_REG_ON */
410		>;
411	};
412
413	pinctrl_wdog: wdoggrp {
414		fsl,pins = <
415			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x046
416		>;
417	};
418
419	pinctrl_wlan: wlangrp {
420		fsl,pins = <
421			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x0d6	/* GPIO_0 - WIFI_GPIO_0 */
422			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x0d6	/* GPIO_1 - WIFI_GPIO_1 */
423			MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4		0x0d6	/* BT_GPIO_5 - WIFI_GPIO_5 */
424			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4			0x0d6	/* I2S_CLK - WIFI_GPIO_6 */
425		>;
426	};
427};
428