1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mn-clock.h> 7#include <dt-bindings/power/imx8mn-power.h> 8#include <dt-bindings/reset/imx8mq-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx8mn-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; 66 clocks = <&clk IMX8MN_CLK_ARM>; 67 enable-method = "psci"; 68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 75 operating-points-v2 = <&a53_opp_table>; 76 nvmem-cells = <&cpu_speed_grade>; 77 nvmem-cell-names = "speed_grade"; 78 cpu-idle-states = <&cpu_pd_wait>; 79 #cooling-cells = <2>; 80 }; 81 82 A53_1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x1>; 86 clock-latency = <61036>; 87 clocks = <&clk IMX8MN_CLK_ARM>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 cpu-idle-states = <&cpu_pd_wait>; 98 #cooling-cells = <2>; 99 }; 100 101 A53_2: cpu@2 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x2>; 105 clock-latency = <61036>; 106 clocks = <&clk IMX8MN_CLK_ARM>; 107 enable-method = "psci"; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&A53_L2>; 115 operating-points-v2 = <&a53_opp_table>; 116 cpu-idle-states = <&cpu_pd_wait>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_3: cpu@3 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x3>; 124 clock-latency = <61036>; 125 clocks = <&clk IMX8MN_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 cpu-idle-states = <&cpu_pd_wait>; 136 #cooling-cells = <2>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-level = <2>; 142 cache-unified; 143 cache-size = <0x80000>; 144 cache-line-size = <64>; 145 cache-sets = <512>; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-1200000000 { 154 opp-hz = /bits/ 64 <1200000000>; 155 opp-microvolt = <850000>; 156 opp-supported-hw = <0xb00>, <0x7>; 157 clock-latency-ns = <150000>; 158 opp-suspend; 159 }; 160 161 opp-1400000000 { 162 opp-hz = /bits/ 64 <1400000000>; 163 opp-microvolt = <950000>; 164 opp-supported-hw = <0x300>, <0x7>; 165 clock-latency-ns = <150000>; 166 opp-suspend; 167 }; 168 169 opp-1500000000 { 170 opp-hz = /bits/ 64 <1500000000>; 171 opp-microvolt = <1000000>; 172 opp-supported-hw = <0x100>, <0x3>; 173 clock-latency-ns = <150000>; 174 opp-suspend; 175 }; 176 }; 177 178 osc_32k: clock-osc-32k { 179 compatible = "fixed-clock"; 180 #clock-cells = <0>; 181 clock-frequency = <32768>; 182 clock-output-names = "osc_32k"; 183 }; 184 185 osc_24m: clock-osc-24m { 186 compatible = "fixed-clock"; 187 #clock-cells = <0>; 188 clock-frequency = <24000000>; 189 clock-output-names = "osc_24m"; 190 }; 191 192 clk_ext1: clock-ext1 { 193 compatible = "fixed-clock"; 194 #clock-cells = <0>; 195 clock-frequency = <133000000>; 196 clock-output-names = "clk_ext1"; 197 }; 198 199 clk_ext2: clock-ext2 { 200 compatible = "fixed-clock"; 201 #clock-cells = <0>; 202 clock-frequency = <133000000>; 203 clock-output-names = "clk_ext2"; 204 }; 205 206 clk_ext3: clock-ext3 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <133000000>; 210 clock-output-names = "clk_ext3"; 211 }; 212 213 clk_ext4: clock-ext4 { 214 compatible = "fixed-clock"; 215 #clock-cells = <0>; 216 clock-frequency = <133000000>; 217 clock-output-names = "clk_ext4"; 218 }; 219 220 pmu { 221 compatible = "arm,cortex-a53-pmu"; 222 interrupts = <GIC_PPI 7 223 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 224 }; 225 226 psci { 227 compatible = "arm,psci-1.0"; 228 method = "smc"; 229 }; 230 231 thermal-zones { 232 cpu-thermal { 233 polling-delay-passive = <250>; 234 polling-delay = <2000>; 235 thermal-sensors = <&tmu>; 236 trips { 237 cpu_alert0: trip0 { 238 temperature = <85000>; 239 hysteresis = <2000>; 240 type = "passive"; 241 }; 242 243 cpu_crit0: trip1 { 244 temperature = <95000>; 245 hysteresis = <2000>; 246 type = "critical"; 247 }; 248 }; 249 250 cooling-maps { 251 map0 { 252 trip = <&cpu_alert0>; 253 cooling-device = 254 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 255 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 256 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 257 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 258 }; 259 }; 260 }; 261 }; 262 263 timer { 264 compatible = "arm,armv8-timer"; 265 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 266 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 267 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 268 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 269 clock-frequency = <8000000>; 270 arm,no-tick-in-suspend; 271 }; 272 273 soc: soc@0 { 274 compatible = "fsl,imx8mn-soc", "simple-bus"; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges = <0x0 0x0 0x0 0x3e000000>; 278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 279 nvmem-cells = <&imx8mn_uid>; 280 nvmem-cell-names = "soc_unique_id"; 281 282 aips1: bus@30000000 { 283 compatible = "fsl,aips-bus", "simple-bus"; 284 reg = <0x30000000 0x400000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 spba2: spba-bus@30000000 { 290 compatible = "fsl,spba-bus", "simple-bus"; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 reg = <0x30000000 0x100000>; 294 ranges; 295 296 sai2: sai@30020000 { 297 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 298 reg = <0x30020000 0x10000>; 299 #sound-dai-cells = <0>; 300 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clk IMX8MN_CLK_SAI2_IPG>, 302 <&clk IMX8MN_CLK_DUMMY>, 303 <&clk IMX8MN_CLK_SAI2_ROOT>, 304 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 305 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 306 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 307 dma-names = "rx", "tx"; 308 status = "disabled"; 309 }; 310 311 sai3: sai@30030000 { 312 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 313 reg = <0x30030000 0x10000>; 314 #sound-dai-cells = <0>; 315 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clk IMX8MN_CLK_SAI3_IPG>, 317 <&clk IMX8MN_CLK_DUMMY>, 318 <&clk IMX8MN_CLK_SAI3_ROOT>, 319 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 320 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 321 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 }; 325 326 sai5: sai@30050000 { 327 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 328 reg = <0x30050000 0x10000>; 329 #sound-dai-cells = <0>; 330 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk IMX8MN_CLK_SAI5_IPG>, 332 <&clk IMX8MN_CLK_DUMMY>, 333 <&clk IMX8MN_CLK_SAI5_ROOT>, 334 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 335 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 336 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 337 dma-names = "rx", "tx"; 338 fsl,shared-interrupt; 339 fsl,dataline = <0 0xf 0xf>; 340 status = "disabled"; 341 }; 342 343 sai6: sai@30060000 { 344 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 345 reg = <0x30060000 0x10000>; 346 #sound-dai-cells = <0>; 347 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clk IMX8MN_CLK_SAI6_IPG>, 349 <&clk IMX8MN_CLK_DUMMY>, 350 <&clk IMX8MN_CLK_SAI6_ROOT>, 351 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 352 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 353 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 354 dma-names = "rx", "tx"; 355 status = "disabled"; 356 }; 357 358 micfil: audio-controller@30080000 { 359 compatible = "fsl,imx8mm-micfil"; 360 reg = <0x30080000 0x10000>; 361 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk IMX8MN_CLK_PDM_IPG>, 366 <&clk IMX8MN_CLK_PDM_ROOT>, 367 <&clk IMX8MN_AUDIO_PLL1_OUT>, 368 <&clk IMX8MN_AUDIO_PLL2_OUT>, 369 <&clk IMX8MN_CLK_EXT3>; 370 clock-names = "ipg_clk", "ipg_clk_app", 371 "pll8k", "pll11k", "clkext3"; 372 dmas = <&sdma2 24 25 0x80000000>; 373 dma-names = "rx"; 374 status = "disabled"; 375 }; 376 377 spdif1: spdif@30090000 { 378 compatible = "fsl,imx35-spdif"; 379 reg = <0x30090000 0x10000>; 380 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ 382 <&clk IMX8MN_CLK_24M>, /* rxtx0 */ 383 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ 384 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ 385 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ 386 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ 387 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ 388 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ 389 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ 390 <&clk IMX8MN_CLK_DUMMY>; /* spba */ 391 clock-names = "core", "rxtx0", 392 "rxtx1", "rxtx2", 393 "rxtx3", "rxtx4", 394 "rxtx5", "rxtx6", 395 "rxtx7", "spba"; 396 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 397 dma-names = "rx", "tx"; 398 status = "disabled"; 399 }; 400 401 sai7: sai@300b0000 { 402 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai"; 403 reg = <0x300b0000 0x10000>; 404 #sound-dai-cells = <0>; 405 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MN_CLK_SAI7_IPG>, 407 <&clk IMX8MN_CLK_DUMMY>, 408 <&clk IMX8MN_CLK_SAI7_ROOT>, 409 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; 410 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 411 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 412 dma-names = "rx", "tx"; 413 status = "disabled"; 414 }; 415 416 easrc: easrc@300c0000 { 417 compatible = "fsl,imx8mn-easrc"; 418 reg = <0x300c0000 0x10000>; 419 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; 421 clock-names = "mem"; 422 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 423 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 424 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 425 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 426 dma-names = "ctx0_rx", "ctx0_tx", 427 "ctx1_rx", "ctx1_tx", 428 "ctx2_rx", "ctx2_tx", 429 "ctx3_rx", "ctx3_tx"; 430 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 431 fsl,asrc-rate = <8000>; 432 fsl,asrc-format = <2>; 433 status = "disabled"; 434 }; 435 }; 436 437 gpio1: gpio@30200000 { 438 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 439 reg = <0x30200000 0x10000>; 440 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 gpio-ranges = <&iomuxc 0 10 30>; 448 }; 449 450 gpio2: gpio@30210000 { 451 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 452 reg = <0x30210000 0x10000>; 453 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>; 456 gpio-controller; 457 #gpio-cells = <2>; 458 interrupt-controller; 459 #interrupt-cells = <2>; 460 gpio-ranges = <&iomuxc 0 40 21>; 461 }; 462 463 gpio3: gpio@30220000 { 464 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 465 reg = <0x30220000 0x10000>; 466 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 468 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 gpio-ranges = <&iomuxc 0 61 26>; 474 }; 475 476 gpio4: gpio@30230000 { 477 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 478 reg = <0x30230000 0x10000>; 479 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>; 482 gpio-controller; 483 #gpio-cells = <2>; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 gpio-ranges = <&iomuxc 21 108 11>; 487 }; 488 489 gpio5: gpio@30240000 { 490 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; 491 reg = <0x30240000 0x10000>; 492 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 gpio-ranges = <&iomuxc 0 119 30>; 500 }; 501 502 tmu: tmu@30260000 { 503 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; 504 reg = <0x30260000 0x10000>; 505 clocks = <&clk IMX8MN_CLK_TMU_ROOT>; 506 nvmem-cells = <&tmu_calib>; 507 nvmem-cell-names = "calib"; 508 #thermal-sensor-cells = <0>; 509 }; 510 511 wdog1: watchdog@30280000 { 512 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 513 reg = <0x30280000 0x10000>; 514 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>; 516 status = "disabled"; 517 }; 518 519 wdog2: watchdog@30290000 { 520 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 521 reg = <0x30290000 0x10000>; 522 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>; 524 status = "disabled"; 525 }; 526 527 wdog3: watchdog@302a0000 { 528 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt"; 529 reg = <0x302a0000 0x10000>; 530 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>; 532 status = "disabled"; 533 }; 534 535 sdma3: dma-controller@302b0000 { 536 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 537 reg = <0x302b0000 0x10000>; 538 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, 540 <&clk IMX8MN_CLK_SDMA3_ROOT>; 541 clock-names = "ipg", "ahb"; 542 #dma-cells = <3>; 543 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 544 }; 545 546 sdma2: dma-controller@302c0000 { 547 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 548 reg = <0x302c0000 0x10000>; 549 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, 551 <&clk IMX8MN_CLK_SDMA2_ROOT>; 552 clock-names = "ipg", "ahb"; 553 #dma-cells = <3>; 554 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 555 }; 556 557 iomuxc: pinctrl@30330000 { 558 compatible = "fsl,imx8mn-iomuxc"; 559 reg = <0x30330000 0x10000>; 560 }; 561 562 gpr: syscon@30340000 { 563 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon"; 564 reg = <0x30340000 0x10000>; 565 }; 566 567 ocotp: efuse@30350000 { 568 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; 569 reg = <0x30350000 0x10000>; 570 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 574 /* 575 * The register address below maps to the MX8M 576 * Fusemap Description Table entries this way. 577 * Assuming 578 * reg = <ADDR SIZE>; 579 * then 580 * Fuse Address = (ADDR * 4) + 0x400 581 * Note that if SIZE is greater than 4, then 582 * each subsequent fuse is located at offset 583 * +0x10 in Fusemap Description Table (e.g. 584 * reg = <0x4 0x8> describes fuses 0x410 and 585 * 0x420). 586 */ 587 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ 588 reg = <0x4 0x8>; 589 }; 590 591 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 592 reg = <0x10 4>; 593 }; 594 595 tmu_calib: calib@3c { /* 0x4f0 */ 596 reg = <0x3c 4>; 597 }; 598 599 fec_mac_address: mac-address@90 { /* 0x640 */ 600 reg = <0x90 6>; 601 }; 602 }; 603 604 anatop: clock-controller@30360000 { 605 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; 606 reg = <0x30360000 0x10000>; 607 #clock-cells = <1>; 608 }; 609 610 snvs: snvs@30370000 { 611 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 612 reg = <0x30370000 0x10000>; 613 614 snvs_rtc: snvs-rtc-lp { 615 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 616 regmap = <&snvs>; 617 offset = <0x34>; 618 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 621 clock-names = "snvs-rtc"; 622 }; 623 624 snvs_pwrkey: snvs-powerkey { 625 compatible = "fsl,sec-v4.0-pwrkey"; 626 regmap = <&snvs>; 627 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; 629 clock-names = "snvs-pwrkey"; 630 linux,keycode = <KEY_POWER>; 631 wakeup-source; 632 status = "disabled"; 633 }; 634 }; 635 636 clk: clock-controller@30380000 { 637 compatible = "fsl,imx8mn-ccm"; 638 reg = <0x30380000 0x10000>; 639 #clock-cells = <1>; 640 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 641 <&clk_ext3>, <&clk_ext4>; 642 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 643 "clk_ext3", "clk_ext4"; 644 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, 645 <&clk IMX8MN_CLK_A53_CORE>, 646 <&clk IMX8MN_CLK_NOC>, 647 <&clk IMX8MN_CLK_AUDIO_AHB>, 648 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, 649 <&clk IMX8MN_SYS_PLL3>, 650 <&clk IMX8MN_AUDIO_PLL1>, 651 <&clk IMX8MN_AUDIO_PLL2>; 652 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, 653 <&clk IMX8MN_ARM_PLL_OUT>, 654 <&clk IMX8MN_SYS_PLL3_OUT>, 655 <&clk IMX8MN_SYS_PLL1_800M>; 656 assigned-clock-rates = <0>, <0>, <0>, 657 <400000000>, 658 <400000000>, 659 <600000000>, 660 <393216000>, 661 <361267200>; 662 }; 663 664 src: reset-controller@30390000 { 665 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; 666 reg = <0x30390000 0x10000>; 667 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 668 #reset-cells = <1>; 669 }; 670 671 gpc: gpc@303a0000 { 672 compatible = "fsl,imx8mn-gpc"; 673 reg = <0x303a0000 0x10000>; 674 interrupt-parent = <&gic>; 675 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 676 677 pgc { 678 #address-cells = <1>; 679 #size-cells = <0>; 680 681 pgc_hsiomix: power-domain@0 { 682 #power-domain-cells = <0>; 683 reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; 684 clocks = <&clk IMX8MN_CLK_USB_BUS>; 685 }; 686 687 pgc_otg1: power-domain@1 { 688 #power-domain-cells = <0>; 689 reg = <IMX8MN_POWER_DOMAIN_OTG1>; 690 }; 691 692 pgc_gpumix: power-domain@2 { 693 #power-domain-cells = <0>; 694 reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; 695 clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 696 <&clk IMX8MN_CLK_GPU_SHADER>, 697 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 698 <&clk IMX8MN_CLK_GPU_AHB>; 699 }; 700 701 pgc_dispmix: power-domain@3 { 702 #power-domain-cells = <0>; 703 reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; 704 clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 705 <&clk IMX8MN_CLK_DISP_APB_ROOT>; 706 }; 707 708 pgc_mipi: power-domain@4 { 709 #power-domain-cells = <0>; 710 reg = <IMX8MN_POWER_DOMAIN_MIPI>; 711 power-domains = <&pgc_dispmix>; 712 }; 713 }; 714 }; 715 }; 716 717 aips2: bus@30400000 { 718 compatible = "fsl,aips-bus", "simple-bus"; 719 reg = <0x30400000 0x400000>; 720 #address-cells = <1>; 721 #size-cells = <1>; 722 ranges; 723 724 pwm1: pwm@30660000 { 725 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 726 reg = <0x30660000 0x10000>; 727 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, 729 <&clk IMX8MN_CLK_PWM1_ROOT>; 730 clock-names = "ipg", "per"; 731 #pwm-cells = <3>; 732 status = "disabled"; 733 }; 734 735 pwm2: pwm@30670000 { 736 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 737 reg = <0x30670000 0x10000>; 738 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, 740 <&clk IMX8MN_CLK_PWM2_ROOT>; 741 clock-names = "ipg", "per"; 742 #pwm-cells = <3>; 743 status = "disabled"; 744 }; 745 746 pwm3: pwm@30680000 { 747 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 748 reg = <0x30680000 0x10000>; 749 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, 751 <&clk IMX8MN_CLK_PWM3_ROOT>; 752 clock-names = "ipg", "per"; 753 #pwm-cells = <3>; 754 status = "disabled"; 755 }; 756 757 pwm4: pwm@30690000 { 758 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm"; 759 reg = <0x30690000 0x10000>; 760 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, 762 <&clk IMX8MN_CLK_PWM4_ROOT>; 763 clock-names = "ipg", "per"; 764 #pwm-cells = <3>; 765 status = "disabled"; 766 }; 767 768 system_counter: timer@306a0000 { 769 compatible = "nxp,sysctr-timer"; 770 reg = <0x306a0000 0x20000>; 771 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&osc_24m>; 773 clock-names = "per"; 774 }; 775 }; 776 777 aips3: bus@30800000 { 778 compatible = "fsl,aips-bus", "simple-bus"; 779 reg = <0x30800000 0x400000>; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 ranges; 783 784 spba1: spba-bus@30800000 { 785 compatible = "fsl,spba-bus", "simple-bus"; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 reg = <0x30800000 0x100000>; 789 ranges; 790 791 ecspi1: spi@30820000 { 792 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 reg = <0x30820000 0x10000>; 796 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>, 798 <&clk IMX8MN_CLK_ECSPI1_ROOT>; 799 clock-names = "ipg", "per"; 800 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 801 dma-names = "rx", "tx"; 802 status = "disabled"; 803 }; 804 805 ecspi2: spi@30830000 { 806 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 reg = <0x30830000 0x10000>; 810 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>, 812 <&clk IMX8MN_CLK_ECSPI2_ROOT>; 813 clock-names = "ipg", "per"; 814 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 815 dma-names = "rx", "tx"; 816 status = "disabled"; 817 }; 818 819 ecspi3: spi@30840000 { 820 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 reg = <0x30840000 0x10000>; 824 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>, 826 <&clk IMX8MN_CLK_ECSPI3_ROOT>; 827 clock-names = "ipg", "per"; 828 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 829 dma-names = "rx", "tx"; 830 status = "disabled"; 831 }; 832 833 uart1: serial@30860000 { 834 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 835 reg = <0x30860000 0x10000>; 836 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&clk IMX8MN_CLK_UART1_ROOT>, 838 <&clk IMX8MN_CLK_UART1_ROOT>; 839 clock-names = "ipg", "per"; 840 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 841 dma-names = "rx", "tx"; 842 status = "disabled"; 843 }; 844 845 uart3: serial@30880000 { 846 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 847 reg = <0x30880000 0x10000>; 848 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&clk IMX8MN_CLK_UART3_ROOT>, 850 <&clk IMX8MN_CLK_UART3_ROOT>; 851 clock-names = "ipg", "per"; 852 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 853 dma-names = "rx", "tx"; 854 status = "disabled"; 855 }; 856 857 uart2: serial@30890000 { 858 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 859 reg = <0x30890000 0x10000>; 860 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clk IMX8MN_CLK_UART2_ROOT>, 862 <&clk IMX8MN_CLK_UART2_ROOT>; 863 clock-names = "ipg", "per"; 864 status = "disabled"; 865 }; 866 }; 867 868 crypto: crypto@30900000 { 869 compatible = "fsl,sec-v4.0"; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 reg = <0x30900000 0x40000>; 873 ranges = <0 0x30900000 0x40000>; 874 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&clk IMX8MN_CLK_AHB>, 876 <&clk IMX8MN_CLK_IPG_ROOT>; 877 clock-names = "aclk", "ipg"; 878 879 sec_jr0: jr@1000 { 880 compatible = "fsl,sec-v4.0-job-ring"; 881 reg = <0x1000 0x1000>; 882 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 883 status = "disabled"; 884 }; 885 886 sec_jr1: jr@2000 { 887 compatible = "fsl,sec-v4.0-job-ring"; 888 reg = <0x2000 0x1000>; 889 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 890 }; 891 892 sec_jr2: jr@3000 { 893 compatible = "fsl,sec-v4.0-job-ring"; 894 reg = <0x3000 0x1000>; 895 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 896 }; 897 }; 898 899 i2c1: i2c@30a20000 { 900 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 reg = <0x30a20000 0x10000>; 904 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>; 906 status = "disabled"; 907 }; 908 909 i2c2: i2c@30a30000 { 910 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 reg = <0x30a30000 0x10000>; 914 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>; 916 status = "disabled"; 917 }; 918 919 i2c3: i2c@30a40000 { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 923 reg = <0x30a40000 0x10000>; 924 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>; 926 status = "disabled"; 927 }; 928 929 i2c4: i2c@30a50000 { 930 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 reg = <0x30a50000 0x10000>; 934 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>; 936 status = "disabled"; 937 }; 938 939 uart4: serial@30a60000 { 940 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart"; 941 reg = <0x30a60000 0x10000>; 942 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&clk IMX8MN_CLK_UART4_ROOT>, 944 <&clk IMX8MN_CLK_UART4_ROOT>; 945 clock-names = "ipg", "per"; 946 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 947 dma-names = "rx", "tx"; 948 status = "disabled"; 949 }; 950 951 mu: mailbox@30aa0000 { 952 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; 953 reg = <0x30aa0000 0x10000>; 954 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&clk IMX8MN_CLK_MU_ROOT>; 956 #mbox-cells = <2>; 957 }; 958 959 usdhc1: mmc@30b40000 { 960 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 961 reg = <0x30b40000 0x10000>; 962 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 964 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 965 <&clk IMX8MN_CLK_USDHC1_ROOT>; 966 clock-names = "ipg", "ahb", "per"; 967 fsl,tuning-start-tap = <20>; 968 fsl,tuning-step = <2>; 969 bus-width = <4>; 970 status = "disabled"; 971 }; 972 973 usdhc2: mmc@30b50000 { 974 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 975 reg = <0x30b50000 0x10000>; 976 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 978 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 979 <&clk IMX8MN_CLK_USDHC2_ROOT>; 980 clock-names = "ipg", "ahb", "per"; 981 fsl,tuning-start-tap = <20>; 982 fsl,tuning-step = <2>; 983 bus-width = <4>; 984 status = "disabled"; 985 }; 986 987 usdhc3: mmc@30b60000 { 988 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 989 reg = <0x30b60000 0x10000>; 990 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&clk IMX8MN_CLK_IPG_ROOT>, 992 <&clk IMX8MN_CLK_NAND_USDHC_BUS>, 993 <&clk IMX8MN_CLK_USDHC3_ROOT>; 994 clock-names = "ipg", "ahb", "per"; 995 fsl,tuning-start-tap = <20>; 996 fsl,tuning-step = <2>; 997 bus-width = <4>; 998 status = "disabled"; 999 }; 1000 1001 flexspi: spi@30bb0000 { 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 compatible = "nxp,imx8mm-fspi"; 1005 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1006 reg-names = "fspi_base", "fspi_mmap"; 1007 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, 1009 <&clk IMX8MN_CLK_QSPI_ROOT>; 1010 clock-names = "fspi_en", "fspi"; 1011 status = "disabled"; 1012 }; 1013 1014 sdma1: dma-controller@30bd0000 { 1015 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; 1016 reg = <0x30bd0000 0x10000>; 1017 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, 1019 <&clk IMX8MN_CLK_AHB>; 1020 clock-names = "ipg", "ahb"; 1021 #dma-cells = <3>; 1022 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1023 }; 1024 1025 fec1: ethernet@30be0000 { 1026 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1027 reg = <0x30be0000 0x10000>; 1028 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, 1033 <&clk IMX8MN_CLK_ENET1_ROOT>, 1034 <&clk IMX8MN_CLK_ENET_TIMER>, 1035 <&clk IMX8MN_CLK_ENET_REF>, 1036 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1037 clock-names = "ipg", "ahb", "ptp", 1038 "enet_clk_ref", "enet_out"; 1039 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>, 1040 <&clk IMX8MN_CLK_ENET_TIMER>, 1041 <&clk IMX8MN_CLK_ENET_REF>, 1042 <&clk IMX8MN_CLK_ENET_PHY_REF>; 1043 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1044 <&clk IMX8MN_SYS_PLL2_100M>, 1045 <&clk IMX8MN_SYS_PLL2_125M>, 1046 <&clk IMX8MN_SYS_PLL2_50M>; 1047 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1048 fsl,num-tx-queues = <3>; 1049 fsl,num-rx-queues = <3>; 1050 nvmem-cells = <&fec_mac_address>; 1051 nvmem-cell-names = "mac-address"; 1052 fsl,stop-mode = <&gpr 0x10 3>; 1053 status = "disabled"; 1054 }; 1055 1056 }; 1057 1058 aips4: bus@32c00000 { 1059 compatible = "fsl,aips-bus", "simple-bus"; 1060 reg = <0x32c00000 0x400000>; 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 ranges; 1064 1065 lcdif: lcdif@32e00000 { 1066 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; 1067 reg = <0x32e00000 0x10000>; 1068 clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1069 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1070 <&clk IMX8MN_CLK_DISP_AXI_ROOT>; 1071 clock-names = "pix", "axi", "disp_axi"; 1072 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1073 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; 1074 status = "disabled"; 1075 1076 port { 1077 lcdif_to_dsim: endpoint { 1078 remote-endpoint = <&dsim_from_lcdif>; 1079 }; 1080 }; 1081 }; 1082 1083 mipi_dsi: dsi@32e10000 { 1084 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; 1085 reg = <0x32e10000 0x400>; 1086 clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1087 <&clk IMX8MN_CLK_DSI_PHY_REF>; 1088 clock-names = "bus_clk", "sclk_mipi"; 1089 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1090 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; 1091 status = "disabled"; 1092 1093 ports { 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 port@0 { 1098 reg = <0>; 1099 1100 dsim_from_lcdif: endpoint { 1101 remote-endpoint = <&lcdif_to_dsim>; 1102 }; 1103 }; 1104 }; 1105 }; 1106 1107 disp_blk_ctrl: blk-ctrl@32e28000 { 1108 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 1109 reg = <0x32e28000 0x100>; 1110 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1111 <&pgc_dispmix>, <&pgc_mipi>, 1112 <&pgc_mipi>; 1113 power-domain-names = "bus", "isi", 1114 "lcdif", "mipi-dsi", 1115 "mipi-csi"; 1116 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 1117 <&clk IMX8MN_CLK_DISP_APB>, 1118 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1119 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1120 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 1121 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 1122 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 1123 <&clk IMX8MN_CLK_DSI_CORE>, 1124 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1125 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 1126 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 1127 clock-names = "disp_axi", "disp_apb", 1128 "disp_axi_root", "disp_apb_root", 1129 "lcdif-axi", "lcdif-apb", "lcdif-pix", 1130 "dsi-pclk", "dsi-ref", 1131 "csi-aclk", "csi-pclk"; 1132 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, 1133 <&clk IMX8MN_CLK_DSI_PHY_REF>, 1134 <&clk IMX8MN_CLK_DISP_PIXEL>, 1135 <&clk IMX8MN_CLK_DISP_AXI>, 1136 <&clk IMX8MN_CLK_DISP_APB>; 1137 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, 1138 <&clk IMX8MN_CLK_24M>, 1139 <&clk IMX8MN_VIDEO_PLL1_OUT>, 1140 <&clk IMX8MN_SYS_PLL2_1000M>, 1141 <&clk IMX8MN_SYS_PLL1_800M>; 1142 assigned-clock-rates = <266000000>, 1143 <24000000>, 1144 <594000000>, 1145 <500000000>, 1146 <200000000>; 1147 #power-domain-cells = <1>; 1148 }; 1149 1150 usbotg1: usb@32e40000 { 1151 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1152 reg = <0x32e40000 0x200>; 1153 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; 1155 clock-names = "usb1_ctrl_root_clk"; 1156 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; 1157 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; 1158 phys = <&usbphynop1>; 1159 fsl,usbmisc = <&usbmisc1 0>; 1160 power-domains = <&pgc_hsiomix>; 1161 status = "disabled"; 1162 }; 1163 1164 usbmisc1: usbmisc@32e40200 { 1165 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc", 1166 "fsl,imx6q-usbmisc"; 1167 #index-cells = <1>; 1168 reg = <0x32e40200 0x200>; 1169 }; 1170 }; 1171 1172 dma_apbh: dma-controller@33000000 { 1173 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1174 reg = <0x33000000 0x2000>; 1175 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1179 #dma-cells = <1>; 1180 dma-channels = <4>; 1181 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1182 }; 1183 1184 gpmi: nand-controller@33002000 { 1185 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1189 reg-names = "gpmi-nand", "bch"; 1190 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1191 interrupt-names = "bch"; 1192 clocks = <&clk IMX8MN_CLK_NAND_ROOT>, 1193 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1194 clock-names = "gpmi_io", "gpmi_bch_apb"; 1195 dmas = <&dma_apbh 0>; 1196 dma-names = "rx-tx"; 1197 status = "disabled"; 1198 }; 1199 1200 gpu: gpu@38000000 { 1201 compatible = "vivante,gc"; 1202 reg = <0x38000000 0x8000>; 1203 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&clk IMX8MN_CLK_GPU_AHB>, 1205 <&clk IMX8MN_CLK_GPU_BUS_ROOT>, 1206 <&clk IMX8MN_CLK_GPU_CORE_ROOT>, 1207 <&clk IMX8MN_CLK_GPU_SHADER>; 1208 clock-names = "reg", "bus", "core", "shader"; 1209 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, 1210 <&clk IMX8MN_CLK_GPU_SHADER>, 1211 <&clk IMX8MN_CLK_GPU_AXI>, 1212 <&clk IMX8MN_CLK_GPU_AHB>, 1213 <&clk IMX8MN_GPU_PLL>; 1214 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, 1215 <&clk IMX8MN_GPU_PLL_OUT>, 1216 <&clk IMX8MN_SYS_PLL1_800M>, 1217 <&clk IMX8MN_SYS_PLL1_800M>; 1218 assigned-clock-rates = <400000000>, 1219 <400000000>, 1220 <800000000>, 1221 <400000000>, 1222 <1200000000>; 1223 power-domains = <&pgc_gpumix>; 1224 }; 1225 1226 gic: interrupt-controller@38800000 { 1227 compatible = "arm,gic-v3"; 1228 reg = <0x38800000 0x10000>, 1229 <0x38880000 0xc0000>; 1230 #interrupt-cells = <3>; 1231 interrupt-controller; 1232 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1233 }; 1234 1235 ddrc: memory-controller@3d400000 { 1236 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; 1237 reg = <0x3d400000 0x400000>; 1238 clock-names = "core", "pll", "alt", "apb"; 1239 clocks = <&clk IMX8MN_CLK_DRAM_CORE>, 1240 <&clk IMX8MN_DRAM_PLL>, 1241 <&clk IMX8MN_CLK_DRAM_ALT>, 1242 <&clk IMX8MN_CLK_DRAM_APB>; 1243 }; 1244 1245 ddr-pmu@3d800000 { 1246 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1247 reg = <0x3d800000 0x400000>; 1248 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1249 }; 1250 }; 1251 1252 usbphynop1: usbphynop1 { 1253 #phy-cells = <0>; 1254 compatible = "usb-nop-xceiv"; 1255 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1256 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; 1257 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; 1258 clock-names = "main_clk"; 1259 power-domains = <&pgc_otg1>; 1260 }; 1261}; 1262