1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/net/qca-ar803x.h> 9#include "imx8mp.dtsi" 10 11/ { 12 model = "Data Modul i.MX8M Plus eDM SBC"; 13 compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp"; 14 15 aliases { 16 rtc0 = &rtc; 17 rtc1 = &snvs_rtc; 18 }; 19 20 chosen { 21 stdout-path = &uart3; 22 }; 23 24 memory@40000000 { 25 device_type = "memory"; 26 /* There are 1/2/4 GiB options, adjusted by bootloader. */ 27 reg = <0x0 0x40000000 0 0x40000000>; 28 }; 29 30 backlight: backlight { 31 compatible = "pwm-backlight"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_panel_backlight>; 34 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; 35 default-brightness-level = <7>; 36 enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 37 pwms = <&pwm1 0 5000000 0>; 38 /* Disabled by default, unless display board plugged in. */ 39 status = "disabled"; 40 }; 41 42 clk_xtal25: clock-xtal25 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <25000000>; 46 }; 47 48 panel: panel { 49 /* Compatible string is filled in by panel board DT Overlay. */ 50 backlight = <&backlight>; 51 power-supply = <®_panel_vcc>; 52 /* Disabled by default, unless display board plugged in. */ 53 status = "disabled"; 54 }; 55 56 reg_panel_vcc: regulator-panel-vcc { 57 compatible = "regulator-fixed"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_panel_vcc_reg>; 60 regulator-min-microvolt = <5000000>; 61 regulator-max-microvolt = <5000000>; 62 regulator-name = "PANEL_VCC"; 63 /* GPIO flags are ignored, enable-active-high applies. */ 64 gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>; 65 enable-active-high; 66 /* Disabled by default, unless display board plugged in. */ 67 status = "disabled"; 68 }; 69 70 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 71 compatible = "regulator-fixed"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 74 regulator-max-microvolt = <3300000>; 75 regulator-min-microvolt = <3300000>; 76 regulator-name = "VDD_3V3_SD"; 77 /* GPIO flags are ignored, enable-active-high applies. */ 78 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */ 79 enable-active-high; 80 off-on-delay-us = <12000>; 81 startup-delay-us = <100>; 82 vin-supply = <&buck4>; 83 }; 84 85 watchdog { /* TPS3813 */ 86 compatible = "linux,wdt-gpio"; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_watchdog_gpio>; 89 always-running; 90 gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 91 hw_algo = "level"; 92 /* Reset triggers in 2..3 seconds */ 93 hw_margin_ms = <1500>; 94 /* Disabled by default */ 95 status = "disabled"; 96 }; 97}; 98 99&A53_0 { 100 cpu-supply = <&buck2>; 101}; 102 103&A53_1 { 104 cpu-supply = <&buck2>; 105}; 106 107&A53_2 { 108 cpu-supply = <&buck2>; 109}; 110 111&A53_3 { 112 cpu-supply = <&buck2>; 113}; 114 115&ecspi1 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&pinctrl_ecspi1>; 118 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 119 status = "okay"; 120 121 flash@0 { /* W25Q128JVEI */ 122 compatible = "jedec,spi-nor"; 123 reg = <0>; 124 spi-max-frequency = <100000000>; /* Up to 133 MHz */ 125 spi-tx-bus-width = <1>; 126 spi-rx-bus-width = <1>; 127 }; 128}; 129 130&ecspi2 { /* Feature connector SPI */ 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_ecspi2>; 133 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 134 /* Disabled by default, unless feature board plugged in. */ 135 status = "disabled"; 136}; 137 138&ecspi3 { /* Display connector SPI */ 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_ecspi3>; 141 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 142 /* Disabled by default, unless display board plugged in. */ 143 status = "disabled"; 144}; 145 146&eqos { /* First ethernet */ 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_eqos>; 149 phy-handle = <&phy_eqos>; 150 phy-mode = "rgmii-id"; 151 status = "okay"; 152 153 mdio { 154 compatible = "snps,dwmac-mdio"; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 /* Atheros AR8031 PHY */ 159 phy_eqos: ethernet-phy@0 { 160 compatible = "ethernet-phy-ieee802.3-c22"; 161 reg = <0>; 162 /* 163 * Dedicated ENET_WOL# signal is unused, the PHY 164 * can wake the SoC up via INT signal as well. 165 */ 166 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; 167 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 168 reset-assert-us = <10000>; 169 reset-deassert-us = <10000>; 170 qca,keep-pll-enabled; 171 vddio-supply = <&vddio_eqos>; 172 173 vddio_eqos: vddio-regulator { 174 regulator-name = "VDDIO_EQOS"; 175 regulator-min-microvolt = <1800000>; 176 regulator-max-microvolt = <1800000>; 177 }; 178 179 vddh_eqos: vddh-regulator { 180 regulator-name = "VDDH_EQOS"; 181 }; 182 }; 183 }; 184}; 185 186&fec { /* Second ethernet */ 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_fec>; 189 phy-handle = <&phy_fec>; 190 phy-mode = "rgmii-id"; 191 fsl,magic-packet; 192 status = "okay"; 193 194 mdio { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 /* Atheros AR8031 PHY */ 199 phy_fec: ethernet-phy@0 { 200 compatible = "ethernet-phy-ieee802.3-c22"; 201 reg = <0>; 202 /* 203 * Dedicated ENET_WOL# signal is unused, the PHY 204 * can wake the SoC up via INT signal as well. 205 */ 206 interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>; 207 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; 208 reset-assert-us = <10000>; 209 reset-deassert-us = <10000>; 210 qca,keep-pll-enabled; 211 vddio-supply = <&vddio_fec>; 212 213 vddio_fec: vddio-regulator { 214 regulator-name = "VDDIO_FEC"; 215 regulator-min-microvolt = <1800000>; 216 regulator-max-microvolt = <1800000>; 217 }; 218 219 vddh_fec: vddh-regulator { 220 regulator-name = "VDDH_FEC"; 221 }; 222 }; 223 }; 224}; 225 226&flexcan1 { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pinctrl_flexcan1>; 229 status = "okay"; 230}; 231 232&gpio1 { 233 gpio-line-names = 234 "", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#", 235 "", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03", 236 "GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#", 237 "", "", "", "ENET_RST#", 238 "", "", "", "", "", "", "", "", 239 "", "", "", "", "", "", "", ""; 240}; 241 242&gpio2 { 243 gpio-line-names = 244 "", "", "ENET2_INT#", "", "", "", "", "", 245 "WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#", 246 "", "", "", "", 247 "", "", "", "SD2_RESET#", "", "", "", "", 248 "", "", "", "", "", "", "", ""; 249}; 250 251&gpio3 { 252 gpio-line-names = 253 "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", 254 "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", 255 "CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "", 256 "", "", "EEPROM_WP_1V8#", "", "", "", "", "", 257 "MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", 258 "", "M2_W_DISABLE1_1V8#", 259 "M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3", 260 "", "", "", ""; 261}; 262 263&gpio4 { 264 gpio-line-names = 265 "DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "", 266 "", "", "", "", "", "", "", "", 267 "", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#", 268 "", "DIS_USB_DN1", "DIS_USB_DN2", "", 269 "", "", "", "", "", "", "", ""; 270}; 271 272&gpio5 { 273 gpio-line-names = 274 "", "", "", "", "", "WDOG_EN", "", "", 275 "", "SPI1_CS#", "", "", 276 "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", 277 "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", 278 "", "", "", "", 279 "", "SPI3_CS#", "", "", "", "", "", ""; 280}; 281 282&i2c1 { 283 clock-frequency = <100000>; 284 pinctrl-names = "default", "gpio"; 285 pinctrl-0 = <&pinctrl_i2c1>; 286 pinctrl-1 = <&pinctrl_i2c1_gpio>; 287 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 288 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 289 status = "okay"; 290 291 usb-hub@2c { 292 compatible = "microchip,usb2514bi"; 293 reg = <0x2c>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_usb_hub>; 296 individual-port-switching; 297 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 298 self-powered; 299 }; 300 301 eeprom: eeprom@50 { 302 compatible = "atmel,24c32"; 303 reg = <0x50>; 304 pagesize = <32>; 305 }; 306 307 rtc: rtc@68 { 308 compatible = "st,m41t62"; 309 reg = <0x68>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pinctrl_rtc>; 312 interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; 313 }; 314 315 pcieclk: clk@6a { 316 compatible = "renesas,9fgv0241"; 317 reg = <0x6a>; 318 clocks = <&clk_xtal25>; 319 #clock-cells = <1>; 320 }; 321}; 322 323&i2c2 { 324 clock-frequency = <100000>; 325 pinctrl-names = "default", "gpio"; 326 pinctrl-0 = <&pinctrl_i2c2>; 327 pinctrl-1 = <&pinctrl_i2c2_gpio>; 328 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 329 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 330 status = "okay"; 331}; 332 333&i2c3 { 334 clock-frequency = <100000>; 335 pinctrl-names = "default", "gpio"; 336 pinctrl-0 = <&pinctrl_i2c3>; 337 pinctrl-1 = <&pinctrl_i2c3_gpio>; 338 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 339 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 340 status = "okay"; 341 342 pmic: pmic@25 { 343 compatible = "nxp,pca9450c"; 344 reg = <0x25>; 345 pinctrl-names = "default"; 346 pinctrl-0 = <&pinctrl_pmic>; 347 interrupt-parent = <&gpio1>; 348 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 349 350 /* 351 * i.MX 8M Plus Data Sheet for Consumer Products 352 * 3.1.4 Operating ranges 353 * MIMX8ML8CVNKZAB 354 */ 355 regulators { 356 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ 357 regulator-min-microvolt = <850000>; 358 regulator-max-microvolt = <1000000>; 359 regulator-ramp-delay = <3125>; 360 regulator-always-on; 361 regulator-boot-on; 362 }; 363 364 buck2: BUCK2 { /* VDD_ARM */ 365 nxp,dvs-run-voltage = <950000>; 366 nxp,dvs-standby-voltage = <850000>; 367 regulator-min-microvolt = <850000>; 368 regulator-max-microvolt = <1000000>; 369 regulator-ramp-delay = <3125>; 370 regulator-always-on; 371 regulator-boot-on; 372 }; 373 374 buck4: BUCK4 { /* VDD_3V3 */ 375 regulator-min-microvolt = <3300000>; 376 regulator-max-microvolt = <3300000>; 377 regulator-always-on; 378 regulator-boot-on; 379 }; 380 381 buck5: BUCK5 { /* VDD_1V8 */ 382 regulator-min-microvolt = <1800000>; 383 regulator-max-microvolt = <1800000>; 384 regulator-always-on; 385 regulator-boot-on; 386 }; 387 388 buck6: BUCK6 { /* NVCC_DRAM_1V1 */ 389 regulator-min-microvolt = <1100000>; 390 regulator-max-microvolt = <1100000>; 391 regulator-always-on; 392 regulator-boot-on; 393 }; 394 395 ldo1: LDO1 { /* NVCC_SNVS_1V8 */ 396 regulator-min-microvolt = <1800000>; 397 regulator-max-microvolt = <1800000>; 398 regulator-always-on; 399 regulator-boot-on; 400 }; 401 402 ldo3: LDO3 { /* VDDA_1V8 */ 403 regulator-min-microvolt = <1800000>; 404 regulator-max-microvolt = <1800000>; 405 regulator-always-on; 406 regulator-boot-on; 407 }; 408 409 ldo4: LDO4 { /* PMIC_LDO4 */ 410 regulator-min-microvolt = <3300000>; 411 regulator-max-microvolt = <3300000>; 412 }; 413 414 ldo5: LDO5 { /* NVCC_SD2 */ 415 regulator-min-microvolt = <1800000>; 416 regulator-max-microvolt = <3300000>; 417 }; 418 }; 419 }; 420}; 421 422&i2c5 { /* HDMI EDID bus */ 423 clock-frequency = <100000>; 424 pinctrl-names = "default", "gpio"; 425 pinctrl-0 = <&pinctrl_i2c5>; 426 pinctrl-1 = <&pinctrl_i2c5_gpio>; 427 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 428 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 429 status = "okay"; 430}; 431 432&pwm1 { 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_panel_pwm>; 435 /* Disabled by default, unless display board plugged in. */ 436 status = "disabled"; 437}; 438 439/* SD slot */ 440&usdhc2 { 441 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 442 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 443 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 444 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 445 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 446 vmmc-supply = <®_usdhc2_vmmc>; 447 bus-width = <4>; 448 status = "okay"; 449}; 450 451/* eMMC */ 452&usdhc3 { 453 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 454 pinctrl-0 = <&pinctrl_usdhc3>; 455 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 456 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 457 vmmc-supply = <&buck4>; 458 vqmmc-supply = <&buck5>; 459 bus-width = <8>; 460 no-sd; 461 no-sdio; 462 non-removable; 463 status = "okay"; 464}; 465 466&uart1 { /* RS485 */ 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_uart1>; 469 uart-has-rtscts; 470 status = "disabled"; /* Optional */ 471}; 472 473&uart2 { 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_uart2>; 476 uart-has-rtscts; 477 status = "okay"; 478}; 479 480&uart3 { /* A53 Debug */ 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_uart3>; 483 status = "okay"; 484}; 485 486&uart4 { 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pinctrl_uart4>; 489 status = "okay"; 490}; 491 492&usb3_phy0 { 493 status = "okay"; 494}; 495 496&usb3_0 { 497 fsl,over-current-active-low; 498 status = "okay"; 499}; 500 501&usb_dwc3_0 { /* Lower plug direct */ 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_usb1>; 504 dr_mode = "host"; 505 status = "okay"; 506}; 507 508&usb3_phy1 { 509 status = "okay"; 510}; 511 512&usb3_1 { 513 status = "okay"; 514}; 515 516&usb_dwc3_1 { /* Upper plug via HUB */ 517 dr_mode = "host"; 518 status = "okay"; 519}; 520 521&wdog1 { 522 status = "okay"; 523}; 524 525/* IOMUXC node should be at the end of DT to improve readability. */ 526&iomuxc { 527 pinctrl-names = "default"; 528 pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, 529 <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, 530 <&pinctrl_panel_expansion>; 531 532 pinctrl_ecspi1: ecspi1-grp { 533 fsl,pins = < 534 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 535 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 536 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 537 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 538 >; 539 }; 540 541 pinctrl_ecspi2: ecspi2-grp { 542 fsl,pins = < 543 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 544 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 545 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 546 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 547 >; 548 }; 549 550 pinctrl_ecspi3: ecspi3-grp { 551 fsl,pins = < 552 MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44 553 MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44 554 MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44 555 MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40 556 >; 557 }; 558 559 pinctrl_eqos: eqos-grp { 560 fsl,pins = < 561 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 562 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 563 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f 564 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f 565 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f 566 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f 567 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f 568 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f 569 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 570 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 571 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 572 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 573 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 574 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 575 /* ENET_RST# */ 576 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 577 /* ENET_INT# */ 578 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 579 >; 580 }; 581 582 pinctrl_fec: fec-grp { 583 fsl,pins = < 584 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 585 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 586 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 587 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 588 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 589 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 590 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 591 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 592 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f 593 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f 594 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f 595 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f 596 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f 597 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f 598 /* ENET2_RST# */ 599 MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 600 /* ENET2_INT# */ 601 MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 602 >; 603 }; 604 605 pinctrl_flexcan1: flexcan1-grp { 606 fsl,pins = < 607 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 608 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 609 >; 610 }; 611 612 pinctrl_hog_feature: hog-feature-grp { 613 fsl,pins = < 614 /* GPIO5_IO03 */ 615 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006 616 /* GPIO5_IO04 */ 617 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006 618 619 /* CAN_INT# */ 620 MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090 621 >; 622 }; 623 624 pinctrl_hog_panel: hog-panel-grp { 625 fsl,pins = < 626 /* GRAPHICS_GPIO0_1V8 */ 627 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26 628 >; 629 }; 630 631 pinctrl_hog_misc: hog-misc-grp { 632 fsl,pins = < 633 /* ENET_WOL# -- shared by both PHYs */ 634 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090 635 636 /* PG_V_IN_VAR# */ 637 MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 638 /* CSI2_PD_1V8 */ 639 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 640 /* CSI2_RESET_1V8# */ 641 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 642 643 /* DIS_USB_DN1 */ 644 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 645 /* DIS_USB_DN2 */ 646 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0 647 648 /* EEPROM_WP_1V8# */ 649 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100 650 /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ 651 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0 652 /* GRAPHICS_PRSNT_1V8# */ 653 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 654 655 /* CLK_CCM_CLKO1_3V3 */ 656 MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 657 >; 658 }; 659 660 pinctrl_hog_sbc: hog-sbc-grp { 661 fsl,pins = < 662 /* MEMCFG[0..2] straps */ 663 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140 664 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140 665 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140 666 >; 667 }; 668 669 pinctrl_i2c1: i2c1-grp { 670 fsl,pins = < 671 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 672 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 673 >; 674 }; 675 676 pinctrl_i2c1_gpio: i2c1-gpio-grp { 677 fsl,pins = < 678 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 679 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 680 >; 681 }; 682 683 pinctrl_i2c2: i2c2-grp { 684 fsl,pins = < 685 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 686 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 687 >; 688 }; 689 690 pinctrl_i2c2_gpio: i2c2-gpio-grp { 691 fsl,pins = < 692 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 693 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 694 >; 695 }; 696 697 pinctrl_i2c3: i2c3-grp { 698 fsl,pins = < 699 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 700 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 701 >; 702 }; 703 704 pinctrl_i2c3_gpio: i2c3-gpio-grp { 705 fsl,pins = < 706 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 707 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 708 >; 709 }; 710 711 pinctrl_i2c5: i2c5-grp { 712 fsl,pins = < 713 MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 714 MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 715 >; 716 }; 717 718 pinctrl_i2c5_gpio: i2c5-gpio-grp { 719 fsl,pins = < 720 MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 721 MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 722 >; 723 }; 724 725 pinctrl_panel_backlight: panel-backlight-grp { 726 fsl,pins = < 727 /* BL_ENABLE_1V8 */ 728 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104 729 >; 730 }; 731 732 pinctrl_panel_expansion: panel-expansion-grp { 733 fsl,pins = < 734 /* DSI_RESET_1V8# */ 735 MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2 736 /* DSI_IRQ_1V8# */ 737 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090 738 >; 739 }; 740 741 pinctrl_panel_pwm: panel-pwm-grp { 742 fsl,pins = < 743 /* BL_PWM_3V3 */ 744 MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12 745 >; 746 }; 747 748 pinctrl_panel_vcc_reg: panel-vcc-grp { 749 fsl,pins = < 750 /* TFT_ENABLE_1V8 */ 751 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104 752 >; 753 }; 754 755 pinctrl_pcie0: pcie-grp { 756 fsl,pins = < 757 /* M2_PCIE_RST# */ 758 MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 759 /* M2_W_DISABLE1_1V8# */ 760 MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 761 /* M2_W_DISABLE2_1V8# */ 762 MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 763 /* CLK_M2_32K768 */ 764 MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 765 /* M2_PCIE_WAKE# */ 766 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 767 /* M2_PCIE_CLKREQ# */ 768 MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 769 >; 770 }; 771 772 pinctrl_pdm: pdm-grp { 773 fsl,pins = < 774 /* PDM_SEL */ 775 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0 776 MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0 777 MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0 778 >; 779 }; 780 781 pinctrl_pmic: pmic-grp { 782 fsl,pins = < 783 /* PMIC_nINT */ 784 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 785 >; 786 }; 787 788 pinctrl_rtc: rtc-grp { 789 fsl,pins = < 790 /* RTC_IRQ# */ 791 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090 792 >; 793 }; 794 795 pinctrl_sai1: sai1-grp { 796 fsl,pins = < 797 MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6 798 MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6 799 MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6 800 MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 801 MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6 802 >; 803 }; 804 805 pinctrl_sai2: sai2-grp { 806 fsl,pins = < 807 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 808 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 809 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 810 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 811 >; 812 }; 813 814 pinctrl_sai3: sai3-grp { 815 fsl,pins = < 816 MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 817 MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 818 MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 819 MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 820 MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 821 >; 822 }; 823 824 pinctrl_uart1: uart1-grp { 825 fsl,pins = < 826 MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49 827 MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49 828 MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49 829 MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 830 >; 831 }; 832 833 pinctrl_uart2: uart2-grp { 834 fsl,pins = < 835 MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49 836 MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49 837 MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 838 MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 839 >; 840 }; 841 842 pinctrl_uart3: uart3-grp { 843 fsl,pins = < 844 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 845 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 846 >; 847 }; 848 849 pinctrl_uart4: uart4-grp { 850 fsl,pins = < 851 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 852 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 853 >; 854 }; 855 856 pinctrl_usdhc2: usdhc2-grp { 857 fsl,pins = < 858 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 859 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 860 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 861 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 862 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 863 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 864 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 865 >; 866 }; 867 868 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 869 fsl,pins = < 870 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 871 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 872 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 873 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 874 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 875 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 876 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 877 >; 878 }; 879 880 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 881 fsl,pins = < 882 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 883 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 884 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 885 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 886 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 887 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 888 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 889 >; 890 }; 891 892 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 893 fsl,pins = < 894 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 895 >; 896 }; 897 898 pinctrl_usdhc2_gpio: usdhc2-gpio-grp { 899 fsl,pins = < 900 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 901 >; 902 }; 903 904 pinctrl_usdhc3: usdhc3-grp { 905 fsl,pins = < 906 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 907 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 908 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 909 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 910 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 911 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 912 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 913 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 914 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 915 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 916 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 917 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 918 >; 919 }; 920 921 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { 922 fsl,pins = < 923 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 924 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 925 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 926 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 927 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 928 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 929 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 930 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 931 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 932 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 933 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 934 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 935 >; 936 }; 937 938 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { 939 fsl,pins = < 940 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 941 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 942 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 943 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 944 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 945 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 946 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 947 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 948 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 949 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 950 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 951 MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 952 >; 953 }; 954 955 pinctrl_usb_hub: usb-hub-grp { 956 fsl,pins = < 957 /* USBHUB_RESET# */ 958 MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4 959 >; 960 }; 961 962 pinctrl_usb1: usb1-grp { 963 fsl,pins = < 964 MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6 965 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80 966 >; 967 }; 968 969 pinctrl_watchdog_gpio: watchdog-gpio-grp { 970 fsl,pins = < 971 /* WDOG_B# */ 972 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26 973 /* WDOG_EN -- ungate WDT RESET# signal propagation */ 974 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6 975 /* WDOG_KICK# / WDI */ 976 MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 977 >; 978 }; 979}; 980