1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
4 */
5
6#include "imx8mp.dtsi"
7
8/ {
9	model = "DH electronics i.MX8M Plus DHCOM SoM";
10	compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
11
12	aliases {
13		ethernet0 = &eqos;
14		ethernet1 = &fec;
15		rtc0 = &rv3032;
16		rtc1 = &snvs_rtc;
17		spi0 = &flexspi;
18	};
19
20	memory@40000000 {
21		device_type = "memory";
22		/* Memory size 512 MiB..8 GiB will be filled by U-Boot */
23		reg = <0x0 0x40000000 0 0x08000000>;
24	};
25
26	reg_eth_vio: regulator-eth-vio {
27		compatible = "regulator-fixed";
28		gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
29		pinctrl-0 = <&pinctrl_enet_vio>;
30		pinctrl-names = "default";
31		regulator-always-on;
32		regulator-boot-on;
33		regulator-min-microvolt = <3300000>;
34		regulator-max-microvolt = <3300000>;
35		regulator-name = "eth_vio";
36		vin-supply = <&buck4>;
37	};
38
39	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40		compatible = "regulator-fixed";
41		enable-active-high;
42		gpio = <&gpio2 19 0>; /* SD2_RESET */
43		off-on-delay-us = <12000>;
44		pinctrl-names = "default";
45		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46		regulator-max-microvolt = <3300000>;
47		regulator-min-microvolt = <3300000>;
48		regulator-name = "VDD_3V3_SD";
49		startup-delay-us = <100>;
50		vin-supply = <&buck4>;
51	};
52};
53
54&A53_0 {
55	cpu-supply = <&buck2>;
56};
57
58&A53_1 {
59	cpu-supply = <&buck2>;
60};
61
62&A53_2 {
63	cpu-supply = <&buck2>;
64};
65
66&A53_3 {
67	cpu-supply = <&buck2>;
68};
69
70&ecspi1 {
71	pinctrl-names = "default";
72	pinctrl-0 = <&pinctrl_ecspi1>;
73	cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
74	status = "disabled";
75};
76
77&ecspi2 {
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_ecspi2>;
80	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
81	status = "disabled";
82};
83
84&eqos {	/* First ethernet */
85	pinctrl-names = "default";
86	pinctrl-0 = <&pinctrl_eqos>;
87	phy-handle = <&ethphy0g>;
88	phy-mode = "rgmii-id";
89	status = "okay";
90
91	mdio {
92		compatible = "snps,dwmac-mdio";
93		#address-cells = <1>;
94		#size-cells = <0>;
95
96		/* Up to one of these two PHYs may be populated. */
97		ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
98			compatible = "ethernet-phy-id0007.c110",
99				     "ethernet-phy-ieee802.3-c22";
100			interrupt-parent = <&gpio3>;
101			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
102			pinctrl-0 = <&pinctrl_ethphy0>;
103			pinctrl-names = "default";
104			reg = <1>;
105			reset-assert-us = <1000>;
106			reset-deassert-us = <1000>;
107			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
108			/* Non-default PHY population option. */
109			status = "disabled";
110		};
111
112		ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
113			compatible = "ethernet-phy-id0022.1642",
114				     "ethernet-phy-ieee802.3-c22";
115			interrupt-parent = <&gpio3>;
116			interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
117			micrel,led-mode = <0>;
118			pinctrl-0 = <&pinctrl_ethphy0>;
119			pinctrl-names = "default";
120			reg = <5>;
121			reset-assert-us = <1000>;
122			reset-deassert-us = <1000>;
123			reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
124			/* Default PHY population option. */
125			status = "okay";
126		};
127	};
128};
129
130&fec {	/* Second ethernet */
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_fec>;
133	phy-handle = <&ethphy1f>;
134	phy-mode = "rgmii";
135	fsl,magic-packet;
136	status = "okay";
137
138	mdio {
139		#address-cells = <1>;
140		#size-cells = <0>;
141
142		/* Up to one PHY may be populated. */
143		ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
144			compatible = "ethernet-phy-id0007.c110",
145				     "ethernet-phy-ieee802.3-c22";
146			interrupt-parent = <&gpio4>;
147			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
148			pinctrl-0 = <&pinctrl_ethphy1>;
149			pinctrl-names = "default";
150			reg = <1>;
151			reset-assert-us = <1000>;
152			reset-deassert-us = <1000>;
153			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
154			/* Non-default PHY population option. */
155			status = "disabled";
156		};
157	};
158};
159
160&flexcan1 {
161	pinctrl-names = "default";
162	pinctrl-0 = <&pinctrl_flexcan1>;
163	status = "disabled";
164};
165
166&flexcan2 {
167	pinctrl-names = "default";
168	pinctrl-0 = <&pinctrl_flexcan2>;
169	status = "disabled";
170};
171
172&flexspi {
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_flexspi>;
175	status = "okay";
176
177	flash@0 {	/* W25Q128JWPIM */
178		compatible = "jedec,spi-nor";
179		reg = <0>;
180		spi-max-frequency = <80000000>;
181		spi-tx-bus-width = <4>;
182		spi-rx-bus-width = <4>;
183	};
184};
185
186&gpio1 {
187	gpio-line-names =
188		"DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
189		"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
190		"", "", "", "", "", "", "", "",
191		"", "", "", "", "", "", "", "";
192};
193
194&gpio2 {
195	gpio-line-names =
196		"", "", "", "", "", "", "", "",
197		"", "", "", "DHCOM-K", "", "", "", "",
198		"", "", "", "", "DHCOM-INT", "", "", "",
199		"", "", "", "", "", "", "", "";
200};
201
202&gpio3 {
203	gpio-line-names =
204		"", "", "", "", "", "", "", "",
205		"", "", "", "", "", "", "SOM-HW0", "",
206		"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
207		"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
208};
209
210&gpio4 {
211	gpio-line-names =
212		"", "", "", "", "", "", "", "",
213		"", "", "", "", "", "", "", "",
214		"", "", "", "SOM-HW1", "", "", "", "",
215		"", "", "", "DHCOM-D", "", "", "", "";
216};
217
218&gpio5 {
219	gpio-line-names =
220		"", "", "DHCOM-C", "", "", "", "", "",
221		"", "", "", "", "", "", "", "",
222		"", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
223		"", "", "", "", "", "", "", "";
224};
225
226&i2c3 {
227	clock-frequency = <100000>;
228	pinctrl-names = "default", "gpio";
229	pinctrl-0 = <&pinctrl_i2c3>;
230	pinctrl-1 = <&pinctrl_i2c3_gpio>;
231	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
232	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
233	status = "okay";
234
235	pmic: pmic@25 {
236		compatible = "nxp,pca9450c";
237		reg = <0x25>;
238		pinctrl-names = "default";
239		pinctrl-0 = <&pinctrl_pmic>;
240		interrupt-parent = <&gpio1>;
241		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
242
243		/*
244		 * i.MX 8M Plus Data Sheet for Consumer Products
245		 * 3.1.4 Operating ranges
246		 * MIMX8ML8CVNKZAB
247		 */
248		regulators {
249			buck1: BUCK1 {	/* VDD_SOC (dual-phase with BUCK3) */
250				regulator-min-microvolt = <850000>;
251				regulator-max-microvolt = <1000000>;
252				regulator-ramp-delay = <3125>;
253				regulator-always-on;
254				regulator-boot-on;
255			};
256
257			buck2: BUCK2 {	/* VDD_ARM */
258				regulator-min-microvolt = <850000>;
259				regulator-max-microvolt = <1000000>;
260				regulator-ramp-delay = <3125>;
261				regulator-always-on;
262				regulator-boot-on;
263			};
264
265			buck4: BUCK4 {	/* VDD_3V3 */
266				regulator-min-microvolt = <3300000>;
267				regulator-max-microvolt = <3300000>;
268				regulator-always-on;
269				regulator-boot-on;
270			};
271
272			buck5: BUCK5 {	/* VDD_1V8 */
273				regulator-min-microvolt = <1800000>;
274				regulator-max-microvolt = <1800000>;
275				regulator-always-on;
276				regulator-boot-on;
277			};
278
279			buck6: BUCK6 {	/* NVCC_DRAM_1V1 */
280				regulator-min-microvolt = <1100000>;
281				regulator-max-microvolt = <1100000>;
282				regulator-always-on;
283				regulator-boot-on;
284			};
285
286			ldo1: LDO1 {	/* NVCC_SNVS_1V8 */
287				regulator-min-microvolt = <1800000>;
288				regulator-max-microvolt = <1800000>;
289				regulator-always-on;
290				regulator-boot-on;
291			};
292
293			ldo3: LDO3 {	/* VDDA_1V8 */
294				regulator-min-microvolt = <1800000>;
295				regulator-max-microvolt = <1800000>;
296				regulator-always-on;
297				regulator-boot-on;
298			};
299
300			ldo4: LDO4 {	/* PMIC_LDO4 */
301				regulator-min-microvolt = <3300000>;
302				regulator-max-microvolt = <3300000>;
303			};
304
305			ldo5: LDO5 {	/* NVCC_SD2 */
306				regulator-min-microvolt = <1800000>;
307				regulator-max-microvolt = <3300000>;
308			};
309		};
310	};
311
312	adc@48 {
313		compatible = "ti,tla2024";
314		reg = <0x48>;
315		#address-cells = <1>;
316		#size-cells = <0>;
317
318		channel@0 {	/* Voltage over AIN0 and AIN1. */
319			reg = <0>;
320		};
321
322		channel@1 {	/* Voltage over AIN0 and AIN3. */
323			reg = <1>;
324		};
325
326		channel@2 {	/* Voltage over AIN1 and AIN3. */
327			reg = <2>;
328		};
329
330		channel@3 {	/* Voltage over AIN2 and AIN3. */
331			reg = <3>;
332		};
333
334		channel@4 {	/* Voltage over AIN0 and GND. */
335			reg = <4>;
336		};
337
338		channel@5 {	/* Voltage over AIN1 and GND. */
339			reg = <5>;
340		};
341
342		channel@6 {	/* Voltage over AIN2 and GND. */
343			reg = <6>;
344		};
345
346		channel@7 {	/* Voltage over AIN3 and GND. */
347			reg = <7>;
348		};
349	};
350
351	touchscreen@49 {
352		compatible = "ti,tsc2004";
353		reg = <0x49>;
354		interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
355		pinctrl-names = "default";
356		pinctrl-0 = <&pinctrl_touch>;
357		vio-supply = <&buck4>;
358	};
359
360	eeprom0: eeprom@50 {	/* EEPROM with EQoS MAC address */
361		compatible = "atmel,24c02";
362		pagesize = <16>;
363		reg = <0x50>;
364	};
365
366	rv3032: rtc@51 {
367		compatible = "microcrystal,rv3032";
368		reg = <0x51>;
369		interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
370		pinctrl-names = "default";
371		pinctrl-0 = <&pinctrl_rtc>;
372	};
373
374	eeprom1: eeprom@53 {	/* EEPROM with FEC MAC address */
375		compatible = "atmel,24c02";
376		pagesize = <16>;
377		reg = <0x53>;
378	};
379};
380
381&i2c4 {
382	clock-frequency = <100000>;
383	pinctrl-names = "default", "gpio";
384	pinctrl-0 = <&pinctrl_i2c4>;
385	pinctrl-1 = <&pinctrl_i2c4_gpio>;
386	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
387	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
388	status = "okay";
389};
390
391&i2c5 {	/* HDMI EDID bus */
392	clock-frequency = <100000>;
393	pinctrl-names = "default", "gpio";
394	pinctrl-0 = <&pinctrl_i2c5>;
395	pinctrl-1 = <&pinctrl_i2c5_gpio>;
396	scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
397	sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
398	status = "okay";
399};
400
401&pwm1 {
402	pinctrl-0 = <&pinctrl_pwm1>;
403	pinctrl-names = "default";
404	status = "disabled";
405};
406
407&uart1 {
408	/* CA53 console */
409	pinctrl-names = "default";
410	pinctrl-0 = <&pinctrl_uart1>;
411	status = "okay";
412};
413
414&uart2 {
415	/* Bluetooth */
416	pinctrl-names = "default";
417	pinctrl-0 = <&pinctrl_uart2>;
418	uart-has-rtscts;
419	status = "okay";
420
421	/*
422	 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
423	 * which with 16x oversampling yields 5 Mbdps baud base,
424	 * which can be well divided by 5/4 to achieve 4 Mbdps,
425	 * which is exactly the maximum rate supported by muRata
426	 * 2AE bluetooth UART.
427	 */
428	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
429	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
430	assigned-clock-rates = <80000000>;
431
432	bluetooth {
433		pinctrl-names = "default";
434		pinctrl-0 = <&pinctrl_uart2_bt>;
435		compatible = "cypress,cyw4373a0-bt";
436		shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
437		max-speed = <4000000>;
438	};
439};
440
441&uart3 {
442	pinctrl-names = "default";
443	pinctrl-0 = <&pinctrl_uart3>;
444	uart-has-rtscts;
445	status = "okay";
446};
447
448&uart4 {
449	pinctrl-names = "default";
450	pinctrl-0 = <&pinctrl_uart4>;
451	status = "okay";
452};
453
454&usb3_phy0 {
455	status = "okay";
456};
457
458&usb3_0 {
459	status = "okay";
460};
461
462&usb_dwc3_0 {
463	pinctrl-names = "default";
464	pinctrl-0 = <&pinctrl_usb0_vbus>;
465	dr_mode = "otg";
466	status = "okay";
467};
468
469&usb3_phy1 {
470	status = "okay";
471};
472
473&usb3_1 {
474	status = "okay";
475};
476
477&usb_dwc3_1 {
478	pinctrl-names = "default";
479	pinctrl-0 = <&pinctrl_usb1_vbus>;
480	dr_mode = "host";
481	status = "okay";
482};
483
484/* SDIO WiFi */
485&usdhc1 {
486	pinctrl-names = "default", "state_100mhz", "state_200mhz";
487	pinctrl-0 = <&pinctrl_usdhc1>;
488	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
489	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
490	vmmc-supply = <&buck4>;
491	bus-width = <4>;
492	non-removable;
493	cap-power-off-card;
494	keep-power-in-suspend;
495	status = "okay";
496
497	#address-cells = <1>;
498	#size-cells = <0>;
499
500	brcmf: bcrmf@1 {	/* muRata 2AE */
501		reg = <1>;
502		compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
503		/*
504		 * The "host-wake" interrupt output is by default not
505		 * connected to the SoC, but can be connected on to
506		 * SoC pin on the carrier board.
507		 */
508		reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
509	};
510};
511
512/* SD slot */
513&usdhc2 {
514	pinctrl-names = "default", "state_100mhz", "state_200mhz";
515	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
516	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
517	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
518	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
519	vmmc-supply = <&reg_usdhc2_vmmc>;
520	bus-width = <4>;
521	status = "okay";
522};
523
524/* eMMC */
525&usdhc3 {
526	pinctrl-names = "default", "state_100mhz", "state_200mhz";
527	pinctrl-0 = <&pinctrl_usdhc3>;
528	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
529	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
530	vmmc-supply = <&buck4>;
531	vqmmc-supply = <&buck5>;
532	bus-width = <8>;
533	non-removable;
534	status = "okay";
535};
536
537&wdog1 {
538	pinctrl-names = "default";
539	pinctrl-0 = <&pinctrl_wdog>;
540	fsl,ext-reset-output;
541	status = "okay";
542};
543
544&iomuxc {
545	pinctrl-0 = <&pinctrl_hog_base
546		     &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
547		     &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
548		     &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
549		     &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
550		     /* GPIO_M is connected to CLKOUT2 */
551		     &pinctrl_dhcom_int>;
552	pinctrl-names = "default";
553
554	pinctrl_dhcom_a: dhcom-a-grp {
555		fsl,pins = <
556			/* ENET_QOS_EVENT0-OUT */
557			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09		0x2
558		>;
559	};
560
561	pinctrl_dhcom_b: dhcom-b-grp {
562		fsl,pins = <
563			/* ENET_QOS_EVENT0-IN */
564			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x2
565		>;
566	};
567
568	pinctrl_dhcom_c: dhcom-c-grp {
569		fsl,pins = <
570			/* GPIO_C */
571			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x2
572		>;
573	};
574
575	pinctrl_dhcom_d: dhcom-d-grp {
576		fsl,pins = <
577			/* GPIO_D */
578			MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27		0x2
579		>;
580	};
581
582	pinctrl_dhcom_e: dhcom-e-grp {
583		fsl,pins = <
584			/* GPIO_E */
585			MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22		0x2
586		>;
587	};
588
589	pinctrl_dhcom_f: dhcom-f-grp {
590		fsl,pins = <
591			/* GPIO_F */
592			MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23		0x2
593		>;
594	};
595
596	pinctrl_dhcom_g: dhcom-g-grp {
597		fsl,pins = <
598			/* GPIO_G */
599			MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x2
600		>;
601	};
602
603	pinctrl_dhcom_h: dhcom-h-grp {
604		fsl,pins = <
605			/* GPIO_H */
606			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11		0x2
607		>;
608	};
609
610	pinctrl_dhcom_i: dhcom-i-grp {
611		fsl,pins = <
612			/* CSI1_SYNC */
613			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x2
614		>;
615	};
616
617	pinctrl_dhcom_j: dhcom-j-grp {
618		fsl,pins = <
619			/* CSIx_#RST */
620			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x2
621		>;
622	};
623
624	pinctrl_dhcom_k: dhcom-k-grp {
625		fsl,pins = <
626			/* CSIx_PWDN */
627			MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x2
628		>;
629	};
630
631	pinctrl_dhcom_l: dhcom-l-grp {
632		fsl,pins = <
633			/* CSI2_SYNC */
634			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x2
635		>;
636	};
637
638	pinctrl_dhcom_int: dhcom-int-grp {
639		fsl,pins = <
640			/* INT_HIGHEST_PRIO */
641			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20			0x2
642		>;
643	};
644
645	pinctrl_hog_base: dhcom-hog-base-grp {
646		fsl,pins = <
647			/* GPIOs for memory coding */
648			MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22		0x40000080
649			MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x40000080
650			MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x40000080
651			/* GPIOs for hardware coding */
652			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14		0x40000080
653			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x40000080
654			MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25		0x40000080
655		>;
656	};
657
658	pinctrl_ecspi1: dhcom-ecspi1-grp {
659		fsl,pins = <
660			MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK		0x44
661			MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI		0x44
662			MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO		0x44
663			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x40
664		>;
665	};
666
667	pinctrl_ecspi2: dhcom-ecspi2-grp {
668		fsl,pins = <
669			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x44
670			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x44
671			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x44
672			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40
673		>;
674	};
675
676	pinctrl_eqos: dhcom-eqos-grp {	/* RGMII */
677		fsl,pins = <
678			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC		0x3
679			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO		0x3
680			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL	0x1f
681			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
682			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0	0x1f
683			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1	0x1f
684			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2	0x1f
685			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3	0x1f
686			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
687			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL	0x91
688			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0	0x91
689			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1	0x91
690			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2	0x91
691			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3	0x91
692		>;
693	};
694
695	pinctrl_enet_vio: dhcom-enet-vio-grp {
696		fsl,pins = <
697			MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x22
698		>;
699	};
700
701	pinctrl_ethphy0: dhcom-ethphy0-grp {
702		fsl,pins = <
703			/* ENET1_#RST Reset */
704			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x22
705			/* ENET1_#INT Interrupt */
706			MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19		0x22
707		>;
708	};
709
710	pinctrl_ethphy1: dhcom-ethphy1-grp {
711		fsl,pins = <
712			/* ENET1_#RST Reset */
713			MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02		0x11
714			/* ENET1_#INT Interrupt */
715			MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x11
716		>;
717	};
718
719	pinctrl_fec: dhcom-fec-grp {
720		fsl,pins = <
721			MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK		0x1f
722			MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3
723			MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3
724			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91
725			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91
726			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91
727			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91
728			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91
729			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91
730			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f
731			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f
732			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f
733			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f
734			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f
735			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f
736			MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER		0x1f
737		>;
738	};
739
740	pinctrl_flexcan1: dhcom-flexcan1-grp {
741		fsl,pins = <
742			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154
743			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154
744		>;
745	};
746
747	pinctrl_flexcan2: dhcom-flexcan2-grp {
748		fsl,pins = <
749			MX8MP_IOMUXC_UART3_RXD__CAN2_TX			0x154
750			MX8MP_IOMUXC_UART3_TXD__CAN2_RX			0x154
751		>;
752	};
753
754	pinctrl_flexspi: dhcom-flexspi-grp {
755		fsl,pins = <
756			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
757			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
758			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
759			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
760			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
761			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
762		>;
763	};
764
765	pinctrl_hdmi: dhcom-hdmi-grp {
766		fsl,pins = <
767			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x154
768			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x154
769		>;
770	};
771
772	pinctrl_i2c3: dhcom-i2c3-grp {
773		fsl,pins = <
774			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x40000084
775			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x40000084
776		>;
777	};
778
779	pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
780		fsl,pins = <
781			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x84
782			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x84
783		>;
784	};
785
786	pinctrl_i2c4: dhcom-i2c4-grp {
787		fsl,pins = <
788			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL			0x40000084
789			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA			0x40000084
790		>;
791	};
792
793	pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
794		fsl,pins = <
795			MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x84
796			MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x84
797		>;
798	};
799
800	pinctrl_i2c5: dhcom-i2c5-grp {
801		fsl,pins = <
802			MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL		0x40000084
803			MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA		0x40000084
804		>;
805	};
806
807	pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
808		fsl,pins = <
809			MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26		0x84
810			MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27		0x84
811		>;
812	};
813
814	pinctrl_pmic: dhcom-pmic-grp {
815		fsl,pins = <
816			/* PMIC_nINT */
817			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x40000090
818		>;
819	};
820
821	pinctrl_pwm1: dhcom-pwm1-grp {
822		fsl,pins = <
823			MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT		0x6
824		>;
825	};
826
827	pinctrl_rtc: dhcom-rtc-grp {
828		fsl,pins = <
829			/* RTC_#INT Interrupt */
830			MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05		0x40000080
831		>;
832	};
833
834	pinctrl_touch: dhcom-touch-grp {
835		fsl,pins = <
836			/* #TOUCH_INT */
837			MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x40000080
838		>;
839	};
840
841	pinctrl_uart1: dhcom-uart1-grp {
842		fsl,pins = <
843			/* Console UART */
844			MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX		0x49
845			MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX		0x49
846			MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x49
847			MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x49
848		>;
849	};
850
851	pinctrl_uart2: dhcom-uart2-grp {
852		fsl,pins = <
853			/* Bluetooth UART */
854			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x49
855			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x49
856			MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x49
857			MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x49
858		>;
859	};
860
861	pinctrl_uart2_bt: dhcom-uart2-bt-grp {
862		fsl,pins = <
863			/* BT_REG_EN */
864			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12		0x144
865		>;
866	};
867
868	pinctrl_uart3: dhcom-uart3-grp {
869		fsl,pins = <
870			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x49
871			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x49
872			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x49
873			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x49
874		>;
875	};
876
877	pinctrl_uart4: dhcom-uart4-grp {
878		fsl,pins = <
879			MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x49
880			MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x49
881		>;
882	};
883
884	pinctrl_usb0_vbus: dhcom-usb0-grp {
885		fsl,pins = <
886			MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID		0x0
887		>;
888	};
889
890	pinctrl_usb1_vbus: dhcom-usb1-grp {
891		fsl,pins = <
892			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x6
893			MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC		0x80
894		>;
895	};
896
897	pinctrl_usdhc1: dhcom-usdhc1-grp {
898		fsl,pins = <
899			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190
900			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0
901			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0
902			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0
903			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0
904			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0
905			/* WL_REG_EN */
906			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
907		>;
908	};
909
910	pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
911		fsl,pins = <
912			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194
913			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4
914			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4
915			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4
916			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4
917			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4
918			/* WL_REG_EN */
919			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
920		>;
921	};
922
923	pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
924		fsl,pins = <
925			MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196
926			MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6
927			MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6
928			MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6
929			MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6
930			MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6
931			/* WL_REG_EN */
932			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x144
933		>;
934	};
935
936	pinctrl_usdhc2: dhcom-usdhc2-grp {
937		fsl,pins = <
938			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
939			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
940			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
941			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
942			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
943			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
944			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
945		>;
946	};
947
948	pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
949		fsl,pins = <
950			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
951			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
952			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
953			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
954			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
955			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
956			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
957		>;
958	};
959
960	pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
961		fsl,pins = <
962			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
963			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
964			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
965			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
966			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
967			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
968			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
969		>;
970	};
971
972	pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
973		fsl,pins = <
974			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x20
975		>;
976	};
977
978	pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
979		fsl,pins = <
980			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x40000080
981		>;
982	};
983
984	pinctrl_usdhc3: dhcom-usdhc3-grp {
985		fsl,pins = <
986			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190
987			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0
988			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0
989			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0
990			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0
991			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0
992			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0
993			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0
994			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0
995			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0
996			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190
997			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
998		>;
999	};
1000
1001	pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1002		fsl,pins = <
1003			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194
1004			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4
1005			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4
1006			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4
1007			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4
1008			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4
1009			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4
1010			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4
1011			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4
1012			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4
1013			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194
1014			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1015		>;
1016	};
1017
1018	pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1019		fsl,pins = <
1020			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196
1021			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6
1022			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d6
1023			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d6
1024			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d6
1025			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d6
1026			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d6
1027			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d6
1028			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d6
1029			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d6
1030			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196
1031			MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B	0x141
1032		>;
1033	};
1034
1035	pinctrl_wdog: dhcom-wdog-grp {
1036		fsl,pins = <
1037			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6
1038		>;
1039	};
1040};
1041