1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 NXP
4 * Copyright (c) 2019 Engicam srl
5 * Copyright (c) 2020 Amarula Solutons(India)
6 */
7
8/dts-v1/;
9
10#include "imx8mp.dtsi"
11#include "imx8mp-icore-mx8mp.dtsi"
12#include <dt-bindings/usb/pd.h>
13
14/ {
15	model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
16	compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
17		     "fsl,imx8mp";
18
19	chosen {
20		stdout-path = &uart2;
21	};
22
23	reg_usb1_vbus: regulator-usb1 {
24		compatible = "regulator-fixed";
25		enable-active-high;
26		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
27		pinctrl-names = "default";
28		pinctrl-0 = <&pinctrl_reg_usb1>;
29		regulator-max-microvolt = <5000000>;
30		regulator-min-microvolt = <5000000>;
31		regulator-name = "usb1_host_vbus";
32	};
33
34	reg_usdhc2_vmmc: regulator-usdhc2 {
35		compatible = "regulator-fixed";
36		enable-active-high;
37		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38		pinctrl-names = "default";
39		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40		regulator-max-microvolt = <3300000>;
41		regulator-min-microvolt = <3300000>;
42		regulator-name = "VSD_3V3";
43	};
44};
45
46/* Ethernet */
47&eqos {
48	pinctrl-names = "default";
49	pinctrl-0 = <&pinctrl_eqos>;
50	phy-handle = <&ethphy0>;
51	phy-mode = "rgmii-id";
52	status = "okay";
53
54	mdio {
55		compatible = "snps,dwmac-mdio";
56		#address-cells = <1>;
57		#size-cells = <0>;
58
59		ethphy0: ethernet-phy@7 {
60			compatible = "ethernet-phy-ieee802.3-c22";
61			micrel,led-mode = <0>;
62			reg = <7>;
63		};
64	};
65};
66
67/* console */
68&uart2 {
69	pinctrl-names = "default";
70	pinctrl-0 = <&pinctrl_uart2>;
71	status = "okay";
72};
73
74&usb3_phy0 {
75	status = "okay";
76};
77
78&usb3_0 {
79	status = "okay";
80};
81
82&usb_dwc3_0 {
83	dr_mode = "host";
84	status = "okay";
85};
86
87&usb3_phy1 {
88	status = "okay";
89};
90
91&usb3_1 {
92	status = "okay";
93};
94
95&usb_dwc3_1 {
96	dr_mode = "host";
97	status = "okay";
98};
99
100/* SDCARD */
101&usdhc2 {
102	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
103	bus-width = <4>;
104	pinctrl-names = "default" ;
105	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
106	vmmc-supply = <&reg_usdhc2_vmmc>;
107	status = "okay";
108};
109
110&iomuxc {
111	pinctrl_eqos: eqosgrp {
112		fsl,pins = <
113			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
114			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
115			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
116			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
117			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
118			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
119			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
120			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
121			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
122			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
123			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
124			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
125			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
126			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
127			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10
128		>;
129	};
130
131	pinctrl_uart2: uart2grp {
132		fsl,pins = <
133			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40
134			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40
135		>;
136	};
137
138	pinctrl_uart3: uart3grp {
139		fsl,pins = <
140			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
141			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
142			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140
143		>;
144	};
145
146	pinctrl_usdhc2: usdhc2grp {
147		fsl,pins = <
148			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
149			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
150			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
151			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
152			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
153			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
154			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
155		>;
156	};
157
158	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
159		fsl,pins = <
160			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
161		>;
162	};
163
164	pinctrl_reg_usb1: regusb1grp {
165		fsl,pins = <
166			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10
167		>;
168	};
169
170	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
171		fsl,pins = <
172			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
173		>;
174	};
175};
176