1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3#include "imx8mp.dtsi"
4
5#include <dt-bindings/leds/common.h>
6
7/ {
8	aliases {
9		/* some of this aliases like backlight0, ethernetX and switch0
10		 * are needed for the bootloader.
11		 */
12		backlight0 = &backlight;
13		ethernet0 = &eqos;
14		ethernet1 = &lan1;
15		ethernet2 = &lan2;
16		rtc0 = &i2c_rtc;
17		rtc1 = &snvs_rtc;
18		switch0 = &switch;
19	};
20
21	/*
22	 * Backlight is present only on some of boards, so it is disabled by
23	 * default.
24	 */
25	backlight: backlight {
26		compatible = "pwm-backlight";
27		pinctrl-0 = <&pinctrl_backlight>;
28		pwms = <&pwm1 0 20000 0>;
29		power-supply = <&reg_24v>;
30		enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
31		brightness-levels = <0 255>;
32		num-interpolated-steps = <17>;
33		default-brightness-level = <8>;
34		status = "disabled";
35	};
36
37	leds {
38		compatible = "gpio-leds";
39		pinctrl-names = "default";
40		pinctrl-0 = <&pinctrl_gpio_led>;
41
42		led-0 {
43			label = "D1";
44			color = <LED_COLOR_ID_GREEN>;
45			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
46			function = LED_FUNCTION_STATUS;
47			default-state = "on";
48			linux,default-trigger = "heartbeat";
49		};
50
51		led-1 {
52			label = "D2";
53			color = <LED_COLOR_ID_GREEN>;
54			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
55			default-state = "off";
56		};
57
58		led-2 {
59			label = "D3";
60			color = <LED_COLOR_ID_GREEN>;
61			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
62			default-state = "on";
63		};
64	};
65
66	reg_1v2: regulator-1v2 {
67		compatible = "regulator-fixed";
68		vin-supply = <&reg_5v_p>;
69		regulator-name = "1V2";
70		regulator-min-microvolt = <1200000>;
71		regulator-max-microvolt = <1200000>;
72	};
73
74	reg_2v5: regulator-2v5 {
75		compatible = "regulator-fixed";
76		vin-supply = <&reg_5v_s>;
77		regulator-name = "2V5";
78		regulator-min-microvolt = <2500000>;
79		regulator-max-microvolt = <2500000>;
80	};
81
82	reg_3v3: regulator-3v3 {
83		compatible = "regulator-fixed";
84		vin-supply = <&reg_5v_s>;
85		regulator-name = "3V3";
86		regulator-min-microvolt = <3300000>;
87		regulator-max-microvolt = <3300000>;
88	};
89
90	/*
91	 * This regulator will provide power as long as possible even if
92	 * undervoltage is detected.
93	 */
94	reg_5v_p: regulator-5v-p {
95		compatible = "regulator-fixed";
96		regulator-name = "5V_P";
97		vin-supply = <&reg_24v>;
98		regulator-min-microvolt = <5000000>;
99		regulator-max-microvolt = <5000000>;
100	};
101
102	/*
103	 * This regulator will be automatically shutdown if undervoltage is
104	 * detected.
105	 */
106	reg_5v_s: regulator-5v-s {
107		compatible = "regulator-fixed";
108		regulator-name = "5V_S";
109		vin-supply = <&reg_24v>;
110		regulator-min-microvolt = <5000000>;
111		regulator-max-microvolt = <5000000>;
112	};
113
114	reg_24v: regulator-24v {
115		compatible = "regulator-fixed";
116		regulator-name = "24V";
117		regulator-min-microvolt = <24000000>;
118		regulator-max-microvolt = <24000000>;
119	};
120
121	reg_can2rs: regulator-can2rs {
122		compatible = "regulator-fixed";
123		regulator-name = "CAN2RS";
124		pinctrl-names = "default";
125		pinctrl-0 = <&pinctrl_can2rs>;
126		regulator-min-microvolt = <3300000>;
127		regulator-max-microvolt = <3300000>;
128		gpio = <&gpio4 22 GPIO_ACTIVE_LOW>;
129	};
130
131	reg_canrs: regulator-canrs {
132		compatible = "regulator-fixed";
133		regulator-name = "CANRS";
134		pinctrl-names = "default";
135		pinctrl-0 = <&pinctrl_canrs>;
136		regulator-min-microvolt = <3300000>;
137		regulator-max-microvolt = <3300000>;
138		gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
139	};
140
141	reg_tft_vcom: regulator-tft-vcom {
142		compatible = "pwm-regulator";
143		pwms = <&pwm4 0 20000 0>;
144		regulator-name = "VCOM";
145		vin-supply = <&reg_5v_s>;
146		regulator-min-microvolt = <3600000>;
147		regulator-max-microvolt = <3600000>;
148		regulator-always-on;
149		voltage-table = <3600000 26>;
150		status = "disabled";
151	};
152
153	reg_vsd_3v3: regulator-vsd-3v3 {
154		pinctrl-names = "default";
155		pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
156		vin-supply = <&reg_vdd_3v3>;
157		compatible = "regulator-fixed";
158		regulator-name = "VSD_3V3";
159		regulator-min-microvolt = <3300000>;
160		regulator-max-microvolt = <3300000>;
161		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
162		enable-active-high;
163	};
164};
165
166&A53_0 {
167	cpu-supply = <&reg_vdd_arm>;
168};
169
170&A53_1 {
171	cpu-supply = <&reg_vdd_arm>;
172};
173
174&A53_2 {
175	cpu-supply = <&reg_vdd_arm>;
176};
177
178&A53_3 {
179	cpu-supply = <&reg_vdd_arm>;
180};
181
182&ecspi2 {
183	pinctrl-names = "default";
184	pinctrl-0 = <&pinctrl_ecspi2>;
185	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
186	status = "okay";
187
188	adc: adc@0 {
189		compatible = "microchip,mcp3002";
190		reg = <0>;
191		vref-supply = <&reg_vdd_3v3>;
192		spi-max-frequency = <1000000>;
193		#io-channel-cells = <1>;
194	};
195};
196
197&eqos {
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_eqos>;
200	phy-mode = "rgmii-txid";
201	status = "okay";
202
203	fixed-link {
204		speed = <1000>;
205		full-duplex;
206	};
207};
208
209&flexcan1 {
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_flexcan1>;
212	xceiver-supply = <&reg_canrs>;
213	status = "okay";
214};
215
216&flexcan2 {
217	pinctrl-names = "default";
218	pinctrl-0 = <&pinctrl_flexcan2>;
219	xceiver-supply = <&reg_can2rs>;
220	status = "okay";
221};
222
223&i2c1 {
224	clock-frequency = <100000>;
225	pinctrl-names = "default";
226	pinctrl-0 = <&pinctrl_i2c1>;
227	status = "okay";
228
229	pmic@25 {
230		compatible = "nxp,pca9450c";
231		reg = <0x25>;
232		pinctrl-names = "default";
233		pinctrl-0 = <&pinctrl_pmic>;
234		interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>;
235		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
236
237		regulators {
238			reg_vdd_soc: BUCK1 {
239				regulator-name = "VDD_SOC";
240				regulator-min-microvolt = <600000>;
241				regulator-max-microvolt = <2187500>;
242				vin-supply = <&reg_5v_p>;
243				regulator-boot-on;
244				regulator-always-on;
245				regulator-ramp-delay = <3125>;
246			};
247
248			reg_vdd_arm: BUCK2 {
249				regulator-name = "VDD_ARM";
250				regulator-min-microvolt = <600000>;
251				regulator-max-microvolt = <2187500>;
252				vin-supply = <&reg_5v_p>;
253				regulator-boot-on;
254				regulator-always-on;
255				regulator-ramp-delay = <3125>;
256				nxp,dvs-run-voltage = <950000>;
257				nxp,dvs-standby-voltage = <850000>;
258			};
259
260			reg_vdd_3v3: BUCK4 {
261				regulator-name = "VDD_3V3";
262				regulator-min-microvolt = <600000>;
263				regulator-max-microvolt = <3400000>;
264				vin-supply = <&reg_5v_p>;
265				regulator-boot-on;
266				regulator-always-on;
267			};
268
269			reg_vdd_1v8: BUCK5 {
270				regulator-name = "VDD_1V8";
271				regulator-min-microvolt = <600000>;
272				regulator-max-microvolt = <3400000>;
273				vin-supply = <&reg_5v_p>;
274				regulator-boot-on;
275				regulator-always-on;
276			};
277
278			reg_nvcc_dram_1v1: BUCK6 {
279				regulator-name = "NVCC_DRAM_1V1";
280				regulator-min-microvolt = <600000>;
281				regulator-max-microvolt = <3400000>;
282				vin-supply = <&reg_5v_p>;
283				regulator-boot-on;
284				regulator-always-on;
285			};
286
287			reg_nvcc_snvs_1v8: LDO1 {
288				regulator-name = "NVCC_SNVS_1V8";
289				regulator-min-microvolt = <1600000>;
290				regulator-max-microvolt = <3300000>;
291				vin-supply = <&reg_5v_p>;
292				regulator-boot-on;
293				regulator-always-on;
294			};
295
296			reg_vdda_1v8: LDO3 {
297				regulator-name = "VDDA_1V8";
298				regulator-min-microvolt = <800000>;
299				regulator-max-microvolt = <3300000>;
300				vin-supply = <&reg_5v_p>;
301				regulator-boot-on;
302				regulator-always-on;
303			};
304
305			reg_nvcc_sd2: LDO5 {
306				regulator-name = "NVCC_SD2";
307				regulator-min-microvolt = <1800000>;
308				regulator-max-microvolt = <3300000>;
309				vin-supply = <&reg_5v_p>;
310				regulator-boot-on;
311				regulator-always-on;
312			};
313		};
314	};
315};
316
317&i2c3 {
318	clock-frequency = <100000>;
319	pinctrl-names = "default";
320	pinctrl-0 = <&pinctrl_i2c3>;
321	status = "okay";
322
323	i2c_rtc: rtc@51 {
324		compatible = "nxp,pcf85063tp";
325		reg = <0x51>;
326		pinctrl-names = "default";
327		pinctrl-0 = <&pinctrl_rtc>;
328		interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>;
329		quartz-load-femtofarads = <12500>;
330	};
331};
332
333&i2c4 {
334	clock-frequency = <380000>;
335	pinctrl-names = "default";
336	pinctrl-0 = <&pinctrl_i2c4>;
337	status = "okay";
338
339	switch: switch@5f {
340		compatible = "microchip,ksz9893";
341		pinctrl-names = "default";
342		pinctrl-0 = <&pinctrl_switch>;
343		reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
344		reg = <0x5f>;
345
346		ethernet-ports {
347			#address-cells = <1>;
348			#size-cells = <0>;
349
350			lan1: port@0 {
351				reg = <0>;
352				phy-mode = "internal";
353				label = "lan1";
354			};
355
356			lan2: port@1 {
357				reg = <1>;
358				phy-mode = "internal";
359				label = "lan2";
360			};
361
362			port@2 {
363				reg = <2>;
364				label = "cpu";
365				ethernet = <&eqos>;
366				phy-mode = "rgmii";
367				/* 2ns RX delay is implemented on PCB */
368				tx-internal-delay-ps = <2000>;
369				rx-internal-delay-ps = <0>;
370
371				fixed-link {
372					speed = <1000>;
373					full-duplex;
374				};
375			};
376		};
377	};
378};
379
380&pwm1 {
381	pinctrl-names = "default";
382	pinctrl-0 = <&pinctrl_pwm1>;
383};
384
385&pwm4 {
386	pinctrl-names = "default";
387	pinctrl-0 = <&pinctrl_pwm4>;
388};
389
390&uart1 {
391	pinctrl-names = "default";
392	pinctrl-0 = <&pinctrl_uart1>;
393	status = "okay";
394};
395
396&uart2 {
397	/* console */
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_uart2>;
400	status = "okay";
401};
402
403&usb3_0 {
404	status = "okay";
405};
406
407&usb3_1 {
408	status = "okay";
409};
410
411&usb3_phy0 {
412	vbus-supply = <&reg_3v3>;
413	status = "okay";
414};
415
416&usb3_phy1 {
417	vbus-supply = <&reg_3v3>;
418	status = "okay";
419};
420
421&usb_dwc3_0 {
422	dr_mode = "host";
423};
424
425&usb_dwc3_1 {
426	dr_mode = "host";
427};
428
429/* SD Card */
430&usdhc2 {
431	pinctrl-names = "default", "state_100mhz", "state_200mhz";
432	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
433	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
434	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
435	vmmc-supply = <&reg_vsd_3v3>;
436	vqmmc-supply = <&reg_nvcc_sd2>;
437	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
438	wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
439	bus-width = <4>;
440	status = "okay";
441};
442
443/* eMMC */
444&usdhc3 {
445	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
446	assigned-clock-rates = <400000000>;
447	pinctrl-names = "default", "state_100mhz", "state_200mhz";
448	pinctrl-0 = <&pinctrl_usdhc3>;
449	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
450	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
451	vmmc-supply = <&reg_vdd_3v3>;
452	vqmmc-supply = <&reg_vdd_1v8>;
453	bus-width = <8>;
454	no-sd;
455	no-sdio;
456	non-removable;
457	status = "okay";
458};
459
460&wdog1 {
461	pinctrl-names = "default";
462	pinctrl-0 = <&pinctrl_wdog>;
463	fsl,ext-reset-output;
464	status = "okay";
465};
466
467&iomuxc {
468	pinctrl_backlight: backlightgrp {
469		fsl,pins = <
470			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24			0x0100
471		>;
472	};
473
474	pinctrl_can2rs: can2rsgrp {
475		fsl,pins = <
476			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22			0x154
477		>;
478	};
479
480	pinctrl_canrs: canrsgrp {
481		fsl,pins = <
482			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21			0x154
483		>;
484	};
485
486	pinctrl_ecspi2: ecspi2grp {
487		fsl,pins = <
488			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK			0x44
489			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI			0x44
490			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO			0x44
491			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13			0x40
492		>;
493	};
494
495	pinctrl_eqos: eqosgrp {
496		fsl,pins = <
497			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91
498			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91
499			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91
500			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91
501			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91
502			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x91
503			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f
504			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f
505			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f
506			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f
507			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x1f
508			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f
509		>;
510	};
511
512	pinctrl_flexcan1: flexcan1grp {
513		fsl,pins = <
514			MX8MP_IOMUXC_SPDIF_RX__CAN1_RX				0x154
515			MX8MP_IOMUXC_SPDIF_TX__CAN1_TX				0x154
516		>;
517	};
518
519	pinctrl_flexcan2: flexcan2grp {
520		fsl,pins = <
521			MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX				0x154
522			MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX				0x154
523		>;
524	};
525
526	pinctrl_gpio_led: gpioledgrp {
527		fsl,pins = <
528			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05			0x19
529			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06			0x19
530			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07			0x19
531		>;
532	};
533
534	pinctrl_i2c1: i2c1grp {
535		fsl,pins = <
536			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL				0x400001c2
537			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA				0x400001c2
538		>;
539	};
540
541	pinctrl_i2c3: i2c3grp {
542		fsl,pins = <
543			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL				0x400001c2
544			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA				0x400001c2
545		>;
546	};
547
548	pinctrl_i2c4: i2c4grp {
549		fsl,pins = <
550			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL				0x400001c3
551			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA				0x400001c3
552		>;
553	};
554
555	pinctrl_pmic: pmicirqgrp {
556		fsl,pins = <
557			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03			0x41
558			MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04			0x41
559		>;
560	};
561
562	pinctrl_pwm1: pwm1grp {
563		fsl,pins = <
564			MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT			0x116
565		>;
566	};
567
568	pinctrl_pwm4: pwm4grp {
569		fsl,pins = <
570			MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT			0x116
571		>;
572	};
573
574	pinctrl_reg_vsd_3v3: regvsd3v3grp {
575		fsl,pins = <
576			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
577		>;
578	};
579
580	pinctrl_rtc: rtcgrp {
581		fsl,pins = <
582			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31			0x41
583		>;
584	};
585
586	pinctrl_switch: switchgrp {
587		fsl,pins = <
588			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00			0x41
589			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01			0x41
590		>;
591	};
592
593	pinctrl_touchscreen: touchscreengrp {
594		fsl,pins = <
595			/* external 10 k pull up */
596			/* CTP_INT */
597			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28			0x41
598			/* CTP_RST */
599			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29			0x41
600		>;
601	};
602
603	pinctrl_uart1: uart1grp {
604		fsl,pins = <
605			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX			0x140
606			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX			0x140
607			MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS			0x140
608		>;
609	};
610
611	pinctrl_uart2: uart2grp {
612		fsl,pins = <
613			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX			0x14f
614			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX			0x14f
615		>;
616	};
617
618	pinctrl_usdhc2: usdhc2grp {
619		fsl,pins = <
620			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK			0x190
621			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD			0x1d0
622			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0			0x1d0
623			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1			0x1d0
624			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2			0x1d0
625			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3			0x1d0
626		>;
627	};
628
629	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
630		fsl,pins = <
631			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK			0x194
632			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD			0x1d4
633			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0			0x1d4
634			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1			0x1d4
635			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2			0x1d4
636			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3			0x1d4
637		>;
638	};
639
640	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
641		fsl,pins = <
642			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK			0x196
643			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD			0x1d6
644			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0			0x1d6
645			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1			0x1d6
646			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2			0x1d6
647			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3			0x1d6
648		>;
649	};
650
651	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
652		fsl,pins = <
653			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12			0x1c4
654			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20				0x1c4
655		>;
656	};
657
658	pinctrl_usdhc3: usdhc3grp {
659		fsl,pins = <
660			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK			0x190
661			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD			0x1d0
662			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0			0x1d0
663			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1			0x1d0
664			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2			0x1d0
665			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3			0x1d0
666			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4			0x1d0
667			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5			0x1d0
668			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6			0x1d0
669			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7			0x1d0
670			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE			0x190
671		>;
672	};
673
674	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
675		fsl,pins = <
676			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK			0x194
677			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD			0x1d4
678			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0			0x1d4
679			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1			0x1d4
680			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2			0x1d4
681			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3			0x1d4
682			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4			0x1d4
683			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5			0x1d4
684			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6			0x1d4
685			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7			0x1d4
686			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE			0x194
687		>;
688	};
689
690	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
691		fsl,pins = <
692			MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK			0x196
693			MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD			0x1d6
694			MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0			0x1d6
695			MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1			0x1d6
696			MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2			0x1d6
697			MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3			0x1d6
698			MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4			0x1d6
699			MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5			0x1d6
700			MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6			0x1d6
701			MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7			0x1d6
702			MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE			0x196
703		>;
704	};
705
706	pinctrl_wdog: wdoggrp {
707		fsl,pins = <
708			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B			0xc6
709		>;
710	};
711};
712