1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 etm0: etm@28440000 { 308 compatible = "arm,coresight-etm4x", "arm,primecell"; 309 reg = <0x28440000 0x1000>; 310 cpu = <&A53_0>; 311 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 312 clock-names = "apb_pclk"; 313 314 out-ports { 315 port { 316 etm0_out_port: endpoint { 317 remote-endpoint = <&ca_funnel_in_port0>; 318 }; 319 }; 320 }; 321 }; 322 323 etm1: etm@28540000 { 324 compatible = "arm,coresight-etm4x", "arm,primecell"; 325 reg = <0x28540000 0x1000>; 326 cpu = <&A53_1>; 327 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 328 clock-names = "apb_pclk"; 329 330 out-ports { 331 port { 332 etm1_out_port: endpoint { 333 remote-endpoint = <&ca_funnel_in_port1>; 334 }; 335 }; 336 }; 337 }; 338 339 etm2: etm@28640000 { 340 compatible = "arm,coresight-etm4x", "arm,primecell"; 341 reg = <0x28640000 0x1000>; 342 cpu = <&A53_2>; 343 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 344 clock-names = "apb_pclk"; 345 346 out-ports { 347 port { 348 etm2_out_port: endpoint { 349 remote-endpoint = <&ca_funnel_in_port2>; 350 }; 351 }; 352 }; 353 }; 354 355 etm3: etm@28740000 { 356 compatible = "arm,coresight-etm4x", "arm,primecell"; 357 reg = <0x28740000 0x1000>; 358 cpu = <&A53_3>; 359 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 360 clock-names = "apb_pclk"; 361 362 out-ports { 363 port { 364 etm3_out_port: endpoint { 365 remote-endpoint = <&ca_funnel_in_port3>; 366 }; 367 }; 368 }; 369 }; 370 371 funnel { 372 /* 373 * non-configurable funnel don't show up on the AMBA 374 * bus. As such no need to add "arm,primecell". 375 */ 376 compatible = "arm,coresight-static-funnel"; 377 378 in-ports { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 port@0 { 383 reg = <0>; 384 385 ca_funnel_in_port0: endpoint { 386 remote-endpoint = <&etm0_out_port>; 387 }; 388 }; 389 390 port@1 { 391 reg = <1>; 392 393 ca_funnel_in_port1: endpoint { 394 remote-endpoint = <&etm1_out_port>; 395 }; 396 }; 397 398 port@2 { 399 reg = <2>; 400 401 ca_funnel_in_port2: endpoint { 402 remote-endpoint = <&etm2_out_port>; 403 }; 404 }; 405 406 port@3 { 407 reg = <3>; 408 409 ca_funnel_in_port3: endpoint { 410 remote-endpoint = <&etm3_out_port>; 411 }; 412 }; 413 }; 414 415 out-ports { 416 port { 417 ca_funnel_out_port0: endpoint { 418 remote-endpoint = <&hugo_funnel_in_port0>; 419 }; 420 }; 421 }; 422 }; 423 424 funnel@28c03000 { 425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 426 reg = <0x28c03000 0x1000>; 427 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 428 clock-names = "apb_pclk"; 429 430 in-ports { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 port@0 { 435 reg = <0>; 436 437 hugo_funnel_in_port0: endpoint { 438 remote-endpoint = <&ca_funnel_out_port0>; 439 }; 440 }; 441 442 port@1 { 443 reg = <1>; 444 445 hugo_funnel_in_port1: endpoint { 446 /* M7 input */ 447 }; 448 }; 449 450 port@2 { 451 reg = <2>; 452 453 hugo_funnel_in_port2: endpoint { 454 /* DSP input */ 455 }; 456 }; 457 /* the other input ports are not connect to anything */ 458 }; 459 460 out-ports { 461 port { 462 hugo_funnel_out_port0: endpoint { 463 remote-endpoint = <&etf_in_port>; 464 }; 465 }; 466 }; 467 }; 468 469 etf@28c04000 { 470 compatible = "arm,coresight-tmc", "arm,primecell"; 471 reg = <0x28c04000 0x1000>; 472 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 473 clock-names = "apb_pclk"; 474 475 in-ports { 476 port { 477 etf_in_port: endpoint { 478 remote-endpoint = <&hugo_funnel_out_port0>; 479 }; 480 }; 481 }; 482 483 out-ports { 484 port { 485 etf_out_port: endpoint { 486 remote-endpoint = <&etr_in_port>; 487 }; 488 }; 489 }; 490 }; 491 492 etr@28c06000 { 493 compatible = "arm,coresight-tmc", "arm,primecell"; 494 reg = <0x28c06000 0x1000>; 495 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 496 clock-names = "apb_pclk"; 497 498 in-ports { 499 port { 500 etr_in_port: endpoint { 501 remote-endpoint = <&etf_out_port>; 502 }; 503 }; 504 }; 505 }; 506 507 aips1: bus@30000000 { 508 compatible = "fsl,aips-bus", "simple-bus"; 509 reg = <0x30000000 0x400000>; 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges; 513 514 gpio1: gpio@30200000 { 515 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 516 reg = <0x30200000 0x10000>; 517 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 520 gpio-controller; 521 #gpio-cells = <2>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 gpio-ranges = <&iomuxc 0 5 30>; 525 }; 526 527 gpio2: gpio@30210000 { 528 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 529 reg = <0x30210000 0x10000>; 530 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 gpio-ranges = <&iomuxc 0 35 21>; 538 }; 539 540 gpio3: gpio@30220000 { 541 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 542 reg = <0x30220000 0x10000>; 543 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 546 gpio-controller; 547 #gpio-cells = <2>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 551 }; 552 553 gpio4: gpio@30230000 { 554 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 555 reg = <0x30230000 0x10000>; 556 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 559 gpio-controller; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 gpio-ranges = <&iomuxc 0 82 32>; 564 }; 565 566 gpio5: gpio@30240000 { 567 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 568 reg = <0x30240000 0x10000>; 569 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 gpio-ranges = <&iomuxc 0 114 30>; 577 }; 578 579 tmu: tmu@30260000 { 580 compatible = "fsl,imx8mp-tmu"; 581 reg = <0x30260000 0x10000>; 582 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 583 nvmem-cells = <&tmu_calib>; 584 nvmem-cell-names = "calib"; 585 #thermal-sensor-cells = <1>; 586 }; 587 588 wdog1: watchdog@30280000 { 589 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 590 reg = <0x30280000 0x10000>; 591 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 593 status = "disabled"; 594 }; 595 596 wdog2: watchdog@30290000 { 597 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 598 reg = <0x30290000 0x10000>; 599 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 601 status = "disabled"; 602 }; 603 604 wdog3: watchdog@302a0000 { 605 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 606 reg = <0x302a0000 0x10000>; 607 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 609 status = "disabled"; 610 }; 611 612 gpt1: timer@302d0000 { 613 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 614 reg = <0x302d0000 0x10000>; 615 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 617 clock-names = "ipg", "per"; 618 }; 619 620 gpt2: timer@302e0000 { 621 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 622 reg = <0x302e0000 0x10000>; 623 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 625 clock-names = "ipg", "per"; 626 }; 627 628 gpt3: timer@302f0000 { 629 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 630 reg = <0x302f0000 0x10000>; 631 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 633 clock-names = "ipg", "per"; 634 }; 635 636 iomuxc: pinctrl@30330000 { 637 compatible = "fsl,imx8mp-iomuxc"; 638 reg = <0x30330000 0x10000>; 639 }; 640 641 gpr: syscon@30340000 { 642 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 643 reg = <0x30340000 0x10000>; 644 }; 645 646 ocotp: efuse@30350000 { 647 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 648 reg = <0x30350000 0x10000>; 649 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 650 /* For nvmem subnodes */ 651 #address-cells = <1>; 652 #size-cells = <1>; 653 654 /* 655 * The register address below maps to the MX8M 656 * Fusemap Description Table entries this way. 657 * Assuming 658 * reg = <ADDR SIZE>; 659 * then 660 * Fuse Address = (ADDR * 4) + 0x400 661 * Note that if SIZE is greater than 4, then 662 * each subsequent fuse is located at offset 663 * +0x10 in Fusemap Description Table (e.g. 664 * reg = <0x8 0x8> describes fuses 0x420 and 665 * 0x430). 666 */ 667 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 668 reg = <0x8 0x8>; 669 }; 670 671 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 672 reg = <0x10 4>; 673 }; 674 675 eth_mac1: mac-address@90 { /* 0x640 */ 676 reg = <0x90 6>; 677 }; 678 679 eth_mac2: mac-address@96 { /* 0x658 */ 680 reg = <0x96 6>; 681 }; 682 683 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 684 reg = <0x264 0x10>; 685 }; 686 }; 687 688 anatop: clock-controller@30360000 { 689 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 690 reg = <0x30360000 0x10000>; 691 #clock-cells = <1>; 692 }; 693 694 snvs: snvs@30370000 { 695 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 696 reg = <0x30370000 0x10000>; 697 698 snvs_rtc: snvs-rtc-lp { 699 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 700 regmap = <&snvs>; 701 offset = <0x34>; 702 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 705 clock-names = "snvs-rtc"; 706 }; 707 708 snvs_pwrkey: snvs-powerkey { 709 compatible = "fsl,sec-v4.0-pwrkey"; 710 regmap = <&snvs>; 711 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 713 clock-names = "snvs-pwrkey"; 714 linux,keycode = <KEY_POWER>; 715 wakeup-source; 716 status = "disabled"; 717 }; 718 719 snvs_lpgpr: snvs-lpgpr { 720 compatible = "fsl,imx8mp-snvs-lpgpr", 721 "fsl,imx7d-snvs-lpgpr"; 722 }; 723 }; 724 725 clk: clock-controller@30380000 { 726 compatible = "fsl,imx8mp-ccm"; 727 reg = <0x30380000 0x10000>; 728 #clock-cells = <1>; 729 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 730 <&clk_ext3>, <&clk_ext4>; 731 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 732 "clk_ext3", "clk_ext4"; 733 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 734 <&clk IMX8MP_CLK_A53_CORE>, 735 <&clk IMX8MP_CLK_NOC>, 736 <&clk IMX8MP_CLK_NOC_IO>, 737 <&clk IMX8MP_CLK_GIC>; 738 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 739 <&clk IMX8MP_ARM_PLL_OUT>, 740 <&clk IMX8MP_SYS_PLL2_1000M>, 741 <&clk IMX8MP_SYS_PLL1_800M>, 742 <&clk IMX8MP_SYS_PLL2_500M>; 743 assigned-clock-rates = <0>, <0>, 744 <1000000000>, 745 <800000000>, 746 <500000000>; 747 }; 748 749 src: reset-controller@30390000 { 750 compatible = "fsl,imx8mp-src", "syscon"; 751 reg = <0x30390000 0x10000>; 752 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 753 #reset-cells = <1>; 754 }; 755 756 gpc: gpc@303a0000 { 757 compatible = "fsl,imx8mp-gpc"; 758 reg = <0x303a0000 0x1000>; 759 interrupt-parent = <&gic>; 760 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-controller; 762 #interrupt-cells = <3>; 763 764 pgc { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 pgc_mipi_phy1: power-domain@0 { 769 #power-domain-cells = <0>; 770 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 771 }; 772 773 pgc_pcie_phy: power-domain@1 { 774 #power-domain-cells = <0>; 775 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 776 }; 777 778 pgc_usb1_phy: power-domain@2 { 779 #power-domain-cells = <0>; 780 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 781 }; 782 783 pgc_usb2_phy: power-domain@3 { 784 #power-domain-cells = <0>; 785 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 786 }; 787 788 pgc_audio: power-domain@5 { 789 #power-domain-cells = <0>; 790 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 791 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 792 <&clk IMX8MP_CLK_AUDIO_AXI>; 793 }; 794 795 pgc_gpu2d: power-domain@6 { 796 #power-domain-cells = <0>; 797 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 798 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 799 power-domains = <&pgc_gpumix>; 800 }; 801 802 pgc_gpumix: power-domain@7 { 803 #power-domain-cells = <0>; 804 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 805 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 806 <&clk IMX8MP_CLK_GPU_AHB>; 807 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 808 <&clk IMX8MP_CLK_GPU_AHB>; 809 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 810 <&clk IMX8MP_SYS_PLL1_800M>; 811 assigned-clock-rates = <800000000>, <400000000>; 812 }; 813 814 pgc_gpu3d: power-domain@9 { 815 #power-domain-cells = <0>; 816 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 817 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 818 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 819 power-domains = <&pgc_gpumix>; 820 }; 821 822 pgc_mediamix: power-domain@10 { 823 #power-domain-cells = <0>; 824 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 825 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 826 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 827 }; 828 829 pgc_mipi_phy2: power-domain@16 { 830 #power-domain-cells = <0>; 831 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 832 }; 833 834 pgc_hsiomix: power-domain@17 { 835 #power-domain-cells = <0>; 836 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 837 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 838 <&clk IMX8MP_CLK_HSIO_ROOT>; 839 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 840 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 841 assigned-clock-rates = <500000000>; 842 }; 843 844 pgc_ispdwp: power-domain@18 { 845 #power-domain-cells = <0>; 846 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 847 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 848 }; 849 850 pgc_vpumix: power-domain@19 { 851 #power-domain-cells = <0>; 852 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 853 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 854 }; 855 856 pgc_vpu_g1: power-domain@20 { 857 #power-domain-cells = <0>; 858 power-domains = <&pgc_vpumix>; 859 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 860 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 861 }; 862 863 pgc_vpu_g2: power-domain@21 { 864 #power-domain-cells = <0>; 865 power-domains = <&pgc_vpumix>; 866 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 867 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 868 }; 869 870 pgc_vpu_vc8000e: power-domain@22 { 871 #power-domain-cells = <0>; 872 power-domains = <&pgc_vpumix>; 873 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 874 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 875 }; 876 877 pgc_mlmix: power-domain@24 { 878 #power-domain-cells = <0>; 879 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 880 clocks = <&clk IMX8MP_CLK_ML_AXI>, 881 <&clk IMX8MP_CLK_ML_AHB>, 882 <&clk IMX8MP_CLK_NPU_ROOT>; 883 }; 884 }; 885 }; 886 }; 887 888 aips2: bus@30400000 { 889 compatible = "fsl,aips-bus", "simple-bus"; 890 reg = <0x30400000 0x400000>; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 ranges; 894 895 pwm1: pwm@30660000 { 896 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 897 reg = <0x30660000 0x10000>; 898 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 900 <&clk IMX8MP_CLK_PWM1_ROOT>; 901 clock-names = "ipg", "per"; 902 #pwm-cells = <3>; 903 status = "disabled"; 904 }; 905 906 pwm2: pwm@30670000 { 907 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 908 reg = <0x30670000 0x10000>; 909 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 911 <&clk IMX8MP_CLK_PWM2_ROOT>; 912 clock-names = "ipg", "per"; 913 #pwm-cells = <3>; 914 status = "disabled"; 915 }; 916 917 pwm3: pwm@30680000 { 918 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 919 reg = <0x30680000 0x10000>; 920 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 922 <&clk IMX8MP_CLK_PWM3_ROOT>; 923 clock-names = "ipg", "per"; 924 #pwm-cells = <3>; 925 status = "disabled"; 926 }; 927 928 pwm4: pwm@30690000 { 929 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 930 reg = <0x30690000 0x10000>; 931 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 933 <&clk IMX8MP_CLK_PWM4_ROOT>; 934 clock-names = "ipg", "per"; 935 #pwm-cells = <3>; 936 status = "disabled"; 937 }; 938 939 system_counter: timer@306a0000 { 940 compatible = "nxp,sysctr-timer"; 941 reg = <0x306a0000 0x20000>; 942 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&osc_24m>; 944 clock-names = "per"; 945 }; 946 947 gpt6: timer@306e0000 { 948 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 949 reg = <0x306e0000 0x10000>; 950 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 952 clock-names = "ipg", "per"; 953 }; 954 955 gpt5: timer@306f0000 { 956 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 957 reg = <0x306f0000 0x10000>; 958 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 960 clock-names = "ipg", "per"; 961 }; 962 963 gpt4: timer@30700000 { 964 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 965 reg = <0x30700000 0x10000>; 966 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 968 clock-names = "ipg", "per"; 969 }; 970 }; 971 972 aips3: bus@30800000 { 973 compatible = "fsl,aips-bus", "simple-bus"; 974 reg = <0x30800000 0x400000>; 975 #address-cells = <1>; 976 #size-cells = <1>; 977 ranges; 978 979 spba-bus@30800000 { 980 compatible = "fsl,spba-bus", "simple-bus"; 981 reg = <0x30800000 0x100000>; 982 #address-cells = <1>; 983 #size-cells = <1>; 984 ranges; 985 986 ecspi1: spi@30820000 { 987 #address-cells = <1>; 988 #size-cells = <0>; 989 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 990 reg = <0x30820000 0x10000>; 991 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 993 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 994 clock-names = "ipg", "per"; 995 assigned-clock-rates = <80000000>; 996 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 997 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 998 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 999 dma-names = "rx", "tx"; 1000 status = "disabled"; 1001 }; 1002 1003 ecspi2: spi@30830000 { 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1007 reg = <0x30830000 0x10000>; 1008 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1010 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1011 clock-names = "ipg", "per"; 1012 assigned-clock-rates = <80000000>; 1013 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1014 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1015 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1016 dma-names = "rx", "tx"; 1017 status = "disabled"; 1018 }; 1019 1020 ecspi3: spi@30840000 { 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1024 reg = <0x30840000 0x10000>; 1025 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1027 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1028 clock-names = "ipg", "per"; 1029 assigned-clock-rates = <80000000>; 1030 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1031 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1032 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1033 dma-names = "rx", "tx"; 1034 status = "disabled"; 1035 }; 1036 1037 uart1: serial@30860000 { 1038 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1039 reg = <0x30860000 0x10000>; 1040 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1042 <&clk IMX8MP_CLK_UART1_ROOT>; 1043 clock-names = "ipg", "per"; 1044 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1045 dma-names = "rx", "tx"; 1046 status = "disabled"; 1047 }; 1048 1049 uart3: serial@30880000 { 1050 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1051 reg = <0x30880000 0x10000>; 1052 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1054 <&clk IMX8MP_CLK_UART3_ROOT>; 1055 clock-names = "ipg", "per"; 1056 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1057 dma-names = "rx", "tx"; 1058 status = "disabled"; 1059 }; 1060 1061 uart2: serial@30890000 { 1062 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1063 reg = <0x30890000 0x10000>; 1064 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1066 <&clk IMX8MP_CLK_UART2_ROOT>; 1067 clock-names = "ipg", "per"; 1068 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1069 dma-names = "rx", "tx"; 1070 status = "disabled"; 1071 }; 1072 1073 flexcan1: can@308c0000 { 1074 compatible = "fsl,imx8mp-flexcan"; 1075 reg = <0x308c0000 0x10000>; 1076 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1078 <&clk IMX8MP_CLK_CAN1_ROOT>; 1079 clock-names = "ipg", "per"; 1080 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1081 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1082 assigned-clock-rates = <40000000>; 1083 fsl,clk-source = /bits/ 8 <0>; 1084 fsl,stop-mode = <&gpr 0x10 4>; 1085 status = "disabled"; 1086 }; 1087 1088 flexcan2: can@308d0000 { 1089 compatible = "fsl,imx8mp-flexcan"; 1090 reg = <0x308d0000 0x10000>; 1091 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1093 <&clk IMX8MP_CLK_CAN2_ROOT>; 1094 clock-names = "ipg", "per"; 1095 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1096 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1097 assigned-clock-rates = <40000000>; 1098 fsl,clk-source = /bits/ 8 <0>; 1099 fsl,stop-mode = <&gpr 0x10 5>; 1100 status = "disabled"; 1101 }; 1102 }; 1103 1104 crypto: crypto@30900000 { 1105 compatible = "fsl,sec-v4.0"; 1106 #address-cells = <1>; 1107 #size-cells = <1>; 1108 reg = <0x30900000 0x40000>; 1109 ranges = <0 0x30900000 0x40000>; 1110 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&clk IMX8MP_CLK_AHB>, 1112 <&clk IMX8MP_CLK_IPG_ROOT>; 1113 clock-names = "aclk", "ipg"; 1114 1115 sec_jr0: jr@1000 { 1116 compatible = "fsl,sec-v4.0-job-ring"; 1117 reg = <0x1000 0x1000>; 1118 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1119 status = "disabled"; 1120 }; 1121 1122 sec_jr1: jr@2000 { 1123 compatible = "fsl,sec-v4.0-job-ring"; 1124 reg = <0x2000 0x1000>; 1125 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1126 }; 1127 1128 sec_jr2: jr@3000 { 1129 compatible = "fsl,sec-v4.0-job-ring"; 1130 reg = <0x3000 0x1000>; 1131 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1132 }; 1133 }; 1134 1135 i2c1: i2c@30a20000 { 1136 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 reg = <0x30a20000 0x10000>; 1140 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1142 status = "disabled"; 1143 }; 1144 1145 i2c2: i2c@30a30000 { 1146 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 reg = <0x30a30000 0x10000>; 1150 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c3: i2c@30a40000 { 1156 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 reg = <0x30a40000 0x10000>; 1160 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1162 status = "disabled"; 1163 }; 1164 1165 i2c4: i2c@30a50000 { 1166 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 reg = <0x30a50000 0x10000>; 1170 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1172 status = "disabled"; 1173 }; 1174 1175 uart4: serial@30a60000 { 1176 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1177 reg = <0x30a60000 0x10000>; 1178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1180 <&clk IMX8MP_CLK_UART4_ROOT>; 1181 clock-names = "ipg", "per"; 1182 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1183 dma-names = "rx", "tx"; 1184 status = "disabled"; 1185 }; 1186 1187 mu: mailbox@30aa0000 { 1188 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1189 reg = <0x30aa0000 0x10000>; 1190 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1191 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1192 #mbox-cells = <2>; 1193 }; 1194 1195 mu2: mailbox@30e60000 { 1196 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1197 reg = <0x30e60000 0x10000>; 1198 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1199 #mbox-cells = <2>; 1200 status = "disabled"; 1201 }; 1202 1203 i2c5: i2c@30ad0000 { 1204 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 reg = <0x30ad0000 0x10000>; 1208 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1210 status = "disabled"; 1211 }; 1212 1213 i2c6: i2c@30ae0000 { 1214 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 reg = <0x30ae0000 0x10000>; 1218 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1220 status = "disabled"; 1221 }; 1222 1223 usdhc1: mmc@30b40000 { 1224 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1225 reg = <0x30b40000 0x10000>; 1226 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&clk IMX8MP_CLK_DUMMY>, 1228 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1229 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1230 clock-names = "ipg", "ahb", "per"; 1231 fsl,tuning-start-tap = <20>; 1232 fsl,tuning-step = <2>; 1233 bus-width = <4>; 1234 status = "disabled"; 1235 }; 1236 1237 usdhc2: mmc@30b50000 { 1238 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1239 reg = <0x30b50000 0x10000>; 1240 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&clk IMX8MP_CLK_DUMMY>, 1242 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1243 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1244 clock-names = "ipg", "ahb", "per"; 1245 fsl,tuning-start-tap = <20>; 1246 fsl,tuning-step = <2>; 1247 bus-width = <4>; 1248 status = "disabled"; 1249 }; 1250 1251 usdhc3: mmc@30b60000 { 1252 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1253 reg = <0x30b60000 0x10000>; 1254 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&clk IMX8MP_CLK_DUMMY>, 1256 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1257 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1258 clock-names = "ipg", "ahb", "per"; 1259 fsl,tuning-start-tap = <20>; 1260 fsl,tuning-step = <2>; 1261 bus-width = <4>; 1262 status = "disabled"; 1263 }; 1264 1265 flexspi: spi@30bb0000 { 1266 compatible = "nxp,imx8mp-fspi"; 1267 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1268 reg-names = "fspi_base", "fspi_mmap"; 1269 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1271 <&clk IMX8MP_CLK_QSPI_ROOT>; 1272 clock-names = "fspi_en", "fspi"; 1273 assigned-clock-rates = <80000000>; 1274 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 sdma1: dma-controller@30bd0000 { 1281 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1282 reg = <0x30bd0000 0x10000>; 1283 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1285 <&clk IMX8MP_CLK_AHB>; 1286 clock-names = "ipg", "ahb"; 1287 #dma-cells = <3>; 1288 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1289 }; 1290 1291 fec: ethernet@30be0000 { 1292 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1293 reg = <0x30be0000 0x10000>; 1294 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1299 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1300 <&clk IMX8MP_CLK_ENET_TIMER>, 1301 <&clk IMX8MP_CLK_ENET_REF>, 1302 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1303 clock-names = "ipg", "ahb", "ptp", 1304 "enet_clk_ref", "enet_out"; 1305 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1306 <&clk IMX8MP_CLK_ENET_TIMER>, 1307 <&clk IMX8MP_CLK_ENET_REF>, 1308 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1309 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1310 <&clk IMX8MP_SYS_PLL2_100M>, 1311 <&clk IMX8MP_SYS_PLL2_125M>, 1312 <&clk IMX8MP_SYS_PLL2_50M>; 1313 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1314 fsl,num-tx-queues = <3>; 1315 fsl,num-rx-queues = <3>; 1316 nvmem-cells = <ð_mac1>; 1317 nvmem-cell-names = "mac-address"; 1318 fsl,stop-mode = <&gpr 0x10 3>; 1319 status = "disabled"; 1320 }; 1321 1322 eqos: ethernet@30bf0000 { 1323 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1324 reg = <0x30bf0000 0x10000>; 1325 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1327 interrupt-names = "macirq", "eth_wake_irq"; 1328 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1329 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1330 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1331 <&clk IMX8MP_CLK_ENET_QOS>; 1332 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1333 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1334 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1335 <&clk IMX8MP_CLK_ENET_QOS>; 1336 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1337 <&clk IMX8MP_SYS_PLL2_100M>, 1338 <&clk IMX8MP_SYS_PLL2_125M>; 1339 assigned-clock-rates = <0>, <100000000>, <125000000>; 1340 nvmem-cells = <ð_mac2>; 1341 nvmem-cell-names = "mac-address"; 1342 intf_mode = <&gpr 0x4>; 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 aips5: bus@30c00000 { 1348 compatible = "fsl,aips-bus", "simple-bus"; 1349 reg = <0x30c00000 0x400000>; 1350 #address-cells = <1>; 1351 #size-cells = <1>; 1352 ranges; 1353 1354 spba-bus@30c00000 { 1355 compatible = "fsl,spba-bus", "simple-bus"; 1356 reg = <0x30c00000 0x100000>; 1357 #address-cells = <1>; 1358 #size-cells = <1>; 1359 ranges; 1360 1361 sai1: sai@30c10000 { 1362 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1363 reg = <0x30c10000 0x10000>; 1364 #sound-dai-cells = <0>; 1365 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1366 <&clk IMX8MP_CLK_DUMMY>, 1367 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1368 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1369 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1370 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1371 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1372 dma-names = "rx", "tx"; 1373 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1374 status = "disabled"; 1375 }; 1376 1377 sai2: sai@30c20000 { 1378 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1379 reg = <0x30c20000 0x10000>; 1380 #sound-dai-cells = <0>; 1381 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1382 <&clk IMX8MP_CLK_DUMMY>, 1383 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1384 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1385 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1386 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1387 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1388 dma-names = "rx", "tx"; 1389 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1390 status = "disabled"; 1391 }; 1392 1393 sai3: sai@30c30000 { 1394 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1395 reg = <0x30c30000 0x10000>; 1396 #sound-dai-cells = <0>; 1397 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1398 <&clk IMX8MP_CLK_DUMMY>, 1399 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1400 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1401 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1402 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1403 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1404 dma-names = "rx", "tx"; 1405 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1406 status = "disabled"; 1407 }; 1408 1409 sai5: sai@30c50000 { 1410 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1411 reg = <0x30c50000 0x10000>; 1412 #sound-dai-cells = <0>; 1413 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1414 <&clk IMX8MP_CLK_DUMMY>, 1415 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1416 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1417 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1418 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1419 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1420 dma-names = "rx", "tx"; 1421 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1422 status = "disabled"; 1423 }; 1424 1425 sai6: sai@30c60000 { 1426 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1427 reg = <0x30c60000 0x10000>; 1428 #sound-dai-cells = <0>; 1429 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1430 <&clk IMX8MP_CLK_DUMMY>, 1431 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1432 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1433 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1434 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1435 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1436 dma-names = "rx", "tx"; 1437 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1438 status = "disabled"; 1439 }; 1440 1441 sai7: sai@30c80000 { 1442 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1443 reg = <0x30c80000 0x10000>; 1444 #sound-dai-cells = <0>; 1445 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1446 <&clk IMX8MP_CLK_DUMMY>, 1447 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1448 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1449 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1450 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1451 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1452 dma-names = "rx", "tx"; 1453 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1454 status = "disabled"; 1455 }; 1456 }; 1457 1458 sdma3: dma-controller@30e00000 { 1459 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1460 reg = <0x30e00000 0x10000>; 1461 #dma-cells = <3>; 1462 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1463 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1464 clock-names = "ipg", "ahb"; 1465 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1466 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1467 }; 1468 1469 sdma2: dma-controller@30e10000 { 1470 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1471 reg = <0x30e10000 0x10000>; 1472 #dma-cells = <3>; 1473 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1474 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1475 clock-names = "ipg", "ahb"; 1476 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1477 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1478 }; 1479 1480 audio_blk_ctrl: clock-controller@30e20000 { 1481 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1482 reg = <0x30e20000 0x10000>; 1483 #clock-cells = <1>; 1484 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1485 <&clk IMX8MP_CLK_SAI1>, 1486 <&clk IMX8MP_CLK_SAI2>, 1487 <&clk IMX8MP_CLK_SAI3>, 1488 <&clk IMX8MP_CLK_SAI5>, 1489 <&clk IMX8MP_CLK_SAI6>, 1490 <&clk IMX8MP_CLK_SAI7>; 1491 clock-names = "ahb", 1492 "sai1", "sai2", "sai3", 1493 "sai5", "sai6", "sai7"; 1494 power-domains = <&pgc_audio>; 1495 }; 1496 }; 1497 1498 noc: interconnect@32700000 { 1499 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1500 reg = <0x32700000 0x100000>; 1501 clocks = <&clk IMX8MP_CLK_NOC>; 1502 #interconnect-cells = <1>; 1503 operating-points-v2 = <&noc_opp_table>; 1504 1505 noc_opp_table: opp-table { 1506 compatible = "operating-points-v2"; 1507 1508 opp-200000000 { 1509 opp-hz = /bits/ 64 <200000000>; 1510 }; 1511 1512 opp-1000000000 { 1513 opp-hz = /bits/ 64 <1000000000>; 1514 }; 1515 }; 1516 }; 1517 1518 aips4: bus@32c00000 { 1519 compatible = "fsl,aips-bus", "simple-bus"; 1520 reg = <0x32c00000 0x400000>; 1521 #address-cells = <1>; 1522 #size-cells = <1>; 1523 ranges; 1524 1525 isi_0: isi@32e00000 { 1526 compatible = "fsl,imx8mp-isi"; 1527 reg = <0x32e00000 0x4000>; 1528 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1530 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1531 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1532 clock-names = "axi", "apb"; 1533 fsl,blk-ctrl = <&media_blk_ctrl>; 1534 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1535 status = "disabled"; 1536 1537 ports { 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 port@0 { 1542 reg = <0>; 1543 1544 isi_in_0: endpoint { 1545 remote-endpoint = <&mipi_csi_0_out>; 1546 }; 1547 }; 1548 1549 port@1 { 1550 reg = <1>; 1551 1552 isi_in_1: endpoint { 1553 remote-endpoint = <&mipi_csi_1_out>; 1554 }; 1555 }; 1556 }; 1557 }; 1558 1559 dewarp: dwe@32e30000 { 1560 compatible = "nxp,imx8mp-dw100"; 1561 reg = <0x32e30000 0x10000>; 1562 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1563 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1564 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1565 clock-names = "axi", "ahb"; 1566 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1567 }; 1568 1569 mipi_csi_0: csi@32e40000 { 1570 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1571 reg = <0x32e40000 0x10000>; 1572 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1573 clock-frequency = <500000000>; 1574 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1575 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1576 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1577 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1578 clock-names = "pclk", "wrap", "phy", "axi"; 1579 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; 1580 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1581 assigned-clock-rates = <500000000>; 1582 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1583 status = "disabled"; 1584 1585 ports { 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 1589 port@0 { 1590 reg = <0>; 1591 }; 1592 1593 port@1 { 1594 reg = <1>; 1595 1596 mipi_csi_0_out: endpoint { 1597 remote-endpoint = <&isi_in_0>; 1598 }; 1599 }; 1600 }; 1601 }; 1602 1603 mipi_csi_1: csi@32e50000 { 1604 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1605 reg = <0x32e50000 0x10000>; 1606 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1607 clock-frequency = <266000000>; 1608 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1609 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1610 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1611 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1612 clock-names = "pclk", "wrap", "phy", "axi"; 1613 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; 1614 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1615 assigned-clock-rates = <266000000>; 1616 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1617 status = "disabled"; 1618 1619 ports { 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 1623 port@0 { 1624 reg = <0>; 1625 }; 1626 1627 port@1 { 1628 reg = <1>; 1629 1630 mipi_csi_1_out: endpoint { 1631 remote-endpoint = <&isi_in_1>; 1632 }; 1633 }; 1634 }; 1635 }; 1636 1637 mipi_dsi: dsi@32e60000 { 1638 compatible = "fsl,imx8mp-mipi-dsim"; 1639 reg = <0x32e60000 0x400>; 1640 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1641 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1642 clock-names = "bus_clk", "sclk_mipi"; 1643 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1644 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1645 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1646 <&clk IMX8MP_CLK_24M>; 1647 assigned-clock-rates = <200000000>, <24000000>; 1648 samsung,pll-clock-frequency = <24000000>; 1649 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1650 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1651 status = "disabled"; 1652 1653 ports { 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 1657 port@0 { 1658 reg = <0>; 1659 1660 dsim_from_lcdif1: endpoint { 1661 remote-endpoint = <&lcdif1_to_dsim>; 1662 }; 1663 }; 1664 }; 1665 }; 1666 1667 lcdif1: display-controller@32e80000 { 1668 compatible = "fsl,imx8mp-lcdif"; 1669 reg = <0x32e80000 0x10000>; 1670 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1671 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1672 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1673 clock-names = "pix", "axi", "disp_axi"; 1674 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1675 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1676 status = "disabled"; 1677 1678 port { 1679 lcdif1_to_dsim: endpoint { 1680 remote-endpoint = <&dsim_from_lcdif1>; 1681 }; 1682 }; 1683 }; 1684 1685 lcdif2: display-controller@32e90000 { 1686 compatible = "fsl,imx8mp-lcdif"; 1687 reg = <0x32e90000 0x10000>; 1688 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1689 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1690 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1691 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1692 clock-names = "pix", "axi", "disp_axi"; 1693 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1694 status = "disabled"; 1695 1696 port { 1697 lcdif2_to_ldb: endpoint { 1698 remote-endpoint = <&ldb_from_lcdif2>; 1699 }; 1700 }; 1701 }; 1702 1703 media_blk_ctrl: blk-ctrl@32ec0000 { 1704 compatible = "fsl,imx8mp-media-blk-ctrl", 1705 "syscon"; 1706 reg = <0x32ec0000 0x10000>; 1707 #address-cells = <1>; 1708 #size-cells = <1>; 1709 power-domains = <&pgc_mediamix>, 1710 <&pgc_mipi_phy1>, 1711 <&pgc_mipi_phy1>, 1712 <&pgc_mediamix>, 1713 <&pgc_mediamix>, 1714 <&pgc_mipi_phy2>, 1715 <&pgc_mediamix>, 1716 <&pgc_ispdwp>, 1717 <&pgc_ispdwp>, 1718 <&pgc_mipi_phy2>; 1719 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1720 "lcdif1", "isi", "mipi-csi2", 1721 "lcdif2", "isp", "dwe", 1722 "mipi-dsi2"; 1723 interconnects = 1724 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1725 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1726 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1727 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1728 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1729 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1730 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1731 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1732 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1733 "isi1", "isi2", "isp0", "isp1", 1734 "dwe"; 1735 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1736 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1737 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1738 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1739 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1740 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1741 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1742 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1743 clock-names = "apb", "axi", "cam1", "cam2", 1744 "disp1", "disp2", "isp", "phy"; 1745 1746 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1747 <&clk IMX8MP_CLK_MEDIA_APB>, 1748 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1749 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1750 <&clk IMX8MP_VIDEO_PLL1>; 1751 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1752 <&clk IMX8MP_SYS_PLL1_800M>, 1753 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1754 <&clk IMX8MP_VIDEO_PLL1_OUT>; 1755 assigned-clock-rates = <500000000>, <200000000>, 1756 <0>, <0>, <1039500000>; 1757 #power-domain-cells = <1>; 1758 1759 lvds_bridge: bridge@5c { 1760 compatible = "fsl,imx8mp-ldb"; 1761 reg = <0x5c 0x4>, <0x128 0x4>; 1762 reg-names = "ldb", "lvds"; 1763 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1764 clock-names = "ldb"; 1765 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1766 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1767 status = "disabled"; 1768 1769 ports { 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 1773 port@0 { 1774 reg = <0>; 1775 1776 ldb_from_lcdif2: endpoint { 1777 remote-endpoint = <&lcdif2_to_ldb>; 1778 }; 1779 }; 1780 1781 port@1 { 1782 reg = <1>; 1783 1784 ldb_lvds_ch0: endpoint { 1785 }; 1786 }; 1787 1788 port@2 { 1789 reg = <2>; 1790 1791 ldb_lvds_ch1: endpoint { 1792 }; 1793 }; 1794 }; 1795 }; 1796 }; 1797 1798 pcie_phy: pcie-phy@32f00000 { 1799 compatible = "fsl,imx8mp-pcie-phy"; 1800 reg = <0x32f00000 0x10000>; 1801 resets = <&src IMX8MP_RESET_PCIEPHY>, 1802 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1803 reset-names = "pciephy", "perst"; 1804 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1805 #phy-cells = <0>; 1806 status = "disabled"; 1807 }; 1808 1809 hsio_blk_ctrl: blk-ctrl@32f10000 { 1810 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1811 reg = <0x32f10000 0x24>; 1812 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1813 <&clk IMX8MP_CLK_PCIE_ROOT>; 1814 clock-names = "usb", "pcie"; 1815 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1816 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1817 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1818 power-domain-names = "bus", "usb", "usb-phy1", 1819 "usb-phy2", "pcie", "pcie-phy"; 1820 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1821 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1822 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1823 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1824 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1825 #power-domain-cells = <1>; 1826 #clock-cells = <0>; 1827 }; 1828 }; 1829 1830 pcie: pcie@33800000 { 1831 compatible = "fsl,imx8mp-pcie"; 1832 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1833 reg-names = "dbi", "config"; 1834 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1835 <&clk IMX8MP_CLK_HSIO_AXI>, 1836 <&clk IMX8MP_CLK_PCIE_ROOT>; 1837 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1838 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1839 assigned-clock-rates = <10000000>; 1840 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1841 #address-cells = <3>; 1842 #size-cells = <2>; 1843 device_type = "pci"; 1844 bus-range = <0x00 0xff>; 1845 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1846 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1847 num-lanes = <1>; 1848 num-viewport = <4>; 1849 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1850 interrupt-names = "msi"; 1851 #interrupt-cells = <1>; 1852 interrupt-map-mask = <0 0 0 0x7>; 1853 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1854 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1855 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1856 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1857 fsl,max-link-speed = <3>; 1858 linux,pci-domain = <0>; 1859 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1860 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1861 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1862 reset-names = "apps", "turnoff"; 1863 phys = <&pcie_phy>; 1864 phy-names = "pcie-phy"; 1865 status = "disabled"; 1866 }; 1867 1868 pcie_ep: pcie-ep@33800000 { 1869 compatible = "fsl,imx8mp-pcie-ep"; 1870 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 1871 reg-names = "dbi", "addr_space"; 1872 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1873 <&clk IMX8MP_CLK_HSIO_AXI>, 1874 <&clk IMX8MP_CLK_PCIE_ROOT>; 1875 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1876 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1877 assigned-clock-rates = <10000000>; 1878 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1879 num-lanes = <1>; 1880 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 1881 interrupt-names = "dma"; 1882 fsl,max-link-speed = <3>; 1883 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1884 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1885 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1886 reset-names = "apps", "turnoff"; 1887 phys = <&pcie_phy>; 1888 phy-names = "pcie-phy"; 1889 num-ib-windows = <4>; 1890 num-ob-windows = <4>; 1891 status = "disabled"; 1892 }; 1893 1894 gpu3d: gpu@38000000 { 1895 compatible = "vivante,gc"; 1896 reg = <0x38000000 0x8000>; 1897 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1898 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1899 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1900 <&clk IMX8MP_CLK_GPU_ROOT>, 1901 <&clk IMX8MP_CLK_GPU_AHB>; 1902 clock-names = "core", "shader", "bus", "reg"; 1903 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1904 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1905 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1906 <&clk IMX8MP_SYS_PLL1_800M>; 1907 assigned-clock-rates = <800000000>, <800000000>; 1908 power-domains = <&pgc_gpu3d>; 1909 }; 1910 1911 gpu2d: gpu@38008000 { 1912 compatible = "vivante,gc"; 1913 reg = <0x38008000 0x8000>; 1914 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1916 <&clk IMX8MP_CLK_GPU_ROOT>, 1917 <&clk IMX8MP_CLK_GPU_AHB>; 1918 clock-names = "core", "bus", "reg"; 1919 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1920 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1921 assigned-clock-rates = <800000000>; 1922 power-domains = <&pgc_gpu2d>; 1923 }; 1924 1925 vpu_g1: video-codec@38300000 { 1926 compatible = "nxp,imx8mm-vpu-g1"; 1927 reg = <0x38300000 0x10000>; 1928 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1929 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 1930 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 1931 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1932 assigned-clock-rates = <600000000>; 1933 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 1934 }; 1935 1936 vpu_g2: video-codec@38310000 { 1937 compatible = "nxp,imx8mq-vpu-g2"; 1938 reg = <0x38310000 0x10000>; 1939 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 1941 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 1942 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1943 assigned-clock-rates = <500000000>; 1944 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 1945 }; 1946 1947 vpumix_blk_ctrl: blk-ctrl@38330000 { 1948 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 1949 reg = <0x38330000 0x100>; 1950 #power-domain-cells = <1>; 1951 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1952 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 1953 power-domain-names = "bus", "g1", "g2", "vc8000e"; 1954 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 1955 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 1956 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 1957 clock-names = "g1", "g2", "vc8000e"; 1958 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 1959 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1960 assigned-clock-rates = <600000000>, <600000000>; 1961 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 1962 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 1963 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 1964 interconnect-names = "g1", "g2", "vc8000e"; 1965 }; 1966 1967 gic: interrupt-controller@38800000 { 1968 compatible = "arm,gic-v3"; 1969 reg = <0x38800000 0x10000>, 1970 <0x38880000 0xc0000>; 1971 #interrupt-cells = <3>; 1972 interrupt-controller; 1973 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1974 interrupt-parent = <&gic>; 1975 }; 1976 1977 edacmc: memory-controller@3d400000 { 1978 compatible = "snps,ddrc-3.80a"; 1979 reg = <0x3d400000 0x400000>; 1980 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1981 }; 1982 1983 ddr-pmu@3d800000 { 1984 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1985 reg = <0x3d800000 0x400000>; 1986 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1987 }; 1988 1989 usb3_phy0: usb-phy@381f0040 { 1990 compatible = "fsl,imx8mp-usb-phy"; 1991 reg = <0x381f0040 0x40>; 1992 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1993 clock-names = "phy"; 1994 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1995 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1996 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 1997 #phy-cells = <0>; 1998 status = "disabled"; 1999 }; 2000 2001 usb3_0: usb@32f10100 { 2002 compatible = "fsl,imx8mp-dwc3"; 2003 reg = <0x32f10100 0x8>, 2004 <0x381f0000 0x20>; 2005 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2006 <&clk IMX8MP_CLK_USB_SUSP>; 2007 clock-names = "hsio", "suspend"; 2008 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2009 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2010 #address-cells = <1>; 2011 #size-cells = <1>; 2012 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2013 ranges; 2014 status = "disabled"; 2015 2016 usb_dwc3_0: usb@38100000 { 2017 compatible = "snps,dwc3"; 2018 reg = <0x38100000 0x10000>; 2019 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2020 <&clk IMX8MP_CLK_USB_CORE_REF>, 2021 <&clk IMX8MP_CLK_USB_SUSP>; 2022 clock-names = "bus_early", "ref", "suspend"; 2023 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2024 phys = <&usb3_phy0>, <&usb3_phy0>; 2025 phy-names = "usb2-phy", "usb3-phy"; 2026 snps,gfladj-refclk-lpm-sel-quirk; 2027 }; 2028 2029 }; 2030 2031 usb3_phy1: usb-phy@382f0040 { 2032 compatible = "fsl,imx8mp-usb-phy"; 2033 reg = <0x382f0040 0x40>; 2034 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2035 clock-names = "phy"; 2036 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2037 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2038 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2039 #phy-cells = <0>; 2040 status = "disabled"; 2041 }; 2042 2043 usb3_1: usb@32f10108 { 2044 compatible = "fsl,imx8mp-dwc3"; 2045 reg = <0x32f10108 0x8>, 2046 <0x382f0000 0x20>; 2047 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2048 <&clk IMX8MP_CLK_USB_SUSP>; 2049 clock-names = "hsio", "suspend"; 2050 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2051 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2052 #address-cells = <1>; 2053 #size-cells = <1>; 2054 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2055 ranges; 2056 status = "disabled"; 2057 2058 usb_dwc3_1: usb@38200000 { 2059 compatible = "snps,dwc3"; 2060 reg = <0x38200000 0x10000>; 2061 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2062 <&clk IMX8MP_CLK_USB_CORE_REF>, 2063 <&clk IMX8MP_CLK_USB_SUSP>; 2064 clock-names = "bus_early", "ref", "suspend"; 2065 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2066 phys = <&usb3_phy1>, <&usb3_phy1>; 2067 phy-names = "usb2-phy", "usb3-phy"; 2068 snps,gfladj-refclk-lpm-sel-quirk; 2069 }; 2070 }; 2071 2072 dsp: dsp@3b6e8000 { 2073 compatible = "fsl,imx8mp-dsp"; 2074 reg = <0x3b6e8000 0x88000>; 2075 mbox-names = "txdb0", "txdb1", 2076 "rxdb0", "rxdb1"; 2077 mboxes = <&mu2 2 0>, <&mu2 2 1>, 2078 <&mu2 3 0>, <&mu2 3 1>; 2079 memory-region = <&dsp_reserved>; 2080 status = "disabled"; 2081 }; 2082 }; 2083}; 2084