1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 Wandboard, Org.
4 * Copyright 2017 NXP
5 *
6 * Author: Richard Hu <hakahu@gmail.com>
7 */
8
9/dts-v1/;
10
11#include "imx8mq.dtsi"
12
13/ {
14	model = "TechNexion PICO-PI-8M";
15	compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
16
17	chosen {
18		stdout-path = &uart1;
19	};
20
21	pmic_osc: clock-pmic {
22		compatible = "fixed-clock";
23		#clock-cells = <0>;
24		clock-frequency = <32768>;
25		clock-output-names = "pmic_osc";
26	};
27
28	reg_usb_otg_vbus: regulator-usb-otg-vbus {
29		pinctrl-names = "default";
30		pinctrl-0 = <&pinctrl_otg_vbus>;
31		compatible = "regulator-fixed";
32		regulator-name = "usb_otg_vbus";
33		regulator-min-microvolt = <5000000>;
34		regulator-max-microvolt = <5000000>;
35		gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
36	};
37};
38
39&fec1 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
42	phy-mode = "rgmii-id";
43	phy-handle = <&ethphy0>;
44	fsl,magic-packet;
45	status = "okay";
46
47	mdio {
48		#address-cells = <1>;
49		#size-cells = <0>;
50
51		ethphy0: ethernet-phy@1 {
52			compatible = "ethernet-phy-ieee802.3-c22";
53			reg = <1>;
54		};
55	};
56};
57
58&i2c1 {
59	clock-frequency = <100000>;
60	pinctrl-names = "default";
61	pinctrl-0 = <&pinctrl_i2c1>;
62	status = "okay";
63
64	pmic: pmic@4b {
65		reg = <0x4b>;
66		compatible = "rohm,bd71837";
67		pinctrl-names = "default";
68		pinctrl-0 = <&pinctrl_pmic>;
69		clocks = <&pmic_osc>;
70		clock-names = "osc";
71		clock-output-names = "pmic_clk";
72		interrupt-parent = <&gpio1>;
73		interrupts = <3 GPIO_ACTIVE_LOW>;
74		interrupt-names = "irq";
75
76		regulators {
77			buck1: BUCK1 {
78				regulator-name = "buck1";
79				regulator-min-microvolt = <700000>;
80				regulator-max-microvolt = <1300000>;
81				regulator-boot-on;
82				regulator-ramp-delay = <1250>;
83				rohm,dvs-run-voltage = <900000>;
84				rohm,dvs-idle-voltage = <850000>;
85				rohm,dvs-suspend-voltage = <800000>;
86			};
87
88			buck2: BUCK2 {
89				regulator-name = "buck2";
90				regulator-min-microvolt = <700000>;
91				regulator-max-microvolt = <1300000>;
92				regulator-boot-on;
93				regulator-ramp-delay = <1250>;
94				rohm,dvs-run-voltage = <1000000>;
95				rohm,dvs-idle-voltage = <900000>;
96			};
97
98			buck3: BUCK3 {
99				regulator-name = "buck3";
100				regulator-min-microvolt = <700000>;
101				regulator-max-microvolt = <1300000>;
102				regulator-boot-on;
103				rohm,dvs-run-voltage = <1000000>;
104			};
105
106			buck4: BUCK4 {
107				regulator-name = "buck4";
108				regulator-min-microvolt = <700000>;
109				regulator-max-microvolt = <1300000>;
110				regulator-boot-on;
111				rohm,dvs-run-voltage = <1000000>;
112			};
113
114			buck5: BUCK5 {
115				regulator-name = "buck5";
116				regulator-min-microvolt = <700000>;
117				regulator-max-microvolt = <1350000>;
118				regulator-boot-on;
119			};
120
121			buck6: BUCK6 {
122				regulator-name = "buck6";
123				regulator-min-microvolt = <3000000>;
124				regulator-max-microvolt = <3300000>;
125				regulator-boot-on;
126			};
127
128			buck7: BUCK7 {
129				regulator-name = "buck7";
130				regulator-min-microvolt = <1605000>;
131				regulator-max-microvolt = <1995000>;
132				regulator-boot-on;
133			};
134
135			buck8: BUCK8 {
136				regulator-name = "buck8";
137				regulator-min-microvolt = <800000>;
138				regulator-max-microvolt = <1400000>;
139				regulator-boot-on;
140			};
141
142			ldo1: LDO1 {
143				regulator-name = "ldo1";
144				regulator-min-microvolt = <3000000>;
145				regulator-max-microvolt = <3300000>;
146				regulator-boot-on;
147				regulator-always-on;
148			};
149
150			ldo2: LDO2 {
151				regulator-name = "ldo2";
152				regulator-min-microvolt = <900000>;
153				regulator-max-microvolt = <900000>;
154				regulator-boot-on;
155				regulator-always-on;
156			};
157
158			ldo3: LDO3 {
159				regulator-name = "ldo3";
160				regulator-min-microvolt = <1800000>;
161				regulator-max-microvolt = <3300000>;
162				regulator-boot-on;
163			};
164
165			ldo4: LDO4 {
166				regulator-name = "ldo4";
167				regulator-min-microvolt = <900000>;
168				regulator-max-microvolt = <1800000>;
169				regulator-boot-on;
170			};
171
172			ldo5: LDO5 {
173				regulator-name = "ldo5";
174				regulator-min-microvolt = <1800000>;
175				regulator-max-microvolt = <3300000>;
176				regulator-boot-on;
177			};
178
179			ldo6: LDO6 {
180				regulator-name = "ldo6";
181				regulator-min-microvolt = <900000>;
182				regulator-max-microvolt = <1800000>;
183				regulator-boot-on;
184			};
185
186			ldo7: LDO7 {
187				regulator-name = "ldo7";
188				regulator-min-microvolt = <1800000>;
189				regulator-max-microvolt = <3300000>;
190				regulator-boot-on;
191			};
192		};
193	};
194};
195
196&i2c2 {
197	clock-frequency = <100000>;
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_i2c2>;
200	status = "okay";
201};
202
203&uart1 { /* console */
204	pinctrl-names = "default";
205	pinctrl-0 = <&pinctrl_uart1>;
206	status = "okay";
207};
208
209&usdhc1 {
210	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
211	assigned-clock-rates = <400000000>;
212	pinctrl-names = "default", "state_100mhz", "state_200mhz";
213	pinctrl-0 = <&pinctrl_usdhc1>;
214	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
215	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
216	bus-width = <8>;
217	non-removable;
218	status = "okay";
219};
220
221&usdhc2 {
222	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
223	assigned-clock-rates = <200000000>;
224	pinctrl-names = "default", "state_100mhz", "state_200mhz";
225	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
226	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
227	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
228	bus-width = <4>;
229	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
230	status = "okay";
231};
232
233&usb3_phy0 {
234	status = "okay";
235};
236
237&usb3_phy1 {
238	status = "okay";
239};
240
241&usb_dwc3_1 {
242	dr_mode = "host";
243	status = "okay";
244};
245
246&wdog1 {
247	pinctrl-names = "default";
248	pinctrl-0 = <&pinctrl_wdog>;
249	fsl,ext-reset-output;
250	status = "okay";
251};
252
253&iomuxc {
254	pinctrl_enet_3v3: enet3v3grp {
255		fsl,pins = <
256			MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x19
257		>;
258	};
259
260	pinctrl_fec1: fec1grp {
261		fsl,pins = <
262			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
263			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
264			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
265			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
266			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
267			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
268			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
269			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
270			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
271			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
272			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
273			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
274			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
275			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
276			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
277		>;
278	};
279
280	pinctrl_i2c1: i2c1grp {
281		fsl,pins = <
282			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
283			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
284		>;
285	};
286
287	pinctrl_i2c2: i2c2grp {
288		fsl,pins = <
289			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
290			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
291		>;
292	};
293
294	pinctrl_otg_vbus: otgvbusgrp {
295		fsl,pins = <
296			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x19   /* USB OTG VBUS Enable */
297		>;
298	};
299
300	pinctrl_pmic: pmicirq {
301		fsl,pins = <
302			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
303		>;
304	};
305
306	pinctrl_uart1: uart1grp {
307		fsl,pins = <
308			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
309			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
310		>;
311	};
312
313	pinctrl_uart2: uart2grp {
314		fsl,pins = <
315			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
316			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
317			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
318			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
319		>;
320	};
321
322	pinctrl_usdhc1: usdhc1grp {
323		fsl,pins = <
324			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
325			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
326			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
327			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
328			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
329			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
330			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
331			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
332			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
333			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
334			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
335		>;
336	};
337
338	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
339		fsl,pins = <
340			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
341			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
342			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
343			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
344			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
345			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
346			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
347			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
348			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
349			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
350			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
351		>;
352	};
353
354	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
355		fsl,pins = <
356			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
357			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
358			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
359			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
360			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
361			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
362			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
363			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
364			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
365			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
366			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
367		>;
368	};
369
370	pinctrl_usdhc2_gpio: usdhc2grpgpio {
371		fsl,pins = <
372			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
373		>;
374	};
375
376	pinctrl_usdhc2: usdhc2grp {
377		fsl,pins = <
378			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
379			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
380			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
381			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
382			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
383			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
384			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
385		>;
386	};
387
388	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
389		fsl,pins = <
390			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
391			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
392			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
393			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
394			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
395			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
396			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
397		>;
398	};
399
400	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
401		fsl,pins = <
402			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
403			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
404			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
405			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
406			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
407			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
408			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
409		>;
410	};
411
412	pinctrl_wdog: wdoggrp {
413		fsl,pins = <
414			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
415		>;
416	};
417};
418