1// SPDX-License-Identifier:     GPL-2.0
2/*
3 * Copyright (C) 2019, Intel Corporation
4 */
5#include "socfpga_agilex.dtsi"
6
7/ {
8	model = "SoCFPGA Agilex SoCDK";
9	compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
10
11	aliases {
12		serial0 = &uart0;
13		ethernet0 = &gmac0;
14		ethernet1 = &gmac1;
15		ethernet2 = &gmac2;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	leds {
23		compatible = "gpio-leds";
24		led0 {
25			label = "hps_led0";
26			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
27		};
28
29		led1 {
30			label = "hps_led1";
31			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
32		};
33
34		led2 {
35			label = "hps_led2";
36			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
37		};
38	};
39
40	memory@80000000 {
41		device_type = "memory";
42		/* We expect the bootloader to fill in the reg */
43		reg = <0 0x80000000 0 0>;
44	};
45};
46
47&gpio1 {
48	status = "okay";
49};
50
51&gmac0 {
52	status = "okay";
53	phy-mode = "rgmii";
54	phy-handle = <&phy0>;
55
56	max-frame-size = <9000>;
57
58	mdio0 {
59		#address-cells = <1>;
60		#size-cells = <0>;
61		compatible = "snps,dwmac-mdio";
62		phy0: ethernet-phy@0 {
63			reg = <4>;
64
65			txd0-skew-ps = <0>; /* -420ps */
66			txd1-skew-ps = <0>; /* -420ps */
67			txd2-skew-ps = <0>; /* -420ps */
68			txd3-skew-ps = <0>; /* -420ps */
69			rxd0-skew-ps = <420>; /* 0ps */
70			rxd1-skew-ps = <420>; /* 0ps */
71			rxd2-skew-ps = <420>; /* 0ps */
72			rxd3-skew-ps = <420>; /* 0ps */
73			txen-skew-ps = <0>; /* -420ps */
74			txc-skew-ps = <900>; /* 0ps */
75			rxdv-skew-ps = <420>; /* 0ps */
76			rxc-skew-ps = <1680>; /* 780ps */
77		};
78	};
79};
80
81&mmc {
82	status = "okay";
83	cap-sd-highspeed;
84	broken-cd;
85	bus-width = <4>;
86	clk-phase-sd-hs = <0>, <135>;
87};
88
89&osc1 {
90	clock-frequency = <25000000>;
91};
92
93&uart0 {
94	status = "okay";
95};
96
97&usb0 {
98	status = "okay";
99	disable-over-current;
100};
101
102&watchdog0 {
103	status = "okay";
104};
105
106&qspi {
107	status = "okay";
108	flash@0 {
109		#address-cells = <1>;
110		#size-cells = <1>;
111		compatible = "micron,mt25qu02g", "jedec,spi-nor";
112		reg = <0>;
113		spi-max-frequency = <100000000>;
114
115		m25p,fast-read;
116		cdns,read-delay = <2>;
117		cdns,tshsl-ns = <50>;
118		cdns,tsd2d-ns = <50>;
119		cdns,tchsh-ns = <4>;
120		cdns,tslch-ns = <4>;
121
122		partitions {
123			compatible = "fixed-partitions";
124			#address-cells = <1>;
125			#size-cells = <1>;
126
127			qspi_boot: partition@0 {
128				label = "Boot and fpga data";
129				reg = <0x0 0x04200000>;
130			};
131
132			root: partition@4200000 {
133				label = "Root Filesystem - UBIFS";
134				reg = <0x04200000 0x0BE00000>;
135			};
136		};
137	};
138};
139