1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
6 */
7
8#include "armada-8040.dtsi"
9
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13	model = "Marvell 8040 MACCHIATOBin";
14	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15			"marvell,armada-ap806-quad", "marvell,armada-ap806";
16
17	chosen {
18		stdout-path = "serial0:115200n8";
19	};
20
21	memory@0 {
22		device_type = "memory";
23		reg = <0x0 0x0 0x0 0x80000000>;
24	};
25
26	aliases {
27		ethernet0 = &cp0_eth0;
28		ethernet1 = &cp1_eth0;
29		ethernet2 = &cp1_eth1;
30		ethernet3 = &cp1_eth2;
31	};
32
33	/* Regulator labels correspond with schematics */
34	v_3_3: regulator-3-3v {
35		compatible = "regulator-fixed";
36		regulator-name = "v_3_3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		regulator-always-on;
40		status = "okay";
41	};
42
43	v_vddo_h: regulator-1-8v {
44		compatible = "regulator-fixed";
45		regulator-name = "v_vddo_h";
46		regulator-min-microvolt = <1800000>;
47		regulator-max-microvolt = <1800000>;
48		regulator-always-on;
49		status = "okay";
50	};
51
52	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
53		compatible = "regulator-fixed";
54		enable-active-high;
55		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
56		pinctrl-names = "default";
57		pinctrl-0 = <&cp0_xhci_vbus_pins>;
58		regulator-name = "v_5v0_usb3_hst_vbus";
59		regulator-min-microvolt = <5000000>;
60		regulator-max-microvolt = <5000000>;
61		status = "okay";
62	};
63
64	sfp_eth0: sfp-eth0 {
65		/* CON15,16 - CPM lane 4 */
66		compatible = "sff,sfp";
67		i2c-bus = <&sfpp0_i2c>;
68		los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
69		mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
70		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
71		tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
72		pinctrl-names = "default";
73		pinctrl-0 = <&cp1_sfpp0_pins>;
74	};
75
76	sfp_eth1: sfp-eth1 {
77		/* CON17,18 - CPS lane 4 */
78		compatible = "sff,sfp";
79		i2c-bus = <&sfpp1_i2c>;
80		los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
81		mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
82		tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
83		tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
84		pinctrl-names = "default";
85		pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
86	};
87
88	sfp_eth3: sfp-eth3 {
89		/* CON13,14 - CPS lane 5 */
90		compatible = "sff,sfp";
91		i2c-bus = <&sfp_1g_i2c>;
92		los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
93		mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
94		tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
95		tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
96		pinctrl-names = "default";
97		pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
98	};
99};
100
101&uart0 {
102	status = "okay";
103	pinctrl-0 = <&uart0_pins>;
104	pinctrl-names = "default";
105};
106
107&ap_sdhci0 {
108	bus-width = <8>;
109	/*
110	 * Not stable in HS modes - phy needs "more calibration", so add
111	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
112	 */
113	marvell,xenon-phy-slow-mode;
114	no-1-8-v;
115	no-sd;
116	no-sdio;
117	non-removable;
118	status = "okay";
119	vqmmc-supply = <&v_vddo_h>;
120};
121
122&cp0_i2c0 {
123	clock-frequency = <100000>;
124	pinctrl-names = "default";
125	pinctrl-0 = <&cp0_i2c0_pins>;
126	status = "okay";
127};
128
129&cp0_i2c1 {
130	clock-frequency = <100000>;
131	pinctrl-names = "default";
132	pinctrl-0 = <&cp0_i2c1_pins>;
133	status = "okay";
134
135	i2c-switch@70 {
136		compatible = "nxp,pca9548";
137		#address-cells = <1>;
138		#size-cells = <0>;
139		reg = <0x70>;
140
141		sfpp0_i2c: i2c@0 {
142			#address-cells = <1>;
143			#size-cells = <0>;
144			reg = <0>;
145		};
146		sfpp1_i2c: i2c@1 {
147			#address-cells = <1>;
148			#size-cells = <0>;
149			reg = <1>;
150		};
151		sfp_1g_i2c: i2c@2 {
152			#address-cells = <1>;
153			#size-cells = <0>;
154			reg = <2>;
155		};
156	};
157};
158
159/* J25 UART header */
160&cp0_uart1 {
161	pinctrl-names = "default";
162	pinctrl-0 = <&cp0_uart1_pins>;
163	status = "okay";
164};
165
166&cp0_mdio {
167	pinctrl-names = "default";
168	pinctrl-0 = <&cp0_ge_mdio_pins>;
169	status = "okay";
170
171	ge_phy: ethernet-phy@0 {
172		reg = <0>;
173	};
174};
175
176&cp0_pcie0 {
177	pinctrl-names = "default";
178	pinctrl-0 = <&cp0_pcie_pins>;
179	num-lanes = <4>;
180	num-viewport = <8>;
181	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
182	ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
183		  0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
184	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
185	       <&cp0_comphy2 0>, <&cp0_comphy3 0>;
186	phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
187		    "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
188	status = "okay";
189};
190
191&cp0_pinctrl {
192	cp0_ge_mdio_pins: ge-mdio-pins {
193		marvell,pins = "mpp32", "mpp34";
194		marvell,function = "ge";
195	};
196	cp0_i2c1_pins: i2c1-pins {
197		marvell,pins = "mpp35", "mpp36";
198		marvell,function = "i2c1";
199	};
200	cp0_i2c0_pins: i2c0-pins {
201		marvell,pins = "mpp37", "mpp38";
202		marvell,function = "i2c0";
203	};
204	cp0_uart1_pins: uart1-pins {
205		marvell,pins = "mpp40", "mpp41";
206		marvell,function = "uart1";
207	};
208	cp0_xhci_vbus_pins: xhci0-vbus-pins {
209		marvell,pins = "mpp47";
210		marvell,function = "gpio";
211	};
212	cp0_sfp_1g_pins: sfp-1g-pins {
213		marvell,pins = "mpp51", "mpp53", "mpp54";
214		marvell,function = "gpio";
215	};
216	cp0_pcie_pins: pcie-pins {
217		marvell,pins = "mpp52";
218		marvell,function = "gpio";
219	};
220	cp0_sdhci_pins: sdhci-pins {
221		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
222			       "mpp60", "mpp61";
223		marvell,function = "sdio";
224	};
225	cp0_sfpp1_pins: sfpp1-pins {
226		marvell,pins = "mpp62";
227		marvell,function = "gpio";
228	};
229};
230
231&cp0_ethernet {
232	status = "okay";
233};
234
235&cp0_eth0 {
236	/* Generic PHY, providing serdes lanes */
237	phys = <&cp0_comphy4 0>;
238};
239
240&cp0_sata0 {
241	status = "okay";
242
243	/* CPM Lane 5 - U29 */
244	sata-port@1 {
245		phys = <&cp0_comphy5 1>;
246		phy-names = "cp0-sata0-1-phy";
247	};
248};
249
250&cp0_sdhci0 {
251	/* U6 */
252	broken-cd;
253	bus-width = <4>;
254	pinctrl-names = "default";
255	pinctrl-0 = <&cp0_sdhci_pins>;
256	status = "okay";
257	vqmmc-supply = <&v_3_3>;
258};
259
260&cp0_usb3_0 {
261	/* J38? - USB2.0 only */
262	status = "okay";
263};
264
265&cp0_usb3_1 {
266	/* J38? - USB2.0 only */
267	status = "okay";
268};
269
270&cp1_ethernet {
271	status = "okay";
272};
273
274&cp1_eth0 {
275	/* Generic PHY, providing serdes lanes */
276	phys = <&cp1_comphy4 0>;
277};
278
279&cp1_eth1 {
280	/* CPS Lane 0 - J5 (Gigabit RJ45) */
281	status = "okay";
282	/* Network PHY */
283	phy = <&ge_phy>;
284	phy-mode = "sgmii";
285	/* Generic PHY, providing serdes lanes */
286	phys = <&cp1_comphy0 1>;
287};
288
289&cp1_eth2 {
290	/* CPS Lane 5 */
291	status = "okay";
292	/* Network PHY */
293	phy-mode = "2500base-x";
294	managed = "in-band-status";
295	/* Generic PHY, providing serdes lanes */
296	phys = <&cp1_comphy5 2>;
297	sfp = <&sfp_eth3>;
298};
299
300&cp1_pinctrl {
301	cp1_sfpp1_pins: sfpp1-pins {
302		marvell,pins = "mpp8", "mpp10", "mpp11";
303		marvell,function = "gpio";
304	};
305	cp1_spi1_pins: spi1-pins {
306		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
307		marvell,function = "spi1";
308	};
309	cp1_uart0_pins: uart0-pins {
310		marvell,pins = "mpp6", "mpp7";
311		marvell,function = "uart0";
312	};
313	cp1_sfp_1g_pins: sfp-1g-pins {
314		marvell,pins = "mpp24";
315		marvell,function = "gpio";
316	};
317	cp1_sfpp0_pins: sfpp0-pins {
318		marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
319		marvell,function = "gpio";
320	};
321};
322
323/* J27 UART header */
324&cp1_uart0 {
325	pinctrl-names = "default";
326	pinctrl-0 = <&cp1_uart0_pins>;
327	status = "okay";
328};
329
330&cp1_sata0 {
331	status = "okay";
332
333	/* CPS Lane 1 - U32 */
334	sata-port@0 {
335		phys = <&cp1_comphy1 0>;
336		phy-names = "cp1-sata0-0-phy";
337	};
338
339	/* CPS Lane 3 - U31 */
340	sata-port@1 {
341		phys = <&cp1_comphy3 1>;
342		phy-names = "cp1-sata0-1-phy";
343	};
344};
345
346&cp1_spi1 {
347	pinctrl-names = "default";
348	pinctrl-0 = <&cp1_spi1_pins>;
349	status = "okay";
350
351	spi-flash@0 {
352		compatible = "st,w25q32";
353		spi-max-frequency = <50000000>;
354		reg = <0>;
355	};
356};
357
358&cp1_comphy2 {
359	cp1_usbh0_con: connector {
360		compatible = "usb-a-connector";
361		phy-supply = <&v_5v0_usb3_hst_vbus>;
362	};
363};
364
365&cp1_usb3_0 {
366	/* CPS Lane 2 - CON7 */
367	phys = <&cp1_comphy2 0>;
368	phy-names = "cp1-usb3h0-comphy";
369	status = "okay";
370};
371