1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: YT Shen <yt.shen@mediatek.com> 4 * 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 */ 7 8#include <dt-bindings/clock/mt2712-clk.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/memory/mt2712-larb-port.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/power/mt2712-power.h> 14#include "mt2712-pinfunc.h" 15 16/ { 17 compatible = "mediatek,mt2712"; 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cluster0_opp: opp_table0 { 23 compatible = "operating-points-v2"; 24 opp-shared; 25 opp00 { 26 opp-hz = /bits/ 64 <598000000>; 27 opp-microvolt = <1000000>; 28 }; 29 opp01 { 30 opp-hz = /bits/ 64 <702000000>; 31 opp-microvolt = <1000000>; 32 }; 33 opp02 { 34 opp-hz = /bits/ 64 <793000000>; 35 opp-microvolt = <1000000>; 36 }; 37 }; 38 39 cluster1_opp: opp_table1 { 40 compatible = "operating-points-v2"; 41 opp-shared; 42 opp00 { 43 opp-hz = /bits/ 64 <598000000>; 44 opp-microvolt = <1000000>; 45 }; 46 opp01 { 47 opp-hz = /bits/ 64 <702000000>; 48 opp-microvolt = <1000000>; 49 }; 50 opp02 { 51 opp-hz = /bits/ 64 <793000000>; 52 opp-microvolt = <1000000>; 53 }; 54 opp03 { 55 opp-hz = /bits/ 64 <897000000>; 56 opp-microvolt = <1000000>; 57 }; 58 opp04 { 59 opp-hz = /bits/ 64 <1001000000>; 60 opp-microvolt = <1000000>; 61 }; 62 }; 63 64 cpus { 65 #address-cells = <1>; 66 #size-cells = <0>; 67 68 cpu-map { 69 cluster0 { 70 core0 { 71 cpu = <&cpu0>; 72 }; 73 core1 { 74 cpu = <&cpu1>; 75 }; 76 }; 77 78 cluster1 { 79 core0 { 80 cpu = <&cpu2>; 81 }; 82 }; 83 }; 84 85 cpu0: cpu@0 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a35"; 88 reg = <0x000>; 89 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 90 <&topckgen CLK_TOP_F_MP0_PLL1>; 91 clock-names = "cpu", "intermediate"; 92 proc-supply = <&cpus_fixed_vproc0>; 93 operating-points-v2 = <&cluster0_opp>; 94 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 95 }; 96 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a35"; 100 reg = <0x001>; 101 enable-method = "psci"; 102 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 103 <&topckgen CLK_TOP_F_MP0_PLL1>; 104 clock-names = "cpu", "intermediate"; 105 proc-supply = <&cpus_fixed_vproc0>; 106 operating-points-v2 = <&cluster0_opp>; 107 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 108 }; 109 110 cpu2: cpu@200 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a72"; 113 reg = <0x200>; 114 enable-method = "psci"; 115 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 116 <&topckgen CLK_TOP_F_BIG_PLL1>; 117 clock-names = "cpu", "intermediate"; 118 proc-supply = <&cpus_fixed_vproc1>; 119 operating-points-v2 = <&cluster1_opp>; 120 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 121 }; 122 123 idle-states { 124 entry-method = "psci"; 125 126 CPU_SLEEP_0: cpu-sleep-0 { 127 compatible = "arm,idle-state"; 128 local-timer-stop; 129 entry-latency-us = <100>; 130 exit-latency-us = <80>; 131 min-residency-us = <2000>; 132 arm,psci-suspend-param = <0x0010000>; 133 }; 134 135 CLUSTER_SLEEP_0: cluster-sleep-0 { 136 compatible = "arm,idle-state"; 137 local-timer-stop; 138 entry-latency-us = <350>; 139 exit-latency-us = <80>; 140 min-residency-us = <3000>; 141 arm,psci-suspend-param = <0x1010000>; 142 }; 143 }; 144 }; 145 146 psci { 147 compatible = "arm,psci-0.2"; 148 method = "smc"; 149 }; 150 151 baud_clk: dummy26m { 152 compatible = "fixed-clock"; 153 clock-frequency = <26000000>; 154 #clock-cells = <0>; 155 }; 156 157 sys_clk: dummyclk { 158 compatible = "fixed-clock"; 159 clock-frequency = <26000000>; 160 #clock-cells = <0>; 161 }; 162 163 clk26m: oscillator@0 { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <26000000>; 167 clock-output-names = "clk26m"; 168 }; 169 170 clk32k: oscillator@1 { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <32768>; 174 clock-output-names = "clk32k"; 175 }; 176 177 clkfpc: oscillator@2 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <50000000>; 181 clock-output-names = "clkfpc"; 182 }; 183 184 clkaud_ext_i_0: oscillator@3 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <6500000>; 188 clock-output-names = "clkaud_ext_i_0"; 189 }; 190 191 clkaud_ext_i_1: oscillator@4 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <196608000>; 195 clock-output-names = "clkaud_ext_i_1"; 196 }; 197 198 clkaud_ext_i_2: oscillator@5 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <180633600>; 202 clock-output-names = "clkaud_ext_i_2"; 203 }; 204 205 clki2si0_mck_i: oscillator@6 { 206 compatible = "fixed-clock"; 207 #clock-cells = <0>; 208 clock-frequency = <30000000>; 209 clock-output-names = "clki2si0_mck_i"; 210 }; 211 212 clki2si1_mck_i: oscillator@7 { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <30000000>; 216 clock-output-names = "clki2si1_mck_i"; 217 }; 218 219 clki2si2_mck_i: oscillator@8 { 220 compatible = "fixed-clock"; 221 #clock-cells = <0>; 222 clock-frequency = <30000000>; 223 clock-output-names = "clki2si2_mck_i"; 224 }; 225 226 clktdmin_mclk_i: oscillator@9 { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 clock-frequency = <30000000>; 230 clock-output-names = "clktdmin_mclk_i"; 231 }; 232 233 timer { 234 compatible = "arm,armv8-timer"; 235 interrupt-parent = <&gic>; 236 interrupts = <GIC_PPI 13 237 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 239 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 241 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 243 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 244 }; 245 246 topckgen: syscon@10000000 { 247 compatible = "mediatek,mt2712-topckgen", "syscon"; 248 reg = <0 0x10000000 0 0x1000>; 249 #clock-cells = <1>; 250 }; 251 252 infracfg: syscon@10001000 { 253 compatible = "mediatek,mt2712-infracfg", "syscon"; 254 reg = <0 0x10001000 0 0x1000>; 255 #clock-cells = <1>; 256 }; 257 258 pericfg: syscon@10003000 { 259 compatible = "mediatek,mt2712-pericfg", "syscon"; 260 reg = <0 0x10003000 0 0x1000>; 261 #clock-cells = <1>; 262 }; 263 264 syscfg_pctl_a: syscfg_pctl_a@10005000 { 265 compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 266 reg = <0 0x10005000 0 0x1000>; 267 }; 268 269 pio: pinctrl@10005000 { 270 compatible = "mediatek,mt2712-pinctrl"; 271 reg = <0 0x1000b000 0 0x1000>; 272 mediatek,pctl-regmap = <&syscfg_pctl_a>; 273 pins-are-numbered; 274 gpio-controller; 275 #gpio-cells = <2>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 279 }; 280 281 scpsys: scpsys@10006000 { 282 compatible = "mediatek,mt2712-scpsys", "syscon"; 283 #power-domain-cells = <1>; 284 reg = <0 0x10006000 0 0x1000>; 285 clocks = <&topckgen CLK_TOP_MM_SEL>, 286 <&topckgen CLK_TOP_MFG_SEL>, 287 <&topckgen CLK_TOP_VENC_SEL>, 288 <&topckgen CLK_TOP_JPGDEC_SEL>, 289 <&topckgen CLK_TOP_A1SYS_HP_SEL>, 290 <&topckgen CLK_TOP_VDEC_SEL>; 291 clock-names = "mm", "mfg", "venc", 292 "jpgdec", "audio", "vdec"; 293 infracfg = <&infracfg>; 294 }; 295 296 uart5: serial@1000f000 { 297 compatible = "mediatek,mt2712-uart", 298 "mediatek,mt6577-uart"; 299 reg = <0 0x1000f000 0 0x400>; 300 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 301 clocks = <&baud_clk>, <&sys_clk>; 302 clock-names = "baud", "bus"; 303 status = "disabled"; 304 }; 305 306 spis1: spi@10013000 { 307 compatible = "mediatek,mt2712-spi-slave"; 308 reg = <0 0x10013000 0 0x100>; 309 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 310 clocks = <&infracfg CLK_INFRA_AO_SPI1>; 311 clock-names = "spi"; 312 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 313 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 314 status = "disabled"; 315 }; 316 317 iommu0: iommu@10205000 { 318 compatible = "mediatek,mt2712-m4u"; 319 reg = <0 0x10205000 0 0x1000>; 320 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 321 clocks = <&infracfg CLK_INFRA_M4U>; 322 clock-names = "bclk"; 323 mediatek,larbs = <&larb0 &larb1 &larb2 324 &larb3 &larb6>; 325 #iommu-cells = <1>; 326 }; 327 328 apmixedsys: syscon@10209000 { 329 compatible = "mediatek,mt2712-apmixedsys", "syscon"; 330 reg = <0 0x10209000 0 0x1000>; 331 #clock-cells = <1>; 332 }; 333 334 iommu1: iommu@1020a000 { 335 compatible = "mediatek,mt2712-m4u"; 336 reg = <0 0x1020a000 0 0x1000>; 337 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 338 clocks = <&infracfg CLK_INFRA_M4U>; 339 clock-names = "bclk"; 340 mediatek,larbs = <&larb4 &larb5 &larb7>; 341 #iommu-cells = <1>; 342 }; 343 344 mcucfg: syscon@10220000 { 345 compatible = "mediatek,mt2712-mcucfg", "syscon"; 346 reg = <0 0x10220000 0 0x1000>; 347 #clock-cells = <1>; 348 }; 349 350 sysirq: interrupt-controller@10220a80 { 351 compatible = "mediatek,mt2712-sysirq", 352 "mediatek,mt6577-sysirq"; 353 interrupt-controller; 354 #interrupt-cells = <3>; 355 interrupt-parent = <&gic>; 356 reg = <0 0x10220a80 0 0x40>; 357 }; 358 359 gic: interrupt-controller@10510000 { 360 compatible = "arm,gic-400"; 361 #interrupt-cells = <3>; 362 interrupt-parent = <&gic>; 363 interrupt-controller; 364 reg = <0 0x10510000 0 0x10000>, 365 <0 0x10520000 0 0x20000>, 366 <0 0x10540000 0 0x20000>, 367 <0 0x10560000 0 0x20000>; 368 interrupts = <GIC_PPI 9 369 (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 370 }; 371 372 auxadc: adc@11001000 { 373 compatible = "mediatek,mt2712-auxadc"; 374 reg = <0 0x11001000 0 0x1000>; 375 clocks = <&pericfg CLK_PERI_AUXADC>; 376 clock-names = "main"; 377 #io-channel-cells = <1>; 378 status = "disabled"; 379 }; 380 381 uart0: serial@11002000 { 382 compatible = "mediatek,mt2712-uart", 383 "mediatek,mt6577-uart"; 384 reg = <0 0x11002000 0 0x400>; 385 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 386 clocks = <&baud_clk>, <&sys_clk>; 387 clock-names = "baud", "bus"; 388 status = "disabled"; 389 }; 390 391 uart1: serial@11003000 { 392 compatible = "mediatek,mt2712-uart", 393 "mediatek,mt6577-uart"; 394 reg = <0 0x11003000 0 0x400>; 395 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 396 clocks = <&baud_clk>, <&sys_clk>; 397 clock-names = "baud", "bus"; 398 status = "disabled"; 399 }; 400 401 uart2: serial@11004000 { 402 compatible = "mediatek,mt2712-uart", 403 "mediatek,mt6577-uart"; 404 reg = <0 0x11004000 0 0x400>; 405 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 406 clocks = <&baud_clk>, <&sys_clk>; 407 clock-names = "baud", "bus"; 408 status = "disabled"; 409 }; 410 411 uart3: serial@11005000 { 412 compatible = "mediatek,mt2712-uart", 413 "mediatek,mt6577-uart"; 414 reg = <0 0x11005000 0 0x400>; 415 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 416 clocks = <&baud_clk>, <&sys_clk>; 417 clock-names = "baud", "bus"; 418 status = "disabled"; 419 }; 420 421 pwm: pwm@11006000 { 422 compatible = "mediatek,mt2712-pwm"; 423 reg = <0 0x11006000 0 0x1000>; 424 #pwm-cells = <2>; 425 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 426 clocks = <&topckgen CLK_TOP_PWM_SEL>, 427 <&pericfg CLK_PERI_PWM>, 428 <&pericfg CLK_PERI_PWM0>, 429 <&pericfg CLK_PERI_PWM1>, 430 <&pericfg CLK_PERI_PWM2>, 431 <&pericfg CLK_PERI_PWM3>, 432 <&pericfg CLK_PERI_PWM4>, 433 <&pericfg CLK_PERI_PWM5>, 434 <&pericfg CLK_PERI_PWM6>, 435 <&pericfg CLK_PERI_PWM7>; 436 clock-names = "top", 437 "main", 438 "pwm1", 439 "pwm2", 440 "pwm3", 441 "pwm4", 442 "pwm5", 443 "pwm6", 444 "pwm7", 445 "pwm8"; 446 status = "disabled"; 447 }; 448 449 i2c0: i2c@11007000 { 450 compatible = "mediatek,mt2712-i2c"; 451 reg = <0 0x11007000 0 0x90>, 452 <0 0x11000180 0 0x80>; 453 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 454 clock-div = <4>; 455 clocks = <&pericfg CLK_PERI_I2C0>, 456 <&pericfg CLK_PERI_AP_DMA>; 457 clock-names = "main", 458 "dma"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 i2c1: i2c@11008000 { 465 compatible = "mediatek,mt2712-i2c"; 466 reg = <0 0x11008000 0 0x90>, 467 <0 0x11000200 0 0x80>; 468 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 469 clock-div = <4>; 470 clocks = <&pericfg CLK_PERI_I2C1>, 471 <&pericfg CLK_PERI_AP_DMA>; 472 clock-names = "main", 473 "dma"; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 479 i2c2: i2c@11009000 { 480 compatible = "mediatek,mt2712-i2c"; 481 reg = <0 0x11009000 0 0x90>, 482 <0 0x11000280 0 0x80>; 483 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 484 clock-div = <4>; 485 clocks = <&pericfg CLK_PERI_I2C2>, 486 <&pericfg CLK_PERI_AP_DMA>; 487 clock-names = "main", 488 "dma"; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 status = "disabled"; 492 }; 493 494 spi0: spi@1100a000 { 495 compatible = "mediatek,mt2712-spi"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <0 0x1100a000 0 0x100>; 499 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 500 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 501 <&topckgen CLK_TOP_SPI_SEL>, 502 <&pericfg CLK_PERI_SPI0>; 503 clock-names = "parent-clk", "sel-clk", "spi-clk"; 504 status = "disabled"; 505 }; 506 507 nandc: nfi@1100e000 { 508 compatible = "mediatek,mt2712-nfc"; 509 reg = <0 0x1100e000 0 0x1000>; 510 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 511 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; 512 clock-names = "nfi_clk", "pad_clk"; 513 ecc-engine = <&bch>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 bch: ecc@1100f000 { 520 compatible = "mediatek,mt2712-ecc"; 521 reg = <0 0x1100f000 0 0x1000>; 522 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 523 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; 524 clock-names = "nfiecc_clk"; 525 status = "disabled"; 526 }; 527 528 i2c3: i2c@11010000 { 529 compatible = "mediatek,mt2712-i2c"; 530 reg = <0 0x11010000 0 0x90>, 531 <0 0x11000300 0 0x80>; 532 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 533 clock-div = <4>; 534 clocks = <&pericfg CLK_PERI_I2C3>, 535 <&pericfg CLK_PERI_AP_DMA>; 536 clock-names = "main", 537 "dma"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 i2c4: i2c@11011000 { 544 compatible = "mediatek,mt2712-i2c"; 545 reg = <0 0x11011000 0 0x90>, 546 <0 0x11000380 0 0x80>; 547 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 548 clock-div = <4>; 549 clocks = <&pericfg CLK_PERI_I2C4>, 550 <&pericfg CLK_PERI_AP_DMA>; 551 clock-names = "main", 552 "dma"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 558 i2c5: i2c@11013000 { 559 compatible = "mediatek,mt2712-i2c"; 560 reg = <0 0x11013000 0 0x90>, 561 <0 0x11000100 0 0x80>; 562 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 563 clock-div = <4>; 564 clocks = <&pericfg CLK_PERI_I2C5>, 565 <&pericfg CLK_PERI_AP_DMA>; 566 clock-names = "main", 567 "dma"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 spi2: spi@11015000 { 574 compatible = "mediatek,mt2712-spi"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <0 0x11015000 0 0x100>; 578 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>; 579 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 580 <&topckgen CLK_TOP_SPI_SEL>, 581 <&pericfg CLK_PERI_SPI2>; 582 clock-names = "parent-clk", "sel-clk", "spi-clk"; 583 status = "disabled"; 584 }; 585 586 spi3: spi@11016000 { 587 compatible = "mediatek,mt2712-spi"; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 reg = <0 0x11016000 0 0x100>; 591 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>; 592 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 593 <&topckgen CLK_TOP_SPI_SEL>, 594 <&pericfg CLK_PERI_SPI3>; 595 clock-names = "parent-clk", "sel-clk", "spi-clk"; 596 status = "disabled"; 597 }; 598 599 spi4: spi@10012000 { 600 compatible = "mediatek,mt2712-spi"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <0 0x10012000 0 0x100>; 604 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 605 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 606 <&topckgen CLK_TOP_SPI_SEL>, 607 <&infracfg CLK_INFRA_AO_SPI0>; 608 clock-names = "parent-clk", "sel-clk", "spi-clk"; 609 status = "disabled"; 610 }; 611 612 spi5: spi@11018000 { 613 compatible = "mediatek,mt2712-spi"; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 reg = <0 0x11018000 0 0x100>; 617 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>; 618 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 619 <&topckgen CLK_TOP_SPI_SEL>, 620 <&pericfg CLK_PERI_SPI5>; 621 clock-names = "parent-clk", "sel-clk", "spi-clk"; 622 status = "disabled"; 623 }; 624 625 uart4: serial@11019000 { 626 compatible = "mediatek,mt2712-uart", 627 "mediatek,mt6577-uart"; 628 reg = <0 0x11019000 0 0x400>; 629 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 630 clocks = <&baud_clk>, <&sys_clk>; 631 clock-names = "baud", "bus"; 632 status = "disabled"; 633 }; 634 635 mmc0: mmc@11230000 { 636 compatible = "mediatek,mt2712-mmc"; 637 reg = <0 0x11230000 0 0x1000>; 638 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 639 clocks = <&pericfg CLK_PERI_MSDC30_0>, 640 <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, 641 <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, 642 <&pericfg CLK_PERI_MSDC50_0_EN>; 643 clock-names = "source", "hclk", "bus_clk", "source_cg"; 644 status = "disabled"; 645 }; 646 647 mmc1: mmc@11240000 { 648 compatible = "mediatek,mt2712-mmc"; 649 reg = <0 0x11240000 0 0x1000>; 650 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 651 clocks = <&pericfg CLK_PERI_MSDC30_1>, 652 <&topckgen CLK_TOP_AXI_SEL>, 653 <&pericfg CLK_PERI_MSDC30_1_EN>; 654 clock-names = "source", "hclk", "source_cg"; 655 status = "disabled"; 656 }; 657 658 mmc2: mmc@11250000 { 659 compatible = "mediatek,mt2712-mmc"; 660 reg = <0 0x11250000 0 0x1000>; 661 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 662 clocks = <&pericfg CLK_PERI_MSDC30_2>, 663 <&topckgen CLK_TOP_AXI_SEL>, 664 <&pericfg CLK_PERI_MSDC30_2_EN>; 665 clock-names = "source", "hclk", "source_cg"; 666 status = "disabled"; 667 }; 668 669 ssusb: usb@11271000 { 670 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 671 reg = <0 0x11271000 0 0x3000>, 672 <0 0x11280700 0 0x0100>; 673 reg-names = "mac", "ippc"; 674 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 675 phys = <&u2port0 PHY_TYPE_USB2>, 676 <&u2port1 PHY_TYPE_USB2>; 677 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 678 clocks = <&topckgen CLK_TOP_USB30_SEL>; 679 clock-names = "sys_ck"; 680 mediatek,syscon-wakeup = <&pericfg 0x510 2>; 681 #address-cells = <2>; 682 #size-cells = <2>; 683 ranges; 684 status = "disabled"; 685 686 usb_host0: xhci@11270000 { 687 compatible = "mediatek,mt2712-xhci", 688 "mediatek,mtk-xhci"; 689 reg = <0 0x11270000 0 0x1000>; 690 reg-names = "mac"; 691 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 692 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 693 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 694 clock-names = "sys_ck", "ref_ck"; 695 status = "disabled"; 696 }; 697 }; 698 699 u3phy0: usb-phy@11290000 { 700 compatible = "mediatek,mt2712-u3phy"; 701 #address-cells = <2>; 702 #size-cells = <2>; 703 ranges; 704 status = "okay"; 705 706 u2port0: usb-phy@11290000 { 707 reg = <0 0x11290000 0 0x700>; 708 clocks = <&clk26m>; 709 clock-names = "ref"; 710 #phy-cells = <1>; 711 status = "okay"; 712 }; 713 714 u2port1: usb-phy@11298000 { 715 reg = <0 0x11298000 0 0x700>; 716 clocks = <&clk26m>; 717 clock-names = "ref"; 718 #phy-cells = <1>; 719 status = "okay"; 720 }; 721 722 u3port0: usb-phy@11298700 { 723 reg = <0 0x11298700 0 0x900>; 724 clocks = <&clk26m>; 725 clock-names = "ref"; 726 #phy-cells = <1>; 727 status = "okay"; 728 }; 729 }; 730 731 ssusb1: usb@112c1000 { 732 compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 733 reg = <0 0x112c1000 0 0x3000>, 734 <0 0x112d0700 0 0x0100>; 735 reg-names = "mac", "ippc"; 736 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 737 phys = <&u2port2 PHY_TYPE_USB2>, 738 <&u2port3 PHY_TYPE_USB2>, 739 <&u3port1 PHY_TYPE_USB3>; 740 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 741 clocks = <&topckgen CLK_TOP_USB30_SEL>; 742 clock-names = "sys_ck"; 743 mediatek,syscon-wakeup = <&pericfg 0x514 2>; 744 #address-cells = <2>; 745 #size-cells = <2>; 746 ranges; 747 status = "disabled"; 748 749 usb_host1: xhci@112c0000 { 750 compatible = "mediatek,mt2712-xhci", 751 "mediatek,mtk-xhci"; 752 reg = <0 0x112c0000 0 0x1000>; 753 reg-names = "mac"; 754 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 755 power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 756 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 757 clock-names = "sys_ck", "ref_ck"; 758 status = "disabled"; 759 }; 760 }; 761 762 u3phy1: usb-phy@112e0000 { 763 compatible = "mediatek,mt2712-u3phy"; 764 #address-cells = <2>; 765 #size-cells = <2>; 766 ranges; 767 status = "okay"; 768 769 u2port2: usb-phy@112e0000 { 770 reg = <0 0x112e0000 0 0x700>; 771 clocks = <&clk26m>; 772 clock-names = "ref"; 773 #phy-cells = <1>; 774 status = "okay"; 775 }; 776 777 u2port3: usb-phy@112e8000 { 778 reg = <0 0x112e8000 0 0x700>; 779 clocks = <&clk26m>; 780 clock-names = "ref"; 781 #phy-cells = <1>; 782 status = "okay"; 783 }; 784 785 u3port1: usb-phy@112e8700 { 786 reg = <0 0x112e8700 0 0x900>; 787 clocks = <&clk26m>; 788 clock-names = "ref"; 789 #phy-cells = <1>; 790 status = "okay"; 791 }; 792 }; 793 794 pcie: pcie@11700000 { 795 compatible = "mediatek,mt2712-pcie"; 796 device_type = "pci"; 797 reg = <0 0x11700000 0 0x1000>, 798 <0 0x112ff000 0 0x1000>; 799 reg-names = "port0", "port1"; 800 #address-cells = <3>; 801 #size-cells = <2>; 802 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 805 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 806 <&pericfg CLK_PERI_PCIE0>, 807 <&pericfg CLK_PERI_PCIE1>; 808 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; 809 phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; 810 phy-names = "pcie-phy0", "pcie-phy1"; 811 bus-range = <0x00 0xff>; 812 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 813 814 pcie0: pcie@0,0 { 815 device_type = "pci"; 816 status = "disabled"; 817 reg = <0x0000 0 0 0 0>; 818 #address-cells = <3>; 819 #size-cells = <2>; 820 #interrupt-cells = <1>; 821 ranges; 822 interrupt-map-mask = <0 0 0 7>; 823 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 824 <0 0 0 2 &pcie_intc0 1>, 825 <0 0 0 3 &pcie_intc0 2>, 826 <0 0 0 4 &pcie_intc0 3>; 827 pcie_intc0: interrupt-controller { 828 interrupt-controller; 829 #address-cells = <0>; 830 #interrupt-cells = <1>; 831 }; 832 }; 833 834 pcie1: pcie@1,0 { 835 device_type = "pci"; 836 status = "disabled"; 837 reg = <0x0800 0 0 0 0>; 838 #address-cells = <3>; 839 #size-cells = <2>; 840 #interrupt-cells = <1>; 841 ranges; 842 interrupt-map-mask = <0 0 0 7>; 843 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 844 <0 0 0 2 &pcie_intc1 1>, 845 <0 0 0 3 &pcie_intc1 2>, 846 <0 0 0 4 &pcie_intc1 3>; 847 pcie_intc1: interrupt-controller { 848 interrupt-controller; 849 #address-cells = <0>; 850 #interrupt-cells = <1>; 851 }; 852 }; 853 }; 854 855 mfgcfg: syscon@13000000 { 856 compatible = "mediatek,mt2712-mfgcfg", "syscon"; 857 reg = <0 0x13000000 0 0x1000>; 858 #clock-cells = <1>; 859 }; 860 861 mmsys: syscon@14000000 { 862 compatible = "mediatek,mt2712-mmsys", "syscon"; 863 reg = <0 0x14000000 0 0x1000>; 864 #clock-cells = <1>; 865 }; 866 867 larb0: larb@14021000 { 868 compatible = "mediatek,mt2712-smi-larb"; 869 reg = <0 0x14021000 0 0x1000>; 870 mediatek,smi = <&smi_common0>; 871 mediatek,larb-id = <0>; 872 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 873 clocks = <&mmsys CLK_MM_SMI_LARB0>, 874 <&mmsys CLK_MM_SMI_LARB0>; 875 clock-names = "apb", "smi"; 876 }; 877 878 smi_common0: smi@14022000 { 879 compatible = "mediatek,mt2712-smi-common"; 880 reg = <0 0x14022000 0 0x1000>; 881 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 882 clocks = <&mmsys CLK_MM_SMI_COMMON>, 883 <&mmsys CLK_MM_SMI_COMMON>; 884 clock-names = "apb", "smi"; 885 }; 886 887 larb4: larb@14027000 { 888 compatible = "mediatek,mt2712-smi-larb"; 889 reg = <0 0x14027000 0 0x1000>; 890 mediatek,smi = <&smi_common1>; 891 mediatek,larb-id = <4>; 892 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 893 clocks = <&mmsys CLK_MM_SMI_LARB4>, 894 <&mmsys CLK_MM_SMI_LARB4>; 895 clock-names = "apb", "smi"; 896 }; 897 898 larb5: larb@14030000 { 899 compatible = "mediatek,mt2712-smi-larb"; 900 reg = <0 0x14030000 0 0x1000>; 901 mediatek,smi = <&smi_common1>; 902 mediatek,larb-id = <5>; 903 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 904 clocks = <&mmsys CLK_MM_SMI_LARB5>, 905 <&mmsys CLK_MM_SMI_LARB5>; 906 clock-names = "apb", "smi"; 907 }; 908 909 smi_common1: smi@14031000 { 910 compatible = "mediatek,mt2712-smi-common"; 911 reg = <0 0x14031000 0 0x1000>; 912 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 913 clocks = <&mmsys CLK_MM_SMI_COMMON1>, 914 <&mmsys CLK_MM_SMI_COMMON1>; 915 clock-names = "apb", "smi"; 916 }; 917 918 larb7: larb@14032000 { 919 compatible = "mediatek,mt2712-smi-larb"; 920 reg = <0 0x14032000 0 0x1000>; 921 mediatek,smi = <&smi_common1>; 922 mediatek,larb-id = <7>; 923 power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 924 clocks = <&mmsys CLK_MM_SMI_LARB7>, 925 <&mmsys CLK_MM_SMI_LARB7>; 926 clock-names = "apb", "smi"; 927 }; 928 929 imgsys: syscon@15000000 { 930 compatible = "mediatek,mt2712-imgsys", "syscon"; 931 reg = <0 0x15000000 0 0x1000>; 932 #clock-cells = <1>; 933 }; 934 935 larb2: larb@15001000 { 936 compatible = "mediatek,mt2712-smi-larb"; 937 reg = <0 0x15001000 0 0x1000>; 938 mediatek,smi = <&smi_common0>; 939 mediatek,larb-id = <2>; 940 power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; 941 clocks = <&imgsys CLK_IMG_SMI_LARB2>, 942 <&imgsys CLK_IMG_SMI_LARB2>; 943 clock-names = "apb", "smi"; 944 }; 945 946 bdpsys: syscon@15010000 { 947 compatible = "mediatek,mt2712-bdpsys", "syscon"; 948 reg = <0 0x15010000 0 0x1000>; 949 #clock-cells = <1>; 950 }; 951 952 vdecsys: syscon@16000000 { 953 compatible = "mediatek,mt2712-vdecsys", "syscon"; 954 reg = <0 0x16000000 0 0x1000>; 955 #clock-cells = <1>; 956 }; 957 958 larb1: larb@16010000 { 959 compatible = "mediatek,mt2712-smi-larb"; 960 reg = <0 0x16010000 0 0x1000>; 961 mediatek,smi = <&smi_common0>; 962 mediatek,larb-id = <1>; 963 power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; 964 clocks = <&vdecsys CLK_VDEC_CKEN>, 965 <&vdecsys CLK_VDEC_LARB1_CKEN>; 966 clock-names = "apb", "smi"; 967 }; 968 969 vencsys: syscon@18000000 { 970 compatible = "mediatek,mt2712-vencsys", "syscon"; 971 reg = <0 0x18000000 0 0x1000>; 972 #clock-cells = <1>; 973 }; 974 975 larb3: larb@18001000 { 976 compatible = "mediatek,mt2712-smi-larb"; 977 reg = <0 0x18001000 0 0x1000>; 978 mediatek,smi = <&smi_common0>; 979 mediatek,larb-id = <3>; 980 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 981 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 982 <&vencsys CLK_VENC_VENC>; 983 clock-names = "apb", "smi"; 984 }; 985 986 larb6: larb@18002000 { 987 compatible = "mediatek,mt2712-smi-larb"; 988 reg = <0 0x18002000 0 0x1000>; 989 mediatek,smi = <&smi_common0>; 990 mediatek,larb-id = <6>; 991 power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 992 clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 993 <&vencsys CLK_VENC_VENC>; 994 clock-names = "apb", "smi"; 995 }; 996 997 jpgdecsys: syscon@19000000 { 998 compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 999 reg = <0 0x19000000 0 0x1000>; 1000 #clock-cells = <1>; 1001 }; 1002}; 1003 1004