1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7986a.dtsi"
9
10/ {
11	model = "MediaTek MT7986a RFB";
12	compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
13
14	aliases {
15		serial0 = &uart0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	memory@40000000 {
23		device_type = "memory";
24		reg = <0 0x40000000 0 0x40000000>;
25	};
26};
27
28&crypto {
29	status = "okay";
30};
31
32&eth {
33	status = "okay";
34
35	gmac0: mac@0 {
36		compatible = "mediatek,eth-mac";
37		reg = <0>;
38		phy-mode = "2500base-x";
39
40		fixed-link {
41			speed = <2500>;
42			full-duplex;
43			pause;
44		};
45	};
46
47	mdio: mdio-bus {
48		#address-cells = <1>;
49		#size-cells = <0>;
50	};
51};
52
53&mdio {
54	switch: switch@0 {
55		compatible = "mediatek,mt7531";
56		reg = <31>;
57		reset-gpios = <&pio 5 0>;
58	};
59};
60
61&pio {
62	spi_flash_pins: spi-flash-pins {
63		mux {
64			function = "spi";
65			groups = "spi0", "spi0_wp_hold";
66		};
67	};
68
69	spic_pins: spic-pins {
70		mux {
71			function = "spi";
72			groups = "spi1_2";
73		};
74	};
75
76	uart1_pins: uart1-pins {
77		mux {
78			function = "uart";
79			groups = "uart1";
80		};
81	};
82
83	uart2_pins: uart2-pins {
84		mux {
85			function = "uart";
86			groups = "uart2";
87		};
88	};
89
90	wf_2g_5g_pins: wf-2g-5g-pins {
91		mux {
92			function = "wifi";
93			groups = "wf_2g", "wf_5g";
94		};
95		conf {
96			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
97			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
98			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
99			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
100			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
101			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
102			       "WF1_TOP_CLK", "WF1_TOP_DATA";
103			drive-strength = <4>;
104		};
105	};
106
107	wf_dbdc_pins: wf-dbdc-pins {
108		mux {
109			function = "wifi";
110			groups = "wf_dbdc";
111		};
112		conf {
113			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
114			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
115			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
116			       "WF0_TOP_CLK", "WF0_TOP_DATA";
117			drive-strength = <4>;
118		};
119	};
120};
121
122&spi0 {
123	pinctrl-names = "default";
124	pinctrl-0 = <&spi_flash_pins>;
125	cs-gpios = <0>, <0>;
126	status = "okay";
127	spi_nand: spi_nand@0 {
128		compatible = "spi-nand";
129		reg = <0>;
130		spi-max-frequency = <10000000>;
131		spi-tx-buswidth = <4>;
132		spi-rx-buswidth = <4>;
133	};
134};
135
136&spi1 {
137	pinctrl-names = "default";
138	pinctrl-0 = <&spic_pins>;
139	cs-gpios = <0>, <0>;
140	status = "okay";
141};
142
143&switch {
144	ports {
145		#address-cells = <1>;
146		#size-cells = <0>;
147
148		port@0 {
149			reg = <0>;
150			label = "lan0";
151		};
152
153		port@1 {
154			reg = <1>;
155			label = "lan1";
156		};
157
158		port@2 {
159			reg = <2>;
160			label = "lan2";
161		};
162
163		port@3 {
164			reg = <3>;
165			label = "lan3";
166		};
167
168		port@4 {
169			reg = <4>;
170			label = "lan4";
171		};
172
173		port@6 {
174			reg = <6>;
175			label = "cpu";
176			ethernet = <&gmac0>;
177			phy-mode = "2500base-x";
178
179			fixed-link {
180				speed = <2500>;
181				full-duplex;
182				pause;
183			};
184		};
185	};
186};
187
188&uart0 {
189	status = "okay";
190};
191
192&uart1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&uart1_pins>;
195	status = "okay";
196};
197
198&uart2 {
199	pinctrl-names = "default";
200	pinctrl-0 = <&uart2_pins>;
201	status = "okay";
202};
203
204&wifi {
205	status = "okay";
206	pinctrl-names = "default", "dbdc";
207	pinctrl-0 = <&wf_2g_5g_pins>;
208	pinctrl-1 = <&wf_dbdc_pins>;
209};
210