xref: /linux/arch/arm64/boot/dts/mediatek/mt7986a.dtsi (revision 6c8c1406) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/mt7986-clk.h>
10#include <dt-bindings/reset/mt7986-resets.h>
11
12/ {
13	interrupt-parent = <&gic>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	clk40m: oscillator@0 {
18		compatible = "fixed-clock";
19		clock-frequency = <40000000>;
20		#clock-cells = <0>;
21		clock-output-names = "clkxtal";
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27		cpu0: cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			enable-method = "psci";
31			reg = <0x0>;
32			#cooling-cells = <2>;
33		};
34
35		cpu1: cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a53";
38			enable-method = "psci";
39			reg = <0x1>;
40			#cooling-cells = <2>;
41		};
42
43		cpu2: cpu@2 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a53";
46			enable-method = "psci";
47			reg = <0x2>;
48			#cooling-cells = <2>;
49		};
50
51		cpu3: cpu@3 {
52			device_type = "cpu";
53			enable-method = "psci";
54			compatible = "arm,cortex-a53";
55			reg = <0x3>;
56			#cooling-cells = <2>;
57		};
58	};
59
60	psci {
61		compatible = "arm,psci-0.2";
62		method = "smc";
63	};
64
65	reserved-memory {
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
70		secmon_reserved: secmon@43000000 {
71			reg = <0 0x43000000 0 0x30000>;
72			no-map;
73		};
74
75		wmcpu_emi: wmcpu-reserved@4fc00000 {
76			no-map;
77			reg = <0 0x4fc00000 0 0x00100000>;
78		};
79	};
80
81	timer {
82		compatible = "arm,armv8-timer";
83		interrupt-parent = <&gic>;
84		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
85			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
86			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
87			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
88	};
89
90	soc {
91		#address-cells = <2>;
92		#size-cells = <2>;
93		compatible = "simple-bus";
94		ranges;
95
96		gic: interrupt-controller@c000000 {
97			compatible = "arm,gic-v3";
98			#interrupt-cells = <3>;
99			interrupt-parent = <&gic>;
100			interrupt-controller;
101			reg = <0 0x0c000000 0 0x10000>,  /* GICD */
102			      <0 0x0c080000 0 0x80000>,  /* GICR */
103			      <0 0x0c400000 0 0x2000>,   /* GICC */
104			      <0 0x0c410000 0 0x1000>,   /* GICH */
105			      <0 0x0c420000 0 0x2000>;   /* GICV */
106			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
107		};
108
109		infracfg: infracfg@10001000 {
110			compatible = "mediatek,mt7986-infracfg", "syscon";
111			reg = <0 0x10001000 0 0x1000>;
112			#clock-cells = <1>;
113		};
114
115		topckgen: topckgen@1001b000 {
116			compatible = "mediatek,mt7986-topckgen", "syscon";
117			reg = <0 0x1001B000 0 0x1000>;
118			#clock-cells = <1>;
119		};
120
121		watchdog: watchdog@1001c000 {
122			compatible = "mediatek,mt7986-wdt",
123				     "mediatek,mt6589-wdt";
124			reg = <0 0x1001c000 0 0x1000>;
125			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
126			#reset-cells = <1>;
127			status = "disabled";
128		};
129
130		apmixedsys: apmixedsys@1001e000 {
131			compatible = "mediatek,mt7986-apmixedsys";
132			reg = <0 0x1001E000 0 0x1000>;
133			#clock-cells = <1>;
134		};
135
136		pio: pinctrl@1001f000 {
137			compatible = "mediatek,mt7986a-pinctrl";
138			reg = <0 0x1001f000 0 0x1000>,
139			      <0 0x11c30000 0 0x1000>,
140			      <0 0x11c40000 0 0x1000>,
141			      <0 0x11e20000 0 0x1000>,
142			      <0 0x11e30000 0 0x1000>,
143			      <0 0x11f00000 0 0x1000>,
144			      <0 0x11f10000 0 0x1000>,
145			      <0 0x1000b000 0 0x1000>;
146			reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
147				    "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
148			gpio-controller;
149			#gpio-cells = <2>;
150			gpio-ranges = <&pio 0 0 100>;
151			interrupt-controller;
152			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
153			interrupt-parent = <&gic>;
154			#interrupt-cells = <2>;
155		};
156
157		sgmiisys0: syscon@10060000 {
158			compatible = "mediatek,mt7986-sgmiisys_0",
159				     "syscon";
160			reg = <0 0x10060000 0 0x1000>;
161			#clock-cells = <1>;
162		};
163
164		sgmiisys1: syscon@10070000 {
165			compatible = "mediatek,mt7986-sgmiisys_1",
166				     "syscon";
167			reg = <0 0x10070000 0 0x1000>;
168			#clock-cells = <1>;
169		};
170
171		trng: trng@1020f000 {
172			compatible = "mediatek,mt7986-rng",
173				     "mediatek,mt7623-rng";
174			reg = <0 0x1020f000 0 0x100>;
175			clocks = <&infracfg CLK_INFRA_TRNG_CK>;
176			clock-names = "rng";
177			status = "disabled";
178		};
179
180		uart0: serial@11002000 {
181			compatible = "mediatek,mt7986-uart",
182				     "mediatek,mt6577-uart";
183			reg = <0 0x11002000 0 0x400>;
184			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
185			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
186				 <&infracfg CLK_INFRA_UART0_CK>;
187			clock-names = "baud", "bus";
188			assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
189					  <&infracfg CLK_INFRA_UART0_SEL>;
190			assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
191						 <&topckgen CLK_TOP_UART_SEL>;
192			status = "disabled";
193		};
194
195		uart1: serial@11003000 {
196			compatible = "mediatek,mt7986-uart",
197				     "mediatek,mt6577-uart";
198			reg = <0 0x11003000 0 0x400>;
199			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
200			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
201				 <&infracfg CLK_INFRA_UART1_CK>;
202			clock-names = "baud", "bus";
203			assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
204			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
205			status = "disabled";
206		};
207
208		uart2: serial@11004000 {
209			compatible = "mediatek,mt7986-uart",
210				     "mediatek,mt6577-uart";
211			reg = <0 0x11004000 0 0x400>;
212			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
213			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
214				 <&infracfg CLK_INFRA_UART2_CK>;
215			clock-names = "baud", "bus";
216			assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
217			assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
218			status = "disabled";
219		};
220
221		ethsys: syscon@15000000 {
222			 #address-cells = <1>;
223			 #size-cells = <1>;
224			 compatible = "mediatek,mt7986-ethsys",
225				      "syscon";
226			 reg = <0 0x15000000 0 0x1000>;
227			 #clock-cells = <1>;
228			 #reset-cells = <1>;
229		};
230
231		wed_pcie: wed-pcie@10003000 {
232			compatible = "mediatek,mt7986-wed-pcie",
233				     "syscon";
234			reg = <0 0x10003000 0 0x10>;
235		};
236
237		wed0: wed@15010000 {
238			compatible = "mediatek,mt7986-wed",
239				     "syscon";
240			reg = <0 0x15010000 0 0x1000>;
241			interrupt-parent = <&gic>;
242			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
243		};
244
245		wed1: wed@15011000 {
246			compatible = "mediatek,mt7986-wed",
247				     "syscon";
248			reg = <0 0x15011000 0 0x1000>;
249			interrupt-parent = <&gic>;
250			interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
251		};
252
253		eth: ethernet@15100000 {
254			compatible = "mediatek,mt7986-eth";
255			reg = <0 0x15100000 0 0x80000>;
256			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
257				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
258				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
259				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
260			clocks = <&ethsys CLK_ETH_FE_EN>,
261				 <&ethsys CLK_ETH_GP2_EN>,
262				 <&ethsys CLK_ETH_GP1_EN>,
263				 <&ethsys CLK_ETH_WOCPU1_EN>,
264				 <&ethsys CLK_ETH_WOCPU0_EN>,
265				 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
266				 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
267				 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
268				 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
269				 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
270				 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
271				 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
272				 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
273				 <&topckgen CLK_TOP_NETSYS_SEL>,
274				 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
275			clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
276				      "sgmii_tx250m", "sgmii_rx250m",
277				      "sgmii_cdr_ref", "sgmii_cdr_fb",
278				      "sgmii2_tx250m", "sgmii2_rx250m",
279				      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
280				      "netsys0", "netsys1";
281			assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
282					  <&topckgen CLK_TOP_SGM_325M_SEL>;
283			assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
284						 <&apmixedsys CLK_APMIXED_SGMPLL>;
285			mediatek,ethsys = <&ethsys>;
286			mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
287			mediatek,wed-pcie = <&wed_pcie>;
288			mediatek,wed = <&wed0>, <&wed1>;
289			#reset-cells = <1>;
290			#address-cells = <1>;
291			#size-cells = <0>;
292			status = "disabled";
293		};
294
295		wifi: wifi@18000000 {
296			compatible = "mediatek,mt7986-wmac";
297			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
298			reset-names = "consys";
299			clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
300				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
301			clock-names = "mcu", "ap2conn";
302			reg = <0 0x18000000 0 0x1000000>,
303			      <0 0x10003000 0 0x1000>,
304			      <0 0x11d10000 0 0x1000>;
305			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
306				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
307				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
308				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
309			memory-region = <&wmcpu_emi>;
310		};
311	};
312
313};
314