1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10 11/ { 12 compatible = "nvidia,tegra194"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* control backbone */ 18 cbb@0 { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges = <0x0 0x0 0x0 0x40000000>; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra194-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x2200000 0x10000>, 28 <0x2210000 0x10000>; 29 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra194-eqos", 43 "nvidia,tegra186-eqos", 44 "snps,dwc-qos-ethernet-4.10"; 45 reg = <0x02490000 0x10000>; 46 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 47 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 48 <&bpmp TEGRA194_CLK_EQOS_AXI>, 49 <&bpmp TEGRA194_CLK_EQOS_RX>, 50 <&bpmp TEGRA194_CLK_EQOS_TX>, 51 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 52 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 53 resets = <&bpmp TEGRA194_RESET_EQOS>; 54 reset-names = "eqos"; 55 status = "disabled"; 56 57 snps,write-requests = <1>; 58 snps,read-requests = <3>; 59 snps,burst-map = <0x7>; 60 snps,txpbl = <16>; 61 snps,rxpbl = <8>; 62 }; 63 64 aconnect@2900000 { 65 compatible = "nvidia,tegra194-aconnect", 66 "nvidia,tegra210-aconnect"; 67 clocks = <&bpmp TEGRA194_CLK_APE>, 68 <&bpmp TEGRA194_CLK_APB2APE>; 69 clock-names = "ape", "apb2ape"; 70 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 ranges = <0x02900000 0x02900000 0x200000>; 74 status = "disabled"; 75 76 dma-controller@2930000 { 77 compatible = "nvidia,tegra194-adma", 78 "nvidia,tegra186-adma"; 79 reg = <0x02930000 0x20000>; 80 interrupt-parent = <&agic>; 81 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 113 #dma-cells = <1>; 114 clocks = <&bpmp TEGRA194_CLK_AHUB>; 115 clock-names = "d_audio"; 116 status = "disabled"; 117 }; 118 119 agic: interrupt-controller@2a40000 { 120 compatible = "nvidia,tegra194-agic", 121 "nvidia,tegra210-agic"; 122 #interrupt-cells = <3>; 123 interrupt-controller; 124 reg = <0x02a41000 0x1000>, 125 <0x02a42000 0x2000>; 126 interrupts = <GIC_SPI 145 127 (GIC_CPU_MASK_SIMPLE(4) | 128 IRQ_TYPE_LEVEL_HIGH)>; 129 clocks = <&bpmp TEGRA194_CLK_APE>; 130 clock-names = "clk"; 131 status = "disabled"; 132 }; 133 }; 134 135 pinmux: pinmux@2430000 { 136 compatible = "nvidia,tegra194-pinmux"; 137 reg = <0x2430000 0x17000 138 0xc300000 0x4000>; 139 140 status = "okay"; 141 142 pex_rst_c5_out_state: pex_rst_c5_out { 143 pex_rst { 144 nvidia,pins = "pex_l5_rst_n_pgg1"; 145 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 146 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 147 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 148 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 149 nvidia,tristate = <TEGRA_PIN_DISABLE>; 150 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 151 }; 152 }; 153 154 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 155 clkreq { 156 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 157 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 158 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 159 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 160 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 161 nvidia,tristate = <TEGRA_PIN_DISABLE>; 162 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 163 }; 164 }; 165 }; 166 167 uarta: serial@3100000 { 168 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 169 reg = <0x03100000 0x40>; 170 reg-shift = <2>; 171 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&bpmp TEGRA194_CLK_UARTA>; 173 clock-names = "serial"; 174 resets = <&bpmp TEGRA194_RESET_UARTA>; 175 reset-names = "serial"; 176 status = "disabled"; 177 }; 178 179 uartb: serial@3110000 { 180 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 181 reg = <0x03110000 0x40>; 182 reg-shift = <2>; 183 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&bpmp TEGRA194_CLK_UARTB>; 185 clock-names = "serial"; 186 resets = <&bpmp TEGRA194_RESET_UARTB>; 187 reset-names = "serial"; 188 status = "disabled"; 189 }; 190 191 uartd: serial@3130000 { 192 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 193 reg = <0x03130000 0x40>; 194 reg-shift = <2>; 195 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&bpmp TEGRA194_CLK_UARTD>; 197 clock-names = "serial"; 198 resets = <&bpmp TEGRA194_RESET_UARTD>; 199 reset-names = "serial"; 200 status = "disabled"; 201 }; 202 203 uarte: serial@3140000 { 204 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 205 reg = <0x03140000 0x40>; 206 reg-shift = <2>; 207 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&bpmp TEGRA194_CLK_UARTE>; 209 clock-names = "serial"; 210 resets = <&bpmp TEGRA194_RESET_UARTE>; 211 reset-names = "serial"; 212 status = "disabled"; 213 }; 214 215 uartf: serial@3150000 { 216 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 217 reg = <0x03150000 0x40>; 218 reg-shift = <2>; 219 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&bpmp TEGRA194_CLK_UARTF>; 221 clock-names = "serial"; 222 resets = <&bpmp TEGRA194_RESET_UARTF>; 223 reset-names = "serial"; 224 status = "disabled"; 225 }; 226 227 gen1_i2c: i2c@3160000 { 228 compatible = "nvidia,tegra194-i2c"; 229 reg = <0x03160000 0x10000>; 230 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clocks = <&bpmp TEGRA194_CLK_I2C1>; 234 clock-names = "div-clk"; 235 resets = <&bpmp TEGRA194_RESET_I2C1>; 236 reset-names = "i2c"; 237 status = "disabled"; 238 }; 239 240 uarth: serial@3170000 { 241 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 242 reg = <0x03170000 0x40>; 243 reg-shift = <2>; 244 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&bpmp TEGRA194_CLK_UARTH>; 246 clock-names = "serial"; 247 resets = <&bpmp TEGRA194_RESET_UARTH>; 248 reset-names = "serial"; 249 status = "disabled"; 250 }; 251 252 cam_i2c: i2c@3180000 { 253 compatible = "nvidia,tegra194-i2c"; 254 reg = <0x03180000 0x10000>; 255 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&bpmp TEGRA194_CLK_I2C3>; 259 clock-names = "div-clk"; 260 resets = <&bpmp TEGRA194_RESET_I2C3>; 261 reset-names = "i2c"; 262 status = "disabled"; 263 }; 264 265 /* shares pads with dpaux1 */ 266 dp_aux_ch1_i2c: i2c@3190000 { 267 compatible = "nvidia,tegra194-i2c"; 268 reg = <0x03190000 0x10000>; 269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 clocks = <&bpmp TEGRA194_CLK_I2C4>; 273 clock-names = "div-clk"; 274 resets = <&bpmp TEGRA194_RESET_I2C4>; 275 reset-names = "i2c"; 276 status = "disabled"; 277 }; 278 279 /* shares pads with dpaux0 */ 280 dp_aux_ch0_i2c: i2c@31b0000 { 281 compatible = "nvidia,tegra194-i2c"; 282 reg = <0x031b0000 0x10000>; 283 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&bpmp TEGRA194_CLK_I2C6>; 287 clock-names = "div-clk"; 288 resets = <&bpmp TEGRA194_RESET_I2C6>; 289 reset-names = "i2c"; 290 status = "disabled"; 291 }; 292 293 gen7_i2c: i2c@31c0000 { 294 compatible = "nvidia,tegra194-i2c"; 295 reg = <0x031c0000 0x10000>; 296 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clocks = <&bpmp TEGRA194_CLK_I2C7>; 300 clock-names = "div-clk"; 301 resets = <&bpmp TEGRA194_RESET_I2C7>; 302 reset-names = "i2c"; 303 status = "disabled"; 304 }; 305 306 gen9_i2c: i2c@31e0000 { 307 compatible = "nvidia,tegra194-i2c"; 308 reg = <0x031e0000 0x10000>; 309 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 clocks = <&bpmp TEGRA194_CLK_I2C9>; 313 clock-names = "div-clk"; 314 resets = <&bpmp TEGRA194_RESET_I2C9>; 315 reset-names = "i2c"; 316 status = "disabled"; 317 }; 318 319 pwm1: pwm@3280000 { 320 compatible = "nvidia,tegra194-pwm", 321 "nvidia,tegra186-pwm"; 322 reg = <0x3280000 0x10000>; 323 clocks = <&bpmp TEGRA194_CLK_PWM1>; 324 clock-names = "pwm"; 325 resets = <&bpmp TEGRA194_RESET_PWM1>; 326 reset-names = "pwm"; 327 status = "disabled"; 328 #pwm-cells = <2>; 329 }; 330 331 pwm2: pwm@3290000 { 332 compatible = "nvidia,tegra194-pwm", 333 "nvidia,tegra186-pwm"; 334 reg = <0x3290000 0x10000>; 335 clocks = <&bpmp TEGRA194_CLK_PWM2>; 336 clock-names = "pwm"; 337 resets = <&bpmp TEGRA194_RESET_PWM2>; 338 reset-names = "pwm"; 339 status = "disabled"; 340 #pwm-cells = <2>; 341 }; 342 343 pwm3: pwm@32a0000 { 344 compatible = "nvidia,tegra194-pwm", 345 "nvidia,tegra186-pwm"; 346 reg = <0x32a0000 0x10000>; 347 clocks = <&bpmp TEGRA194_CLK_PWM3>; 348 clock-names = "pwm"; 349 resets = <&bpmp TEGRA194_RESET_PWM3>; 350 reset-names = "pwm"; 351 status = "disabled"; 352 #pwm-cells = <2>; 353 }; 354 355 pwm5: pwm@32c0000 { 356 compatible = "nvidia,tegra194-pwm", 357 "nvidia,tegra186-pwm"; 358 reg = <0x32c0000 0x10000>; 359 clocks = <&bpmp TEGRA194_CLK_PWM5>; 360 clock-names = "pwm"; 361 resets = <&bpmp TEGRA194_RESET_PWM5>; 362 reset-names = "pwm"; 363 status = "disabled"; 364 #pwm-cells = <2>; 365 }; 366 367 pwm6: pwm@32d0000 { 368 compatible = "nvidia,tegra194-pwm", 369 "nvidia,tegra186-pwm"; 370 reg = <0x32d0000 0x10000>; 371 clocks = <&bpmp TEGRA194_CLK_PWM6>; 372 clock-names = "pwm"; 373 resets = <&bpmp TEGRA194_RESET_PWM6>; 374 reset-names = "pwm"; 375 status = "disabled"; 376 #pwm-cells = <2>; 377 }; 378 379 pwm7: pwm@32e0000 { 380 compatible = "nvidia,tegra194-pwm", 381 "nvidia,tegra186-pwm"; 382 reg = <0x32e0000 0x10000>; 383 clocks = <&bpmp TEGRA194_CLK_PWM7>; 384 clock-names = "pwm"; 385 resets = <&bpmp TEGRA194_RESET_PWM7>; 386 reset-names = "pwm"; 387 status = "disabled"; 388 #pwm-cells = <2>; 389 }; 390 391 pwm8: pwm@32f0000 { 392 compatible = "nvidia,tegra194-pwm", 393 "nvidia,tegra186-pwm"; 394 reg = <0x32f0000 0x10000>; 395 clocks = <&bpmp TEGRA194_CLK_PWM8>; 396 clock-names = "pwm"; 397 resets = <&bpmp TEGRA194_RESET_PWM8>; 398 reset-names = "pwm"; 399 status = "disabled"; 400 #pwm-cells = <2>; 401 }; 402 403 sdmmc1: sdhci@3400000 { 404 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 405 reg = <0x03400000 0x10000>; 406 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 408 clock-names = "sdhci"; 409 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 410 reset-names = "sdhci"; 411 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 412 <0x07>; 413 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 414 <0x07>; 415 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 416 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 417 <0x07>; 418 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 419 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 420 nvidia,default-tap = <0x9>; 421 nvidia,default-trim = <0x5>; 422 status = "disabled"; 423 }; 424 425 sdmmc3: sdhci@3440000 { 426 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 427 reg = <0x03440000 0x10000>; 428 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 430 clock-names = "sdhci"; 431 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 432 reset-names = "sdhci"; 433 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 434 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 435 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 436 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 437 <0x07>; 438 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 439 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 440 <0x07>; 441 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 442 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 443 nvidia,default-tap = <0x9>; 444 nvidia,default-trim = <0x5>; 445 status = "disabled"; 446 }; 447 448 sdmmc4: sdhci@3460000 { 449 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 450 reg = <0x03460000 0x10000>; 451 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 453 clock-names = "sdhci"; 454 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 455 <&bpmp TEGRA194_CLK_PLLC4>; 456 assigned-clock-parents = 457 <&bpmp TEGRA194_CLK_PLLC4>; 458 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 459 reset-names = "sdhci"; 460 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 461 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 462 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 463 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 464 <0x0a>; 465 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 466 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 467 <0x0a>; 468 nvidia,default-tap = <0x8>; 469 nvidia,default-trim = <0x14>; 470 nvidia,dqs-trim = <40>; 471 supports-cqe; 472 status = "disabled"; 473 }; 474 475 hda@3510000 { 476 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 477 reg = <0x3510000 0x10000>; 478 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&bpmp TEGRA194_CLK_HDA>, 480 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 481 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 482 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 483 resets = <&bpmp TEGRA194_RESET_HDA>, 484 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 485 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 486 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 487 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 488 status = "disabled"; 489 }; 490 491 gic: interrupt-controller@3881000 { 492 compatible = "arm,gic-400"; 493 #interrupt-cells = <3>; 494 interrupt-controller; 495 reg = <0x03881000 0x1000>, 496 <0x03882000 0x2000>, 497 <0x03884000 0x2000>, 498 <0x03886000 0x2000>; 499 interrupts = <GIC_PPI 9 500 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 501 interrupt-parent = <&gic>; 502 }; 503 504 cec@3960000 { 505 compatible = "nvidia,tegra194-cec"; 506 reg = <0x03960000 0x10000>; 507 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&bpmp TEGRA194_CLK_CEC>; 509 clock-names = "cec"; 510 status = "disabled"; 511 }; 512 513 hsp_top0: hsp@3c00000 { 514 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 515 reg = <0x03c00000 0xa0000>; 516 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 526 "shared3", "shared4", "shared5", "shared6", 527 "shared7"; 528 #mbox-cells = <2>; 529 }; 530 531 p2u_hsio_0: phy@3e10000 { 532 compatible = "nvidia,tegra194-p2u"; 533 reg = <0x03e10000 0x10000>; 534 reg-names = "ctl"; 535 536 #phy-cells = <0>; 537 }; 538 539 p2u_hsio_1: phy@3e20000 { 540 compatible = "nvidia,tegra194-p2u"; 541 reg = <0x03e20000 0x10000>; 542 reg-names = "ctl"; 543 544 #phy-cells = <0>; 545 }; 546 547 p2u_hsio_2: phy@3e30000 { 548 compatible = "nvidia,tegra194-p2u"; 549 reg = <0x03e30000 0x10000>; 550 reg-names = "ctl"; 551 552 #phy-cells = <0>; 553 }; 554 555 p2u_hsio_3: phy@3e40000 { 556 compatible = "nvidia,tegra194-p2u"; 557 reg = <0x03e40000 0x10000>; 558 reg-names = "ctl"; 559 560 #phy-cells = <0>; 561 }; 562 563 p2u_hsio_4: phy@3e50000 { 564 compatible = "nvidia,tegra194-p2u"; 565 reg = <0x03e50000 0x10000>; 566 reg-names = "ctl"; 567 568 #phy-cells = <0>; 569 }; 570 571 p2u_hsio_5: phy@3e60000 { 572 compatible = "nvidia,tegra194-p2u"; 573 reg = <0x03e60000 0x10000>; 574 reg-names = "ctl"; 575 576 #phy-cells = <0>; 577 }; 578 579 p2u_hsio_6: phy@3e70000 { 580 compatible = "nvidia,tegra194-p2u"; 581 reg = <0x03e70000 0x10000>; 582 reg-names = "ctl"; 583 584 #phy-cells = <0>; 585 }; 586 587 p2u_hsio_7: phy@3e80000 { 588 compatible = "nvidia,tegra194-p2u"; 589 reg = <0x03e80000 0x10000>; 590 reg-names = "ctl"; 591 592 #phy-cells = <0>; 593 }; 594 595 p2u_hsio_8: phy@3e90000 { 596 compatible = "nvidia,tegra194-p2u"; 597 reg = <0x03e90000 0x10000>; 598 reg-names = "ctl"; 599 600 #phy-cells = <0>; 601 }; 602 603 p2u_hsio_9: phy@3ea0000 { 604 compatible = "nvidia,tegra194-p2u"; 605 reg = <0x03ea0000 0x10000>; 606 reg-names = "ctl"; 607 608 #phy-cells = <0>; 609 }; 610 611 p2u_nvhs_0: phy@3eb0000 { 612 compatible = "nvidia,tegra194-p2u"; 613 reg = <0x03eb0000 0x10000>; 614 reg-names = "ctl"; 615 616 #phy-cells = <0>; 617 }; 618 619 p2u_nvhs_1: phy@3ec0000 { 620 compatible = "nvidia,tegra194-p2u"; 621 reg = <0x03ec0000 0x10000>; 622 reg-names = "ctl"; 623 624 #phy-cells = <0>; 625 }; 626 627 p2u_nvhs_2: phy@3ed0000 { 628 compatible = "nvidia,tegra194-p2u"; 629 reg = <0x03ed0000 0x10000>; 630 reg-names = "ctl"; 631 632 #phy-cells = <0>; 633 }; 634 635 p2u_nvhs_3: phy@3ee0000 { 636 compatible = "nvidia,tegra194-p2u"; 637 reg = <0x03ee0000 0x10000>; 638 reg-names = "ctl"; 639 640 #phy-cells = <0>; 641 }; 642 643 p2u_nvhs_4: phy@3ef0000 { 644 compatible = "nvidia,tegra194-p2u"; 645 reg = <0x03ef0000 0x10000>; 646 reg-names = "ctl"; 647 648 #phy-cells = <0>; 649 }; 650 651 p2u_nvhs_5: phy@3f00000 { 652 compatible = "nvidia,tegra194-p2u"; 653 reg = <0x03f00000 0x10000>; 654 reg-names = "ctl"; 655 656 #phy-cells = <0>; 657 }; 658 659 p2u_nvhs_6: phy@3f10000 { 660 compatible = "nvidia,tegra194-p2u"; 661 reg = <0x03f10000 0x10000>; 662 reg-names = "ctl"; 663 664 #phy-cells = <0>; 665 }; 666 667 p2u_nvhs_7: phy@3f20000 { 668 compatible = "nvidia,tegra194-p2u"; 669 reg = <0x03f20000 0x10000>; 670 reg-names = "ctl"; 671 672 #phy-cells = <0>; 673 }; 674 675 p2u_hsio_10: phy@3f30000 { 676 compatible = "nvidia,tegra194-p2u"; 677 reg = <0x03f30000 0x10000>; 678 reg-names = "ctl"; 679 680 #phy-cells = <0>; 681 }; 682 683 p2u_hsio_11: phy@3f40000 { 684 compatible = "nvidia,tegra194-p2u"; 685 reg = <0x03f40000 0x10000>; 686 reg-names = "ctl"; 687 688 #phy-cells = <0>; 689 }; 690 691 hsp_aon: hsp@c150000 { 692 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 693 reg = <0x0c150000 0xa0000>; 694 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 698 /* 699 * Shared interrupt 0 is routed only to AON/SPE, so 700 * we only have 4 shared interrupts for the CCPLEX. 701 */ 702 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 703 #mbox-cells = <2>; 704 }; 705 706 gen2_i2c: i2c@c240000 { 707 compatible = "nvidia,tegra194-i2c"; 708 reg = <0x0c240000 0x10000>; 709 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 clocks = <&bpmp TEGRA194_CLK_I2C2>; 713 clock-names = "div-clk"; 714 resets = <&bpmp TEGRA194_RESET_I2C2>; 715 reset-names = "i2c"; 716 status = "disabled"; 717 }; 718 719 gen8_i2c: i2c@c250000 { 720 compatible = "nvidia,tegra194-i2c"; 721 reg = <0x0c250000 0x10000>; 722 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 clocks = <&bpmp TEGRA194_CLK_I2C8>; 726 clock-names = "div-clk"; 727 resets = <&bpmp TEGRA194_RESET_I2C8>; 728 reset-names = "i2c"; 729 status = "disabled"; 730 }; 731 732 uartc: serial@c280000 { 733 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 734 reg = <0x0c280000 0x40>; 735 reg-shift = <2>; 736 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&bpmp TEGRA194_CLK_UARTC>; 738 clock-names = "serial"; 739 resets = <&bpmp TEGRA194_RESET_UARTC>; 740 reset-names = "serial"; 741 status = "disabled"; 742 }; 743 744 uartg: serial@c290000 { 745 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 746 reg = <0x0c290000 0x40>; 747 reg-shift = <2>; 748 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&bpmp TEGRA194_CLK_UARTG>; 750 clock-names = "serial"; 751 resets = <&bpmp TEGRA194_RESET_UARTG>; 752 reset-names = "serial"; 753 status = "disabled"; 754 }; 755 756 rtc: rtc@c2a0000 { 757 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 758 reg = <0x0c2a0000 0x10000>; 759 interrupt-parent = <&pmc>; 760 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 762 clock-names = "rtc"; 763 status = "disabled"; 764 }; 765 766 gpio_aon: gpio@c2f0000 { 767 compatible = "nvidia,tegra194-gpio-aon"; 768 reg-names = "security", "gpio"; 769 reg = <0xc2f0000 0x1000>, 770 <0xc2f1000 0x1000>; 771 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 775 gpio-controller; 776 #gpio-cells = <2>; 777 interrupt-controller; 778 #interrupt-cells = <2>; 779 }; 780 781 pwm4: pwm@c340000 { 782 compatible = "nvidia,tegra194-pwm", 783 "nvidia,tegra186-pwm"; 784 reg = <0xc340000 0x10000>; 785 clocks = <&bpmp TEGRA194_CLK_PWM4>; 786 clock-names = "pwm"; 787 resets = <&bpmp TEGRA194_RESET_PWM4>; 788 reset-names = "pwm"; 789 status = "disabled"; 790 #pwm-cells = <2>; 791 }; 792 793 pmc: pmc@c360000 { 794 compatible = "nvidia,tegra194-pmc"; 795 reg = <0x0c360000 0x10000>, 796 <0x0c370000 0x10000>, 797 <0x0c380000 0x10000>, 798 <0x0c390000 0x10000>, 799 <0x0c3a0000 0x10000>; 800 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 801 802 #interrupt-cells = <2>; 803 interrupt-controller; 804 }; 805 806 host1x@13e00000 { 807 compatible = "nvidia,tegra194-host1x", "simple-bus"; 808 reg = <0x13e00000 0x10000>, 809 <0x13e10000 0x10000>; 810 reg-names = "hypervisor", "vm"; 811 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 814 clock-names = "host1x"; 815 resets = <&bpmp TEGRA194_RESET_HOST1X>; 816 reset-names = "host1x"; 817 818 #address-cells = <1>; 819 #size-cells = <1>; 820 821 ranges = <0x15000000 0x15000000 0x01000000>; 822 823 display-hub@15200000 { 824 compatible = "nvidia,tegra194-display", "simple-bus"; 825 reg = <0x15200000 0x00040000>; 826 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 827 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 828 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 829 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 830 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 831 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 832 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 833 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 834 "wgrp3", "wgrp4", "wgrp5"; 835 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 836 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 837 clock-names = "disp", "hub"; 838 status = "disabled"; 839 840 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 841 842 #address-cells = <1>; 843 #size-cells = <1>; 844 845 ranges = <0x15200000 0x15200000 0x40000>; 846 847 display@15200000 { 848 compatible = "nvidia,tegra194-dc"; 849 reg = <0x15200000 0x10000>; 850 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 852 clock-names = "dc"; 853 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 854 reset-names = "dc"; 855 856 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 857 858 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 859 nvidia,head = <0>; 860 }; 861 862 display@15210000 { 863 compatible = "nvidia,tegra194-dc"; 864 reg = <0x15210000 0x10000>; 865 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 867 clock-names = "dc"; 868 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 869 reset-names = "dc"; 870 871 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 872 873 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 874 nvidia,head = <1>; 875 }; 876 877 display@15220000 { 878 compatible = "nvidia,tegra194-dc"; 879 reg = <0x15220000 0x10000>; 880 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 882 clock-names = "dc"; 883 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 884 reset-names = "dc"; 885 886 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 887 888 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 889 nvidia,head = <2>; 890 }; 891 892 display@15230000 { 893 compatible = "nvidia,tegra194-dc"; 894 reg = <0x15230000 0x10000>; 895 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 897 clock-names = "dc"; 898 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 899 reset-names = "dc"; 900 901 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 902 903 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 904 nvidia,head = <3>; 905 }; 906 }; 907 908 vic@15340000 { 909 compatible = "nvidia,tegra194-vic"; 910 reg = <0x15340000 0x00040000>; 911 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&bpmp TEGRA194_CLK_VIC>; 913 clock-names = "vic"; 914 resets = <&bpmp TEGRA194_RESET_VIC>; 915 reset-names = "vic"; 916 917 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 918 }; 919 920 dpaux0: dpaux@155c0000 { 921 compatible = "nvidia,tegra194-dpaux"; 922 reg = <0x155c0000 0x10000>; 923 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 925 <&bpmp TEGRA194_CLK_PLLDP>; 926 clock-names = "dpaux", "parent"; 927 resets = <&bpmp TEGRA194_RESET_DPAUX>; 928 reset-names = "dpaux"; 929 status = "disabled"; 930 931 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 932 933 state_dpaux0_aux: pinmux-aux { 934 groups = "dpaux-io"; 935 function = "aux"; 936 }; 937 938 state_dpaux0_i2c: pinmux-i2c { 939 groups = "dpaux-io"; 940 function = "i2c"; 941 }; 942 943 state_dpaux0_off: pinmux-off { 944 groups = "dpaux-io"; 945 function = "off"; 946 }; 947 948 i2c-bus { 949 #address-cells = <1>; 950 #size-cells = <0>; 951 }; 952 }; 953 954 dpaux1: dpaux@155d0000 { 955 compatible = "nvidia,tegra194-dpaux"; 956 reg = <0x155d0000 0x10000>; 957 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 959 <&bpmp TEGRA194_CLK_PLLDP>; 960 clock-names = "dpaux", "parent"; 961 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 962 reset-names = "dpaux"; 963 status = "disabled"; 964 965 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 966 967 state_dpaux1_aux: pinmux-aux { 968 groups = "dpaux-io"; 969 function = "aux"; 970 }; 971 972 state_dpaux1_i2c: pinmux-i2c { 973 groups = "dpaux-io"; 974 function = "i2c"; 975 }; 976 977 state_dpaux1_off: pinmux-off { 978 groups = "dpaux-io"; 979 function = "off"; 980 }; 981 982 i2c-bus { 983 #address-cells = <1>; 984 #size-cells = <0>; 985 }; 986 }; 987 988 dpaux2: dpaux@155e0000 { 989 compatible = "nvidia,tegra194-dpaux"; 990 reg = <0x155e0000 0x10000>; 991 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 993 <&bpmp TEGRA194_CLK_PLLDP>; 994 clock-names = "dpaux", "parent"; 995 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 996 reset-names = "dpaux"; 997 status = "disabled"; 998 999 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1000 1001 state_dpaux2_aux: pinmux-aux { 1002 groups = "dpaux-io"; 1003 function = "aux"; 1004 }; 1005 1006 state_dpaux2_i2c: pinmux-i2c { 1007 groups = "dpaux-io"; 1008 function = "i2c"; 1009 }; 1010 1011 state_dpaux2_off: pinmux-off { 1012 groups = "dpaux-io"; 1013 function = "off"; 1014 }; 1015 1016 i2c-bus { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 }; 1020 }; 1021 1022 dpaux3: dpaux@155f0000 { 1023 compatible = "nvidia,tegra194-dpaux"; 1024 reg = <0x155f0000 0x10000>; 1025 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1027 <&bpmp TEGRA194_CLK_PLLDP>; 1028 clock-names = "dpaux", "parent"; 1029 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1030 reset-names = "dpaux"; 1031 status = "disabled"; 1032 1033 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1034 1035 state_dpaux3_aux: pinmux-aux { 1036 groups = "dpaux-io"; 1037 function = "aux"; 1038 }; 1039 1040 state_dpaux3_i2c: pinmux-i2c { 1041 groups = "dpaux-io"; 1042 function = "i2c"; 1043 }; 1044 1045 state_dpaux3_off: pinmux-off { 1046 groups = "dpaux-io"; 1047 function = "off"; 1048 }; 1049 1050 i2c-bus { 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 }; 1054 }; 1055 1056 sor0: sor@15b00000 { 1057 compatible = "nvidia,tegra194-sor"; 1058 reg = <0x15b00000 0x40000>; 1059 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1061 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1062 <&bpmp TEGRA194_CLK_PLLD>, 1063 <&bpmp TEGRA194_CLK_PLLDP>, 1064 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1065 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1066 clock-names = "sor", "out", "parent", "dp", "safe", 1067 "pad"; 1068 resets = <&bpmp TEGRA194_RESET_SOR0>; 1069 reset-names = "sor"; 1070 pinctrl-0 = <&state_dpaux0_aux>; 1071 pinctrl-1 = <&state_dpaux0_i2c>; 1072 pinctrl-2 = <&state_dpaux0_off>; 1073 pinctrl-names = "aux", "i2c", "off"; 1074 status = "disabled"; 1075 1076 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1077 nvidia,interface = <0>; 1078 }; 1079 1080 sor1: sor@15b40000 { 1081 compatible = "nvidia,tegra194-sor"; 1082 reg = <0x15b40000 0x40000>; 1083 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1085 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1086 <&bpmp TEGRA194_CLK_PLLD2>, 1087 <&bpmp TEGRA194_CLK_PLLDP>, 1088 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1089 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1090 clock-names = "sor", "out", "parent", "dp", "safe", 1091 "pad"; 1092 resets = <&bpmp TEGRA194_RESET_SOR1>; 1093 reset-names = "sor"; 1094 pinctrl-0 = <&state_dpaux1_aux>; 1095 pinctrl-1 = <&state_dpaux1_i2c>; 1096 pinctrl-2 = <&state_dpaux1_off>; 1097 pinctrl-names = "aux", "i2c", "off"; 1098 status = "disabled"; 1099 1100 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1101 nvidia,interface = <1>; 1102 }; 1103 1104 sor2: sor@15b80000 { 1105 compatible = "nvidia,tegra194-sor"; 1106 reg = <0x15b80000 0x40000>; 1107 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1109 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1110 <&bpmp TEGRA194_CLK_PLLD3>, 1111 <&bpmp TEGRA194_CLK_PLLDP>, 1112 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1113 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1114 clock-names = "sor", "out", "parent", "dp", "safe", 1115 "pad"; 1116 resets = <&bpmp TEGRA194_RESET_SOR2>; 1117 reset-names = "sor"; 1118 pinctrl-0 = <&state_dpaux2_aux>; 1119 pinctrl-1 = <&state_dpaux2_i2c>; 1120 pinctrl-2 = <&state_dpaux2_off>; 1121 pinctrl-names = "aux", "i2c", "off"; 1122 status = "disabled"; 1123 1124 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1125 nvidia,interface = <2>; 1126 }; 1127 1128 sor3: sor@15bc0000 { 1129 compatible = "nvidia,tegra194-sor"; 1130 reg = <0x15bc0000 0x40000>; 1131 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1133 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1134 <&bpmp TEGRA194_CLK_PLLD4>, 1135 <&bpmp TEGRA194_CLK_PLLDP>, 1136 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1137 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1138 clock-names = "sor", "out", "parent", "dp", "safe", 1139 "pad"; 1140 resets = <&bpmp TEGRA194_RESET_SOR3>; 1141 reset-names = "sor"; 1142 pinctrl-0 = <&state_dpaux3_aux>; 1143 pinctrl-1 = <&state_dpaux3_i2c>; 1144 pinctrl-2 = <&state_dpaux3_off>; 1145 pinctrl-names = "aux", "i2c", "off"; 1146 status = "disabled"; 1147 1148 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1149 nvidia,interface = <3>; 1150 }; 1151 }; 1152 }; 1153 1154 pcie@14100000 { 1155 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1156 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1157 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 1158 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 1159 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1160 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1161 reg-names = "appl", "config", "atu_dma", "dbi"; 1162 1163 status = "disabled"; 1164 1165 #address-cells = <3>; 1166 #size-cells = <2>; 1167 device_type = "pci"; 1168 num-lanes = <1>; 1169 num-viewport = <8>; 1170 linux,pci-domain = <1>; 1171 1172 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1173 clock-names = "core"; 1174 1175 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1176 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1177 reset-names = "apb", "core"; 1178 1179 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1180 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1181 interrupt-names = "intr", "msi"; 1182 1183 #interrupt-cells = <1>; 1184 interrupt-map-mask = <0 0 0 0>; 1185 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1186 1187 nvidia,bpmp = <&bpmp 1>; 1188 1189 nvidia,aspm-cmrt-us = <60>; 1190 nvidia,aspm-pwr-on-t-us = <20>; 1191 nvidia,aspm-l0s-entrance-latency-us = <3>; 1192 1193 bus-range = <0x0 0xff>; 1194 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1195 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1196 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1197 }; 1198 1199 pcie@14120000 { 1200 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1201 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1202 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 1203 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 1204 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1205 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1206 reg-names = "appl", "config", "atu_dma", "dbi"; 1207 1208 status = "disabled"; 1209 1210 #address-cells = <3>; 1211 #size-cells = <2>; 1212 device_type = "pci"; 1213 num-lanes = <1>; 1214 num-viewport = <8>; 1215 linux,pci-domain = <2>; 1216 1217 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1218 clock-names = "core"; 1219 1220 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1221 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1222 reset-names = "apb", "core"; 1223 1224 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1225 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1226 interrupt-names = "intr", "msi"; 1227 1228 #interrupt-cells = <1>; 1229 interrupt-map-mask = <0 0 0 0>; 1230 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1231 1232 nvidia,bpmp = <&bpmp 2>; 1233 1234 nvidia,aspm-cmrt-us = <60>; 1235 nvidia,aspm-pwr-on-t-us = <20>; 1236 nvidia,aspm-l0s-entrance-latency-us = <3>; 1237 1238 bus-range = <0x0 0xff>; 1239 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1240 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1241 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1242 }; 1243 1244 pcie@14140000 { 1245 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1246 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1247 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 1248 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 1249 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1250 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1251 reg-names = "appl", "config", "atu_dma", "dbi"; 1252 1253 status = "disabled"; 1254 1255 #address-cells = <3>; 1256 #size-cells = <2>; 1257 device_type = "pci"; 1258 num-lanes = <1>; 1259 num-viewport = <8>; 1260 linux,pci-domain = <3>; 1261 1262 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1263 clock-names = "core"; 1264 1265 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1266 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1267 reset-names = "apb", "core"; 1268 1269 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1270 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1271 interrupt-names = "intr", "msi"; 1272 1273 #interrupt-cells = <1>; 1274 interrupt-map-mask = <0 0 0 0>; 1275 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1276 1277 nvidia,bpmp = <&bpmp 3>; 1278 1279 nvidia,aspm-cmrt-us = <60>; 1280 nvidia,aspm-pwr-on-t-us = <20>; 1281 nvidia,aspm-l0s-entrance-latency-us = <3>; 1282 1283 bus-range = <0x0 0xff>; 1284 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1285 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1286 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1287 }; 1288 1289 pcie@14160000 { 1290 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1291 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1292 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1293 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 1294 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1295 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1296 reg-names = "appl", "config", "atu_dma", "dbi"; 1297 1298 status = "disabled"; 1299 1300 #address-cells = <3>; 1301 #size-cells = <2>; 1302 device_type = "pci"; 1303 num-lanes = <4>; 1304 num-viewport = <8>; 1305 linux,pci-domain = <4>; 1306 1307 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1308 clock-names = "core"; 1309 1310 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1311 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1312 reset-names = "apb", "core"; 1313 1314 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1315 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1316 interrupt-names = "intr", "msi"; 1317 1318 #interrupt-cells = <1>; 1319 interrupt-map-mask = <0 0 0 0>; 1320 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1321 1322 nvidia,bpmp = <&bpmp 4>; 1323 1324 nvidia,aspm-cmrt-us = <60>; 1325 nvidia,aspm-pwr-on-t-us = <20>; 1326 nvidia,aspm-l0s-entrance-latency-us = <3>; 1327 1328 bus-range = <0x0 0xff>; 1329 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1330 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1331 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1332 }; 1333 1334 pcie@14180000 { 1335 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1336 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1337 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1338 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 1339 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1340 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1341 reg-names = "appl", "config", "atu_dma", "dbi"; 1342 1343 status = "disabled"; 1344 1345 #address-cells = <3>; 1346 #size-cells = <2>; 1347 device_type = "pci"; 1348 num-lanes = <8>; 1349 num-viewport = <8>; 1350 linux,pci-domain = <0>; 1351 1352 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1353 clock-names = "core"; 1354 1355 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1356 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1357 reset-names = "apb", "core"; 1358 1359 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1360 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1361 interrupt-names = "intr", "msi"; 1362 1363 #interrupt-cells = <1>; 1364 interrupt-map-mask = <0 0 0 0>; 1365 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1366 1367 nvidia,bpmp = <&bpmp 0>; 1368 1369 nvidia,aspm-cmrt-us = <60>; 1370 nvidia,aspm-pwr-on-t-us = <20>; 1371 nvidia,aspm-l0s-entrance-latency-us = <3>; 1372 1373 bus-range = <0x0 0xff>; 1374 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1375 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1376 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1377 }; 1378 1379 pcie@141a0000 { 1380 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1381 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1382 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1383 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 1384 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1385 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1386 reg-names = "appl", "config", "atu_dma", "dbi"; 1387 1388 status = "disabled"; 1389 1390 #address-cells = <3>; 1391 #size-cells = <2>; 1392 device_type = "pci"; 1393 num-lanes = <8>; 1394 num-viewport = <8>; 1395 linux,pci-domain = <5>; 1396 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1399 1400 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1401 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1402 clock-names = "core", "core_m"; 1403 1404 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1405 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1406 reset-names = "apb", "core"; 1407 1408 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1409 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1410 interrupt-names = "intr", "msi"; 1411 1412 nvidia,bpmp = <&bpmp 5>; 1413 1414 #interrupt-cells = <1>; 1415 interrupt-map-mask = <0 0 0 0>; 1416 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1417 1418 nvidia,aspm-cmrt-us = <60>; 1419 nvidia,aspm-pwr-on-t-us = <20>; 1420 nvidia,aspm-l0s-entrance-latency-us = <3>; 1421 1422 bus-range = <0x0 0xff>; 1423 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1424 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1425 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1426 }; 1427 1428 sysram@40000000 { 1429 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1430 reg = <0x0 0x40000000 0x0 0x50000>; 1431 #address-cells = <1>; 1432 #size-cells = <1>; 1433 ranges = <0x0 0x0 0x40000000 0x50000>; 1434 1435 cpu_bpmp_tx: shmem@4e000 { 1436 compatible = "nvidia,tegra194-bpmp-shmem"; 1437 reg = <0x4e000 0x1000>; 1438 label = "cpu-bpmp-tx"; 1439 pool; 1440 }; 1441 1442 cpu_bpmp_rx: shmem@4f000 { 1443 compatible = "nvidia,tegra194-bpmp-shmem"; 1444 reg = <0x4f000 0x1000>; 1445 label = "cpu-bpmp-rx"; 1446 pool; 1447 }; 1448 }; 1449 1450 bpmp: bpmp { 1451 compatible = "nvidia,tegra186-bpmp"; 1452 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1453 TEGRA_HSP_DB_MASTER_BPMP>; 1454 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1455 #clock-cells = <1>; 1456 #reset-cells = <1>; 1457 #power-domain-cells = <1>; 1458 1459 bpmp_i2c: i2c { 1460 compatible = "nvidia,tegra186-bpmp-i2c"; 1461 nvidia,bpmp-bus-id = <5>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 }; 1465 1466 bpmp_thermal: thermal { 1467 compatible = "nvidia,tegra186-bpmp-thermal"; 1468 #thermal-sensor-cells = <1>; 1469 }; 1470 }; 1471 1472 cpus { 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 1476 cpu0_0: cpu@0 { 1477 compatible = "nvidia,tegra194-carmel"; 1478 device_type = "cpu"; 1479 reg = <0x000>; 1480 enable-method = "psci"; 1481 i-cache-size = <131072>; 1482 i-cache-line-size = <64>; 1483 i-cache-sets = <512>; 1484 d-cache-size = <65536>; 1485 d-cache-line-size = <64>; 1486 d-cache-sets = <256>; 1487 next-level-cache = <&l2c_0>; 1488 }; 1489 1490 cpu0_1: cpu@1 { 1491 compatible = "nvidia,tegra194-carmel"; 1492 device_type = "cpu"; 1493 reg = <0x001>; 1494 enable-method = "psci"; 1495 i-cache-size = <131072>; 1496 i-cache-line-size = <64>; 1497 i-cache-sets = <512>; 1498 d-cache-size = <65536>; 1499 d-cache-line-size = <64>; 1500 d-cache-sets = <256>; 1501 next-level-cache = <&l2c_0>; 1502 }; 1503 1504 cpu1_0: cpu@100 { 1505 compatible = "nvidia,tegra194-carmel"; 1506 device_type = "cpu"; 1507 reg = <0x100>; 1508 enable-method = "psci"; 1509 i-cache-size = <131072>; 1510 i-cache-line-size = <64>; 1511 i-cache-sets = <512>; 1512 d-cache-size = <65536>; 1513 d-cache-line-size = <64>; 1514 d-cache-sets = <256>; 1515 next-level-cache = <&l2c_1>; 1516 }; 1517 1518 cpu1_1: cpu@101 { 1519 compatible = "nvidia,tegra194-carmel"; 1520 device_type = "cpu"; 1521 reg = <0x101>; 1522 enable-method = "psci"; 1523 i-cache-size = <131072>; 1524 i-cache-line-size = <64>; 1525 i-cache-sets = <512>; 1526 d-cache-size = <65536>; 1527 d-cache-line-size = <64>; 1528 d-cache-sets = <256>; 1529 next-level-cache = <&l2c_1>; 1530 }; 1531 1532 cpu2_0: cpu@200 { 1533 compatible = "nvidia,tegra194-carmel"; 1534 device_type = "cpu"; 1535 reg = <0x200>; 1536 enable-method = "psci"; 1537 i-cache-size = <131072>; 1538 i-cache-line-size = <64>; 1539 i-cache-sets = <512>; 1540 d-cache-size = <65536>; 1541 d-cache-line-size = <64>; 1542 d-cache-sets = <256>; 1543 next-level-cache = <&l2c_2>; 1544 }; 1545 1546 cpu2_1: cpu@201 { 1547 compatible = "nvidia,tegra194-carmel"; 1548 device_type = "cpu"; 1549 reg = <0x201>; 1550 enable-method = "psci"; 1551 i-cache-size = <131072>; 1552 i-cache-line-size = <64>; 1553 i-cache-sets = <512>; 1554 d-cache-size = <65536>; 1555 d-cache-line-size = <64>; 1556 d-cache-sets = <256>; 1557 next-level-cache = <&l2c_2>; 1558 }; 1559 1560 cpu3_0: cpu@300 { 1561 compatible = "nvidia,tegra194-carmel"; 1562 device_type = "cpu"; 1563 reg = <0x300>; 1564 enable-method = "psci"; 1565 i-cache-size = <131072>; 1566 i-cache-line-size = <64>; 1567 i-cache-sets = <512>; 1568 d-cache-size = <65536>; 1569 d-cache-line-size = <64>; 1570 d-cache-sets = <256>; 1571 next-level-cache = <&l2c_3>; 1572 }; 1573 1574 cpu3_1: cpu@301 { 1575 compatible = "nvidia,tegra194-carmel"; 1576 device_type = "cpu"; 1577 reg = <0x301>; 1578 enable-method = "psci"; 1579 i-cache-size = <131072>; 1580 i-cache-line-size = <64>; 1581 i-cache-sets = <512>; 1582 d-cache-size = <65536>; 1583 d-cache-line-size = <64>; 1584 d-cache-sets = <256>; 1585 next-level-cache = <&l2c_3>; 1586 }; 1587 1588 cpu-map { 1589 cluster0 { 1590 core0 { 1591 cpu = <&cpu0_0>; 1592 }; 1593 1594 core1 { 1595 cpu = <&cpu0_1>; 1596 }; 1597 }; 1598 1599 cluster1 { 1600 core0 { 1601 cpu = <&cpu1_0>; 1602 }; 1603 1604 core1 { 1605 cpu = <&cpu1_1>; 1606 }; 1607 }; 1608 1609 cluster2 { 1610 core0 { 1611 cpu = <&cpu2_0>; 1612 }; 1613 1614 core1 { 1615 cpu = <&cpu2_1>; 1616 }; 1617 }; 1618 1619 cluster3 { 1620 core0 { 1621 cpu = <&cpu3_0>; 1622 }; 1623 1624 core1 { 1625 cpu = <&cpu3_1>; 1626 }; 1627 }; 1628 }; 1629 1630 l2c_0: l2-cache0 { 1631 cache-size = <2097152>; 1632 cache-line-size = <64>; 1633 cache-sets = <2048>; 1634 next-level-cache = <&l3c>; 1635 }; 1636 1637 l2c_1: l2-cache1 { 1638 cache-size = <2097152>; 1639 cache-line-size = <64>; 1640 cache-sets = <2048>; 1641 next-level-cache = <&l3c>; 1642 }; 1643 1644 l2c_2: l2-cache2 { 1645 cache-size = <2097152>; 1646 cache-line-size = <64>; 1647 cache-sets = <2048>; 1648 next-level-cache = <&l3c>; 1649 }; 1650 1651 l2c_3: l2-cache3 { 1652 cache-size = <2097152>; 1653 cache-line-size = <64>; 1654 cache-sets = <2048>; 1655 next-level-cache = <&l3c>; 1656 }; 1657 1658 l3c: l3-cache { 1659 cache-size = <4194304>; 1660 cache-line-size = <64>; 1661 cache-sets = <4096>; 1662 }; 1663 }; 1664 1665 psci { 1666 compatible = "arm,psci-1.0"; 1667 status = "okay"; 1668 method = "smc"; 1669 }; 1670 1671 tcu: tcu { 1672 compatible = "nvidia,tegra194-tcu"; 1673 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1674 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1675 mbox-names = "rx", "tx"; 1676 }; 1677 1678 thermal-zones { 1679 cpu { 1680 thermal-sensors = <&{/bpmp/thermal} 1681 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1682 status = "disabled"; 1683 }; 1684 1685 gpu { 1686 thermal-sensors = <&{/bpmp/thermal} 1687 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1688 status = "disabled"; 1689 }; 1690 1691 aux { 1692 thermal-sensors = <&{/bpmp/thermal} 1693 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1694 status = "disabled"; 1695 }; 1696 1697 pllx { 1698 thermal-sensors = <&{/bpmp/thermal} 1699 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1700 status = "disabled"; 1701 }; 1702 1703 ao { 1704 thermal-sensors = <&{/bpmp/thermal} 1705 TEGRA194_BPMP_THERMAL_ZONE_AO>; 1706 status = "disabled"; 1707 }; 1708 1709 tj { 1710 thermal-sensors = <&{/bpmp/thermal} 1711 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1712 status = "disabled"; 1713 }; 1714 }; 1715 1716 timer { 1717 compatible = "arm,armv8-timer"; 1718 interrupts = <GIC_PPI 13 1719 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1720 <GIC_PPI 14 1721 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1722 <GIC_PPI 11 1723 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1724 <GIC_PPI 10 1725 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1726 interrupt-parent = <&gic>; 1727 always-on; 1728 }; 1729}; 1730