1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 pinmux: pinmux@2430000 { 115 compatible = "nvidia,tegra194-pinmux"; 116 reg = <0x0 0x2430000 0x0 0x17000>; 117 status = "okay"; 118 119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 120 clkreq { 121 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 122 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 123 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 124 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 }; 128 }; 129 130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 131 pex_rst { 132 nvidia,pins = "pex_l5_rst_n_pgg1"; 133 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 }; 139 }; 140 }; 141 142 ethernet@2490000 { 143 compatible = "nvidia,tegra194-eqos", 144 "nvidia,tegra186-eqos", 145 "snps,dwc-qos-ethernet-4.10"; 146 reg = <0x0 0x02490000 0x0 0x10000>; 147 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149 <&bpmp TEGRA194_CLK_EQOS_AXI>, 150 <&bpmp TEGRA194_CLK_EQOS_RX>, 151 <&bpmp TEGRA194_CLK_EQOS_TX>, 152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154 resets = <&bpmp TEGRA194_RESET_EQOS>; 155 reset-names = "eqos"; 156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158 interconnect-names = "dma-mem", "write"; 159 iommus = <&smmu TEGRA194_SID_EQOS>; 160 status = "disabled"; 161 162 snps,write-requests = <1>; 163 snps,read-requests = <3>; 164 snps,burst-map = <0x7>; 165 snps,txpbl = <16>; 166 snps,rxpbl = <8>; 167 }; 168 169 gpcdma: dma-controller@2600000 { 170 compatible = "nvidia,tegra194-gpcdma", 171 "nvidia,tegra186-gpcdma"; 172 reg = <0x0 0x2600000 0x0 0x210000>; 173 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174 reset-names = "gpcdma"; 175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207 #dma-cells = <1>; 208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209 dma-coherent; 210 dma-channel-mask = <0xfffffffe>; 211 status = "okay"; 212 }; 213 214 aconnect@2900000 { 215 compatible = "nvidia,tegra194-aconnect", 216 "nvidia,tegra210-aconnect"; 217 clocks = <&bpmp TEGRA194_CLK_APE>, 218 <&bpmp TEGRA194_CLK_APB2APE>; 219 clock-names = "ape", "apb2ape"; 220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 221 status = "disabled"; 222 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 226 227 tegra_ahub: ahub@2900800 { 228 compatible = "nvidia,tegra194-ahub", 229 "nvidia,tegra186-ahub"; 230 reg = <0x0 0x02900800 0x0 0x800>; 231 clocks = <&bpmp TEGRA194_CLK_AHUB>; 232 clock-names = "ahub"; 233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 235 status = "disabled"; 236 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 240 241 tegra_i2s1: i2s@2901000 { 242 compatible = "nvidia,tegra194-i2s", 243 "nvidia,tegra210-i2s"; 244 reg = <0x0 0x2901000 0x0 0x100>; 245 clocks = <&bpmp TEGRA194_CLK_I2S1>, 246 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 247 clock-names = "i2s", "sync_input"; 248 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 249 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 250 assigned-clock-rates = <1536000>; 251 sound-name-prefix = "I2S1"; 252 status = "disabled"; 253 }; 254 255 tegra_i2s2: i2s@2901100 { 256 compatible = "nvidia,tegra194-i2s", 257 "nvidia,tegra210-i2s"; 258 reg = <0x0 0x2901100 0x0 0x100>; 259 clocks = <&bpmp TEGRA194_CLK_I2S2>, 260 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 261 clock-names = "i2s", "sync_input"; 262 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 263 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 264 assigned-clock-rates = <1536000>; 265 sound-name-prefix = "I2S2"; 266 status = "disabled"; 267 }; 268 269 tegra_i2s3: i2s@2901200 { 270 compatible = "nvidia,tegra194-i2s", 271 "nvidia,tegra210-i2s"; 272 reg = <0x0 0x2901200 0x0 0x100>; 273 clocks = <&bpmp TEGRA194_CLK_I2S3>, 274 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 275 clock-names = "i2s", "sync_input"; 276 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 277 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 278 assigned-clock-rates = <1536000>; 279 sound-name-prefix = "I2S3"; 280 status = "disabled"; 281 }; 282 283 tegra_i2s4: i2s@2901300 { 284 compatible = "nvidia,tegra194-i2s", 285 "nvidia,tegra210-i2s"; 286 reg = <0x0 0x2901300 0x0 0x100>; 287 clocks = <&bpmp TEGRA194_CLK_I2S4>, 288 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 289 clock-names = "i2s", "sync_input"; 290 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 291 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 292 assigned-clock-rates = <1536000>; 293 sound-name-prefix = "I2S4"; 294 status = "disabled"; 295 }; 296 297 tegra_i2s5: i2s@2901400 { 298 compatible = "nvidia,tegra194-i2s", 299 "nvidia,tegra210-i2s"; 300 reg = <0x0 0x2901400 0x0 0x100>; 301 clocks = <&bpmp TEGRA194_CLK_I2S5>, 302 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 303 clock-names = "i2s", "sync_input"; 304 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 305 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 306 assigned-clock-rates = <1536000>; 307 sound-name-prefix = "I2S5"; 308 status = "disabled"; 309 }; 310 311 tegra_i2s6: i2s@2901500 { 312 compatible = "nvidia,tegra194-i2s", 313 "nvidia,tegra210-i2s"; 314 reg = <0x0 0x2901500 0x0 0x100>; 315 clocks = <&bpmp TEGRA194_CLK_I2S6>, 316 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 317 clock-names = "i2s", "sync_input"; 318 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 319 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 320 assigned-clock-rates = <1536000>; 321 sound-name-prefix = "I2S6"; 322 status = "disabled"; 323 }; 324 325 tegra_sfc1: sfc@2902000 { 326 compatible = "nvidia,tegra194-sfc", 327 "nvidia,tegra210-sfc"; 328 reg = <0x0 0x2902000 0x0 0x200>; 329 sound-name-prefix = "SFC1"; 330 status = "disabled"; 331 }; 332 333 tegra_sfc2: sfc@2902200 { 334 compatible = "nvidia,tegra194-sfc", 335 "nvidia,tegra210-sfc"; 336 reg = <0x0 0x2902200 0x0 0x200>; 337 sound-name-prefix = "SFC2"; 338 status = "disabled"; 339 }; 340 341 tegra_sfc3: sfc@2902400 { 342 compatible = "nvidia,tegra194-sfc", 343 "nvidia,tegra210-sfc"; 344 reg = <0x0 0x2902400 0x0 0x200>; 345 sound-name-prefix = "SFC3"; 346 status = "disabled"; 347 }; 348 349 tegra_sfc4: sfc@2902600 { 350 compatible = "nvidia,tegra194-sfc", 351 "nvidia,tegra210-sfc"; 352 reg = <0x0 0x2902600 0x0 0x200>; 353 sound-name-prefix = "SFC4"; 354 status = "disabled"; 355 }; 356 357 tegra_amx1: amx@2903000 { 358 compatible = "nvidia,tegra194-amx"; 359 reg = <0x0 0x2903000 0x0 0x100>; 360 sound-name-prefix = "AMX1"; 361 status = "disabled"; 362 }; 363 364 tegra_amx2: amx@2903100 { 365 compatible = "nvidia,tegra194-amx"; 366 reg = <0x0 0x2903100 0x0 0x100>; 367 sound-name-prefix = "AMX2"; 368 status = "disabled"; 369 }; 370 371 tegra_amx3: amx@2903200 { 372 compatible = "nvidia,tegra194-amx"; 373 reg = <0x0 0x2903200 0x0 0x100>; 374 sound-name-prefix = "AMX3"; 375 status = "disabled"; 376 }; 377 378 tegra_amx4: amx@2903300 { 379 compatible = "nvidia,tegra194-amx"; 380 reg = <0x0 0x2903300 0x0 0x100>; 381 sound-name-prefix = "AMX4"; 382 status = "disabled"; 383 }; 384 385 tegra_adx1: adx@2903800 { 386 compatible = "nvidia,tegra194-adx", 387 "nvidia,tegra210-adx"; 388 reg = <0x0 0x2903800 0x0 0x100>; 389 sound-name-prefix = "ADX1"; 390 status = "disabled"; 391 }; 392 393 tegra_adx2: adx@2903900 { 394 compatible = "nvidia,tegra194-adx", 395 "nvidia,tegra210-adx"; 396 reg = <0x0 0x2903900 0x0 0x100>; 397 sound-name-prefix = "ADX2"; 398 status = "disabled"; 399 }; 400 401 tegra_adx3: adx@2903a00 { 402 compatible = "nvidia,tegra194-adx", 403 "nvidia,tegra210-adx"; 404 reg = <0x0 0x2903a00 0x0 0x100>; 405 sound-name-prefix = "ADX3"; 406 status = "disabled"; 407 }; 408 409 tegra_adx4: adx@2903b00 { 410 compatible = "nvidia,tegra194-adx", 411 "nvidia,tegra210-adx"; 412 reg = <0x0 0x2903b00 0x0 0x100>; 413 sound-name-prefix = "ADX4"; 414 status = "disabled"; 415 }; 416 417 tegra_dmic1: dmic@2904000 { 418 compatible = "nvidia,tegra194-dmic", 419 "nvidia,tegra210-dmic"; 420 reg = <0x0 0x2904000 0x0 0x100>; 421 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 422 clock-names = "dmic"; 423 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 424 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 425 assigned-clock-rates = <3072000>; 426 sound-name-prefix = "DMIC1"; 427 status = "disabled"; 428 }; 429 430 tegra_dmic2: dmic@2904100 { 431 compatible = "nvidia,tegra194-dmic", 432 "nvidia,tegra210-dmic"; 433 reg = <0x0 0x2904100 0x0 0x100>; 434 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 435 clock-names = "dmic"; 436 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 437 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 438 assigned-clock-rates = <3072000>; 439 sound-name-prefix = "DMIC2"; 440 status = "disabled"; 441 }; 442 443 tegra_dmic3: dmic@2904200 { 444 compatible = "nvidia,tegra194-dmic", 445 "nvidia,tegra210-dmic"; 446 reg = <0x0 0x2904200 0x0 0x100>; 447 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 448 clock-names = "dmic"; 449 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 450 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 451 assigned-clock-rates = <3072000>; 452 sound-name-prefix = "DMIC3"; 453 status = "disabled"; 454 }; 455 456 tegra_dmic4: dmic@2904300 { 457 compatible = "nvidia,tegra194-dmic", 458 "nvidia,tegra210-dmic"; 459 reg = <0x0 0x2904300 0x0 0x100>; 460 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 461 clock-names = "dmic"; 462 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 463 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 464 assigned-clock-rates = <3072000>; 465 sound-name-prefix = "DMIC4"; 466 status = "disabled"; 467 }; 468 469 tegra_dspk1: dspk@2905000 { 470 compatible = "nvidia,tegra194-dspk", 471 "nvidia,tegra186-dspk"; 472 reg = <0x0 0x2905000 0x0 0x100>; 473 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 474 clock-names = "dspk"; 475 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 476 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 477 assigned-clock-rates = <12288000>; 478 sound-name-prefix = "DSPK1"; 479 status = "disabled"; 480 }; 481 482 tegra_dspk2: dspk@2905100 { 483 compatible = "nvidia,tegra194-dspk", 484 "nvidia,tegra186-dspk"; 485 reg = <0x0 0x2905100 0x0 0x100>; 486 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 487 clock-names = "dspk"; 488 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 489 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 490 assigned-clock-rates = <12288000>; 491 sound-name-prefix = "DSPK2"; 492 status = "disabled"; 493 }; 494 495 tegra_ope1: processing-engine@2908000 { 496 compatible = "nvidia,tegra194-ope", 497 "nvidia,tegra210-ope"; 498 reg = <0x0 0x2908000 0x0 0x100>; 499 sound-name-prefix = "OPE1"; 500 status = "disabled"; 501 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 506 equalizer@2908100 { 507 compatible = "nvidia,tegra194-peq", 508 "nvidia,tegra210-peq"; 509 reg = <0x0 0x2908100 0x0 0x100>; 510 }; 511 512 dynamic-range-compressor@2908200 { 513 compatible = "nvidia,tegra194-mbdrc", 514 "nvidia,tegra210-mbdrc"; 515 reg = <0x0 0x2908200 0x0 0x200>; 516 }; 517 }; 518 519 tegra_mvc1: mvc@290a000 { 520 compatible = "nvidia,tegra194-mvc", 521 "nvidia,tegra210-mvc"; 522 reg = <0x0 0x290a000 0x0 0x200>; 523 sound-name-prefix = "MVC1"; 524 status = "disabled"; 525 }; 526 527 tegra_mvc2: mvc@290a200 { 528 compatible = "nvidia,tegra194-mvc", 529 "nvidia,tegra210-mvc"; 530 reg = <0x0 0x290a200 0x0 0x200>; 531 sound-name-prefix = "MVC2"; 532 status = "disabled"; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra194-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x0 0x290bb00 0x0 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_admaif: admaif@290f000 { 544 compatible = "nvidia,tegra194-admaif", 545 "nvidia,tegra186-admaif"; 546 reg = <0x0 0x0290f000 0x0 0x1000>; 547 dmas = <&adma 1>, <&adma 1>, 548 <&adma 2>, <&adma 2>, 549 <&adma 3>, <&adma 3>, 550 <&adma 4>, <&adma 4>, 551 <&adma 5>, <&adma 5>, 552 <&adma 6>, <&adma 6>, 553 <&adma 7>, <&adma 7>, 554 <&adma 8>, <&adma 8>, 555 <&adma 9>, <&adma 9>, 556 <&adma 10>, <&adma 10>, 557 <&adma 11>, <&adma 11>, 558 <&adma 12>, <&adma 12>, 559 <&adma 13>, <&adma 13>, 560 <&adma 14>, <&adma 14>, 561 <&adma 15>, <&adma 15>, 562 <&adma 16>, <&adma 16>, 563 <&adma 17>, <&adma 17>, 564 <&adma 18>, <&adma 18>, 565 <&adma 19>, <&adma 19>, 566 <&adma 20>, <&adma 20>; 567 dma-names = "rx1", "tx1", 568 "rx2", "tx2", 569 "rx3", "tx3", 570 "rx4", "tx4", 571 "rx5", "tx5", 572 "rx6", "tx6", 573 "rx7", "tx7", 574 "rx8", "tx8", 575 "rx9", "tx9", 576 "rx10", "tx10", 577 "rx11", "tx11", 578 "rx12", "tx12", 579 "rx13", "tx13", 580 "rx14", "tx14", 581 "rx15", "tx15", 582 "rx16", "tx16", 583 "rx17", "tx17", 584 "rx18", "tx18", 585 "rx19", "tx19", 586 "rx20", "tx20"; 587 status = "disabled"; 588 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 589 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 590 interconnect-names = "dma-mem", "write"; 591 iommus = <&smmu TEGRA194_SID_APE>; 592 }; 593 594 tegra_asrc: asrc@2910000 { 595 compatible = "nvidia,tegra194-asrc", 596 "nvidia,tegra186-asrc"; 597 reg = <0x0 0x2910000 0x0 0x2000>; 598 sound-name-prefix = "ASRC1"; 599 status = "disabled"; 600 }; 601 }; 602 603 adma: dma-controller@2930000 { 604 compatible = "nvidia,tegra194-adma", 605 "nvidia,tegra186-adma"; 606 reg = <0x0 0x02930000 0x0 0x20000>; 607 interrupt-parent = <&agic>; 608 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 640 #dma-cells = <1>; 641 clocks = <&bpmp TEGRA194_CLK_AHUB>; 642 clock-names = "d_audio"; 643 status = "disabled"; 644 }; 645 646 agic: interrupt-controller@2a40000 { 647 compatible = "nvidia,tegra194-agic", 648 "nvidia,tegra210-agic"; 649 #interrupt-cells = <3>; 650 interrupt-controller; 651 reg = <0x0 0x02a41000 0x0 0x1000>, 652 <0x0 0x02a42000 0x0 0x2000>; 653 interrupts = <GIC_SPI 145 654 (GIC_CPU_MASK_SIMPLE(4) | 655 IRQ_TYPE_LEVEL_HIGH)>; 656 clocks = <&bpmp TEGRA194_CLK_APE>; 657 clock-names = "clk"; 658 status = "disabled"; 659 }; 660 }; 661 662 mc: memory-controller@2c00000 { 663 compatible = "nvidia,tegra194-mc"; 664 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 665 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 666 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 667 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 668 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 669 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 670 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 671 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 672 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 673 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 674 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 675 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 676 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 677 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 678 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 679 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 680 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 681 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684 "ch11", "ch12", "ch13", "ch14", "ch15"; 685 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686 #interconnect-cells = <1>; 687 status = "disabled"; 688 689 #address-cells = <2>; 690 #size-cells = <2>; 691 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 692 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 693 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694 695 /* 696 * Bit 39 of addresses passing through the memory 697 * controller selects the XBAR format used when memory 698 * is accessed. This is used to transparently access 699 * memory in the XBAR format used by the discrete GPU 700 * (bit 39 set) or Tegra (bit 39 clear). 701 * 702 * As a consequence, the operating system must ensure 703 * that bit 39 is never used implicitly, for example 704 * via an I/O virtual address mapping of an IOMMU. If 705 * devices require access to the XBAR switch, their 706 * drivers must set this bit explicitly. 707 * 708 * Limit the DMA range for memory clients to [38:0]. 709 */ 710 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711 712 emc: external-memory-controller@2c60000 { 713 compatible = "nvidia,tegra194-emc"; 714 reg = <0x0 0x02c60000 0x0 0x90000>, 715 <0x0 0x01780000 0x0 0x80000>; 716 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&bpmp TEGRA194_CLK_EMC>; 718 clock-names = "emc"; 719 720 #interconnect-cells = <0>; 721 722 nvidia,bpmp = <&bpmp>; 723 }; 724 }; 725 726 timer@3010000 { 727 compatible = "nvidia,tegra186-timer"; 728 reg = <0x0 0x03010000 0x0 0x000e0000>; 729 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 739 status = "okay"; 740 }; 741 742 uarta: serial@3100000 { 743 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 744 reg = <0x0 0x03100000 0x0 0x40>; 745 reg-shift = <2>; 746 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&bpmp TEGRA194_CLK_UARTA>; 748 clock-names = "serial"; 749 resets = <&bpmp TEGRA194_RESET_UARTA>; 750 reset-names = "serial"; 751 status = "disabled"; 752 }; 753 754 uartb: serial@3110000 { 755 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 756 reg = <0x0 0x03110000 0x0 0x40>; 757 reg-shift = <2>; 758 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&bpmp TEGRA194_CLK_UARTB>; 760 clock-names = "serial"; 761 resets = <&bpmp TEGRA194_RESET_UARTB>; 762 reset-names = "serial"; 763 status = "disabled"; 764 }; 765 766 uartd: serial@3130000 { 767 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 768 reg = <0x0 0x03130000 0x0 0x40>; 769 reg-shift = <2>; 770 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&bpmp TEGRA194_CLK_UARTD>; 772 clock-names = "serial"; 773 resets = <&bpmp TEGRA194_RESET_UARTD>; 774 reset-names = "serial"; 775 status = "disabled"; 776 }; 777 778 uarte: serial@3140000 { 779 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 780 reg = <0x0 0x03140000 0x0 0x40>; 781 reg-shift = <2>; 782 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&bpmp TEGRA194_CLK_UARTE>; 784 clock-names = "serial"; 785 resets = <&bpmp TEGRA194_RESET_UARTE>; 786 reset-names = "serial"; 787 status = "disabled"; 788 }; 789 790 uartf: serial@3150000 { 791 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 792 reg = <0x0 0x03150000 0x0 0x40>; 793 reg-shift = <2>; 794 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&bpmp TEGRA194_CLK_UARTF>; 796 clock-names = "serial"; 797 resets = <&bpmp TEGRA194_RESET_UARTF>; 798 reset-names = "serial"; 799 status = "disabled"; 800 }; 801 802 gen1_i2c: i2c@3160000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x0 0x03160000 0x0 0x10000>; 805 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&bpmp TEGRA194_CLK_I2C1>; 809 clock-names = "div-clk"; 810 resets = <&bpmp TEGRA194_RESET_I2C1>; 811 reset-names = "i2c"; 812 dmas = <&gpcdma 21>, <&gpcdma 21>; 813 dma-names = "rx", "tx"; 814 status = "disabled"; 815 }; 816 817 uarth: serial@3170000 { 818 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 819 reg = <0x0 0x03170000 0x0 0x40>; 820 reg-shift = <2>; 821 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&bpmp TEGRA194_CLK_UARTH>; 823 clock-names = "serial"; 824 resets = <&bpmp TEGRA194_RESET_UARTH>; 825 reset-names = "serial"; 826 status = "disabled"; 827 }; 828 829 cam_i2c: i2c@3180000 { 830 compatible = "nvidia,tegra194-i2c"; 831 reg = <0x0 0x03180000 0x0 0x10000>; 832 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 clocks = <&bpmp TEGRA194_CLK_I2C3>; 836 clock-names = "div-clk"; 837 resets = <&bpmp TEGRA194_RESET_I2C3>; 838 reset-names = "i2c"; 839 dmas = <&gpcdma 23>, <&gpcdma 23>; 840 dma-names = "rx", "tx"; 841 status = "disabled"; 842 }; 843 844 /* shares pads with dpaux1 */ 845 dp_aux_ch1_i2c: i2c@3190000 { 846 compatible = "nvidia,tegra194-i2c"; 847 reg = <0x0 0x03190000 0x0 0x10000>; 848 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 clocks = <&bpmp TEGRA194_CLK_I2C4>; 852 clock-names = "div-clk"; 853 resets = <&bpmp TEGRA194_RESET_I2C4>; 854 reset-names = "i2c"; 855 pinctrl-0 = <&state_dpaux1_i2c>; 856 pinctrl-1 = <&state_dpaux1_off>; 857 pinctrl-names = "default", "idle"; 858 dmas = <&gpcdma 26>, <&gpcdma 26>; 859 dma-names = "rx", "tx"; 860 status = "disabled"; 861 }; 862 863 /* shares pads with dpaux0 */ 864 dp_aux_ch0_i2c: i2c@31b0000 { 865 compatible = "nvidia,tegra194-i2c"; 866 reg = <0x0 0x031b0000 0x0 0x10000>; 867 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 clocks = <&bpmp TEGRA194_CLK_I2C6>; 871 clock-names = "div-clk"; 872 resets = <&bpmp TEGRA194_RESET_I2C6>; 873 reset-names = "i2c"; 874 pinctrl-0 = <&state_dpaux0_i2c>; 875 pinctrl-1 = <&state_dpaux0_off>; 876 pinctrl-names = "default", "idle"; 877 dmas = <&gpcdma 30>, <&gpcdma 30>; 878 dma-names = "rx", "tx"; 879 status = "disabled"; 880 }; 881 882 /* shares pads with dpaux2 */ 883 dp_aux_ch2_i2c: i2c@31c0000 { 884 compatible = "nvidia,tegra194-i2c"; 885 reg = <0x0 0x031c0000 0x0 0x10000>; 886 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 clocks = <&bpmp TEGRA194_CLK_I2C7>; 890 clock-names = "div-clk"; 891 resets = <&bpmp TEGRA194_RESET_I2C7>; 892 reset-names = "i2c"; 893 pinctrl-0 = <&state_dpaux2_i2c>; 894 pinctrl-1 = <&state_dpaux2_off>; 895 pinctrl-names = "default", "idle"; 896 dmas = <&gpcdma 27>, <&gpcdma 27>; 897 dma-names = "rx", "tx"; 898 status = "disabled"; 899 }; 900 901 /* shares pads with dpaux3 */ 902 dp_aux_ch3_i2c: i2c@31e0000 { 903 compatible = "nvidia,tegra194-i2c"; 904 reg = <0x0 0x031e0000 0x0 0x10000>; 905 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 clocks = <&bpmp TEGRA194_CLK_I2C9>; 909 clock-names = "div-clk"; 910 resets = <&bpmp TEGRA194_RESET_I2C9>; 911 reset-names = "i2c"; 912 pinctrl-0 = <&state_dpaux3_i2c>; 913 pinctrl-1 = <&state_dpaux3_off>; 914 pinctrl-names = "default", "idle"; 915 dmas = <&gpcdma 31>, <&gpcdma 31>; 916 dma-names = "rx", "tx"; 917 status = "disabled"; 918 }; 919 920 spi@3270000 { 921 compatible = "nvidia,tegra194-qspi"; 922 reg = <0x0 0x3270000 0x0 0x1000>; 923 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 927 <&bpmp TEGRA194_CLK_QSPI0_PM>; 928 clock-names = "qspi", "qspi_out"; 929 resets = <&bpmp TEGRA194_RESET_QSPI0>; 930 status = "disabled"; 931 }; 932 933 pwm1: pwm@3280000 { 934 compatible = "nvidia,tegra194-pwm", 935 "nvidia,tegra186-pwm"; 936 reg = <0x0 0x3280000 0x0 0x10000>; 937 clocks = <&bpmp TEGRA194_CLK_PWM1>; 938 resets = <&bpmp TEGRA194_RESET_PWM1>; 939 reset-names = "pwm"; 940 status = "disabled"; 941 #pwm-cells = <2>; 942 }; 943 944 pwm2: pwm@3290000 { 945 compatible = "nvidia,tegra194-pwm", 946 "nvidia,tegra186-pwm"; 947 reg = <0x0 0x3290000 0x0 0x10000>; 948 clocks = <&bpmp TEGRA194_CLK_PWM2>; 949 resets = <&bpmp TEGRA194_RESET_PWM2>; 950 reset-names = "pwm"; 951 status = "disabled"; 952 #pwm-cells = <2>; 953 }; 954 955 pwm3: pwm@32a0000 { 956 compatible = "nvidia,tegra194-pwm", 957 "nvidia,tegra186-pwm"; 958 reg = <0x0 0x32a0000 0x0 0x10000>; 959 clocks = <&bpmp TEGRA194_CLK_PWM3>; 960 resets = <&bpmp TEGRA194_RESET_PWM3>; 961 reset-names = "pwm"; 962 status = "disabled"; 963 #pwm-cells = <2>; 964 }; 965 966 pwm5: pwm@32c0000 { 967 compatible = "nvidia,tegra194-pwm", 968 "nvidia,tegra186-pwm"; 969 reg = <0x0 0x32c0000 0x0 0x10000>; 970 clocks = <&bpmp TEGRA194_CLK_PWM5>; 971 resets = <&bpmp TEGRA194_RESET_PWM5>; 972 reset-names = "pwm"; 973 status = "disabled"; 974 #pwm-cells = <2>; 975 }; 976 977 pwm6: pwm@32d0000 { 978 compatible = "nvidia,tegra194-pwm", 979 "nvidia,tegra186-pwm"; 980 reg = <0x0 0x32d0000 0x0 0x10000>; 981 clocks = <&bpmp TEGRA194_CLK_PWM6>; 982 resets = <&bpmp TEGRA194_RESET_PWM6>; 983 reset-names = "pwm"; 984 status = "disabled"; 985 #pwm-cells = <2>; 986 }; 987 988 pwm7: pwm@32e0000 { 989 compatible = "nvidia,tegra194-pwm", 990 "nvidia,tegra186-pwm"; 991 reg = <0x0 0x32e0000 0x0 0x10000>; 992 clocks = <&bpmp TEGRA194_CLK_PWM7>; 993 resets = <&bpmp TEGRA194_RESET_PWM7>; 994 reset-names = "pwm"; 995 status = "disabled"; 996 #pwm-cells = <2>; 997 }; 998 999 pwm8: pwm@32f0000 { 1000 compatible = "nvidia,tegra194-pwm", 1001 "nvidia,tegra186-pwm"; 1002 reg = <0x0 0x32f0000 0x0 0x10000>; 1003 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1004 resets = <&bpmp TEGRA194_RESET_PWM8>; 1005 reset-names = "pwm"; 1006 status = "disabled"; 1007 #pwm-cells = <2>; 1008 }; 1009 1010 spi@3300000 { 1011 compatible = "nvidia,tegra194-qspi"; 1012 reg = <0x0 0x3300000 0x0 0x1000>; 1013 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1017 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1018 clock-names = "qspi", "qspi_out"; 1019 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1020 status = "disabled"; 1021 }; 1022 1023 sdmmc1: mmc@3400000 { 1024 compatible = "nvidia,tegra194-sdhci"; 1025 reg = <0x0 0x03400000 0x0 0x10000>; 1026 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1028 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1029 clock-names = "sdhci", "tmclk"; 1030 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1031 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1032 assigned-clock-parents = 1033 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1034 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1035 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1036 reset-names = "sdhci"; 1037 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1038 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1039 interconnect-names = "dma-mem", "write"; 1040 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1041 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1042 pinctrl-0 = <&sdmmc1_3v3>; 1043 pinctrl-1 = <&sdmmc1_1v8>; 1044 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1045 <0x07>; 1046 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1047 <0x07>; 1048 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1049 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1050 <0x07>; 1051 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1052 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1053 nvidia,default-tap = <0x9>; 1054 nvidia,default-trim = <0x5>; 1055 sd-uhs-sdr25; 1056 sd-uhs-sdr50; 1057 sd-uhs-ddr50; 1058 sd-uhs-sdr104; 1059 status = "disabled"; 1060 }; 1061 1062 sdmmc3: mmc@3440000 { 1063 compatible = "nvidia,tegra194-sdhci"; 1064 reg = <0x0 0x03440000 0x0 0x10000>; 1065 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1067 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1068 clock-names = "sdhci", "tmclk"; 1069 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1070 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1071 assigned-clock-parents = 1072 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1073 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1074 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1075 reset-names = "sdhci"; 1076 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1077 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1078 interconnect-names = "dma-mem", "write"; 1079 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1080 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1081 pinctrl-0 = <&sdmmc3_3v3>; 1082 pinctrl-1 = <&sdmmc3_1v8>; 1083 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1084 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1085 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1086 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1087 <0x07>; 1088 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1089 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1090 <0x07>; 1091 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1092 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1093 nvidia,default-tap = <0x9>; 1094 nvidia,default-trim = <0x5>; 1095 sd-uhs-sdr25; 1096 sd-uhs-sdr50; 1097 sd-uhs-ddr50; 1098 sd-uhs-sdr104; 1099 status = "disabled"; 1100 }; 1101 1102 sdmmc4: mmc@3460000 { 1103 compatible = "nvidia,tegra194-sdhci"; 1104 reg = <0x0 0x03460000 0x0 0x10000>; 1105 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1107 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1108 clock-names = "sdhci", "tmclk"; 1109 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1110 <&bpmp TEGRA194_CLK_PLLC4>; 1111 assigned-clock-parents = 1112 <&bpmp TEGRA194_CLK_PLLC4>; 1113 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1114 reset-names = "sdhci"; 1115 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1116 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1117 interconnect-names = "dma-mem", "write"; 1118 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1119 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1120 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1121 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1122 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1123 <0x0a>; 1124 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1125 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1126 <0x0a>; 1127 nvidia,default-tap = <0x8>; 1128 nvidia,default-trim = <0x14>; 1129 nvidia,dqs-trim = <40>; 1130 cap-mmc-highspeed; 1131 mmc-ddr-1_8v; 1132 mmc-hs200-1_8v; 1133 mmc-hs400-1_8v; 1134 mmc-hs400-enhanced-strobe; 1135 supports-cqe; 1136 status = "disabled"; 1137 }; 1138 1139 hda@3510000 { 1140 compatible = "nvidia,tegra194-hda"; 1141 reg = <0x0 0x3510000 0x0 0x10000>; 1142 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&bpmp TEGRA194_CLK_HDA>, 1144 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1145 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1146 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1147 resets = <&bpmp TEGRA194_RESET_HDA>, 1148 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1149 reset-names = "hda", "hda2hdmi"; 1150 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1151 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1152 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1153 interconnect-names = "dma-mem", "write"; 1154 iommus = <&smmu TEGRA194_SID_HDA>; 1155 status = "disabled"; 1156 }; 1157 1158 xusb_padctl: padctl@3520000 { 1159 compatible = "nvidia,tegra194-xusb-padctl"; 1160 reg = <0x0 0x03520000 0x0 0x1000>, 1161 <0x0 0x03540000 0x0 0x1000>; 1162 reg-names = "padctl", "ao"; 1163 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1164 1165 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1166 reset-names = "padctl"; 1167 1168 status = "disabled"; 1169 1170 pads { 1171 usb2 { 1172 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1173 clock-names = "trk"; 1174 1175 lanes { 1176 usb2-0 { 1177 nvidia,function = "xusb"; 1178 status = "disabled"; 1179 #phy-cells = <0>; 1180 }; 1181 1182 usb2-1 { 1183 nvidia,function = "xusb"; 1184 status = "disabled"; 1185 #phy-cells = <0>; 1186 }; 1187 1188 usb2-2 { 1189 nvidia,function = "xusb"; 1190 status = "disabled"; 1191 #phy-cells = <0>; 1192 }; 1193 1194 usb2-3 { 1195 nvidia,function = "xusb"; 1196 status = "disabled"; 1197 #phy-cells = <0>; 1198 }; 1199 }; 1200 }; 1201 1202 usb3 { 1203 lanes { 1204 usb3-0 { 1205 nvidia,function = "xusb"; 1206 status = "disabled"; 1207 #phy-cells = <0>; 1208 }; 1209 1210 usb3-1 { 1211 nvidia,function = "xusb"; 1212 status = "disabled"; 1213 #phy-cells = <0>; 1214 }; 1215 1216 usb3-2 { 1217 nvidia,function = "xusb"; 1218 status = "disabled"; 1219 #phy-cells = <0>; 1220 }; 1221 1222 usb3-3 { 1223 nvidia,function = "xusb"; 1224 status = "disabled"; 1225 #phy-cells = <0>; 1226 }; 1227 }; 1228 }; 1229 }; 1230 1231 ports { 1232 usb2-0 { 1233 status = "disabled"; 1234 }; 1235 1236 usb2-1 { 1237 status = "disabled"; 1238 }; 1239 1240 usb2-2 { 1241 status = "disabled"; 1242 }; 1243 1244 usb2-3 { 1245 status = "disabled"; 1246 }; 1247 1248 usb3-0 { 1249 status = "disabled"; 1250 }; 1251 1252 usb3-1 { 1253 status = "disabled"; 1254 }; 1255 1256 usb3-2 { 1257 status = "disabled"; 1258 }; 1259 1260 usb3-3 { 1261 status = "disabled"; 1262 }; 1263 }; 1264 }; 1265 1266 usb@3550000 { 1267 compatible = "nvidia,tegra194-xudc"; 1268 reg = <0x0 0x03550000 0x0 0x8000>, 1269 <0x0 0x03558000 0x0 0x1000>; 1270 reg-names = "base", "fpci"; 1271 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1273 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1274 <&bpmp TEGRA194_CLK_XUSB_SS>, 1275 <&bpmp TEGRA194_CLK_XUSB_FS>; 1276 clock-names = "dev", "ss", "ss_src", "fs_src"; 1277 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1278 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1279 interconnect-names = "dma-mem", "write"; 1280 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1281 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1282 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1283 power-domain-names = "dev", "ss"; 1284 nvidia,xusb-padctl = <&xusb_padctl>; 1285 dma-coherent; 1286 status = "disabled"; 1287 }; 1288 1289 usb@3610000 { 1290 compatible = "nvidia,tegra194-xusb"; 1291 reg = <0x0 0x03610000 0x0 0x40000>, 1292 <0x0 0x03600000 0x0 0x10000>; 1293 reg-names = "hcd", "fpci"; 1294 1295 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1297 1298 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1299 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1300 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1301 <&bpmp TEGRA194_CLK_XUSB_SS>, 1302 <&bpmp TEGRA194_CLK_CLK_M>, 1303 <&bpmp TEGRA194_CLK_XUSB_FS>, 1304 <&bpmp TEGRA194_CLK_UTMIPLL>, 1305 <&bpmp TEGRA194_CLK_CLK_M>, 1306 <&bpmp TEGRA194_CLK_PLLE>; 1307 clock-names = "xusb_host", "xusb_falcon_src", 1308 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1309 "xusb_fs_src", "pll_u_480m", "clk_m", 1310 "pll_e"; 1311 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1312 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1313 interconnect-names = "dma-mem", "write"; 1314 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1315 1316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1317 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1318 power-domain-names = "xusb_host", "xusb_ss"; 1319 1320 nvidia,xusb-padctl = <&xusb_padctl>; 1321 status = "disabled"; 1322 }; 1323 1324 fuse@3820000 { 1325 compatible = "nvidia,tegra194-efuse"; 1326 reg = <0x0 0x03820000 0x0 0x10000>; 1327 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1328 clock-names = "fuse"; 1329 }; 1330 1331 gic: interrupt-controller@3881000 { 1332 compatible = "arm,gic-400"; 1333 #interrupt-cells = <3>; 1334 interrupt-controller; 1335 reg = <0x0 0x03881000 0x0 0x1000>, 1336 <0x0 0x03882000 0x0 0x2000>, 1337 <0x0 0x03884000 0x0 0x2000>, 1338 <0x0 0x03886000 0x0 0x2000>; 1339 interrupts = <GIC_PPI 9 1340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1341 interrupt-parent = <&gic>; 1342 }; 1343 1344 cec@3960000 { 1345 compatible = "nvidia,tegra194-cec"; 1346 reg = <0x0 0x03960000 0x0 0x10000>; 1347 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&bpmp TEGRA194_CLK_CEC>; 1349 clock-names = "cec"; 1350 status = "disabled"; 1351 }; 1352 1353 hte_lic: hardware-timestamp@3aa0000 { 1354 compatible = "nvidia,tegra194-gte-lic"; 1355 reg = <0x0 0x3aa0000 0x0 0x10000>; 1356 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1357 nvidia,int-threshold = <1>; 1358 nvidia,slices = <11>; 1359 #timestamp-cells = <1>; 1360 status = "okay"; 1361 }; 1362 1363 hsp_top0: hsp@3c00000 { 1364 compatible = "nvidia,tegra194-hsp"; 1365 reg = <0x0 0x03c00000 0x0 0xa0000>; 1366 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1375 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1376 "shared3", "shared4", "shared5", "shared6", 1377 "shared7"; 1378 #mbox-cells = <2>; 1379 }; 1380 1381 p2u_hsio_0: phy@3e10000 { 1382 compatible = "nvidia,tegra194-p2u"; 1383 reg = <0x0 0x03e10000 0x0 0x10000>; 1384 reg-names = "ctl"; 1385 1386 #phy-cells = <0>; 1387 }; 1388 1389 p2u_hsio_1: phy@3e20000 { 1390 compatible = "nvidia,tegra194-p2u"; 1391 reg = <0x0 0x03e20000 0x0 0x10000>; 1392 reg-names = "ctl"; 1393 1394 #phy-cells = <0>; 1395 }; 1396 1397 p2u_hsio_2: phy@3e30000 { 1398 compatible = "nvidia,tegra194-p2u"; 1399 reg = <0x0 0x03e30000 0x0 0x10000>; 1400 reg-names = "ctl"; 1401 1402 #phy-cells = <0>; 1403 }; 1404 1405 p2u_hsio_3: phy@3e40000 { 1406 compatible = "nvidia,tegra194-p2u"; 1407 reg = <0x0 0x03e40000 0x0 0x10000>; 1408 reg-names = "ctl"; 1409 1410 #phy-cells = <0>; 1411 }; 1412 1413 p2u_hsio_4: phy@3e50000 { 1414 compatible = "nvidia,tegra194-p2u"; 1415 reg = <0x0 0x03e50000 0x0 0x10000>; 1416 reg-names = "ctl"; 1417 1418 #phy-cells = <0>; 1419 }; 1420 1421 p2u_hsio_5: phy@3e60000 { 1422 compatible = "nvidia,tegra194-p2u"; 1423 reg = <0x0 0x03e60000 0x0 0x10000>; 1424 reg-names = "ctl"; 1425 1426 #phy-cells = <0>; 1427 }; 1428 1429 p2u_hsio_6: phy@3e70000 { 1430 compatible = "nvidia,tegra194-p2u"; 1431 reg = <0x0 0x03e70000 0x0 0x10000>; 1432 reg-names = "ctl"; 1433 1434 #phy-cells = <0>; 1435 }; 1436 1437 p2u_hsio_7: phy@3e80000 { 1438 compatible = "nvidia,tegra194-p2u"; 1439 reg = <0x0 0x03e80000 0x0 0x10000>; 1440 reg-names = "ctl"; 1441 1442 #phy-cells = <0>; 1443 }; 1444 1445 p2u_hsio_8: phy@3e90000 { 1446 compatible = "nvidia,tegra194-p2u"; 1447 reg = <0x0 0x03e90000 0x0 0x10000>; 1448 reg-names = "ctl"; 1449 1450 #phy-cells = <0>; 1451 }; 1452 1453 p2u_hsio_9: phy@3ea0000 { 1454 compatible = "nvidia,tegra194-p2u"; 1455 reg = <0x0 0x03ea0000 0x0 0x10000>; 1456 reg-names = "ctl"; 1457 1458 #phy-cells = <0>; 1459 }; 1460 1461 p2u_nvhs_0: phy@3eb0000 { 1462 compatible = "nvidia,tegra194-p2u"; 1463 reg = <0x0 0x03eb0000 0x0 0x10000>; 1464 reg-names = "ctl"; 1465 1466 #phy-cells = <0>; 1467 }; 1468 1469 p2u_nvhs_1: phy@3ec0000 { 1470 compatible = "nvidia,tegra194-p2u"; 1471 reg = <0x0 0x03ec0000 0x0 0x10000>; 1472 reg-names = "ctl"; 1473 1474 #phy-cells = <0>; 1475 }; 1476 1477 p2u_nvhs_2: phy@3ed0000 { 1478 compatible = "nvidia,tegra194-p2u"; 1479 reg = <0x0 0x03ed0000 0x0 0x10000>; 1480 reg-names = "ctl"; 1481 1482 #phy-cells = <0>; 1483 }; 1484 1485 p2u_nvhs_3: phy@3ee0000 { 1486 compatible = "nvidia,tegra194-p2u"; 1487 reg = <0x0 0x03ee0000 0x0 0x10000>; 1488 reg-names = "ctl"; 1489 1490 #phy-cells = <0>; 1491 }; 1492 1493 p2u_nvhs_4: phy@3ef0000 { 1494 compatible = "nvidia,tegra194-p2u"; 1495 reg = <0x0 0x03ef0000 0x0 0x10000>; 1496 reg-names = "ctl"; 1497 1498 #phy-cells = <0>; 1499 }; 1500 1501 p2u_nvhs_5: phy@3f00000 { 1502 compatible = "nvidia,tegra194-p2u"; 1503 reg = <0x0 0x03f00000 0x0 0x10000>; 1504 reg-names = "ctl"; 1505 1506 #phy-cells = <0>; 1507 }; 1508 1509 p2u_nvhs_6: phy@3f10000 { 1510 compatible = "nvidia,tegra194-p2u"; 1511 reg = <0x0 0x03f10000 0x0 0x10000>; 1512 reg-names = "ctl"; 1513 1514 #phy-cells = <0>; 1515 }; 1516 1517 p2u_nvhs_7: phy@3f20000 { 1518 compatible = "nvidia,tegra194-p2u"; 1519 reg = <0x0 0x03f20000 0x0 0x10000>; 1520 reg-names = "ctl"; 1521 1522 #phy-cells = <0>; 1523 }; 1524 1525 p2u_hsio_10: phy@3f30000 { 1526 compatible = "nvidia,tegra194-p2u"; 1527 reg = <0x0 0x03f30000 0x0 0x10000>; 1528 reg-names = "ctl"; 1529 1530 #phy-cells = <0>; 1531 }; 1532 1533 p2u_hsio_11: phy@3f40000 { 1534 compatible = "nvidia,tegra194-p2u"; 1535 reg = <0x0 0x03f40000 0x0 0x10000>; 1536 reg-names = "ctl"; 1537 1538 #phy-cells = <0>; 1539 }; 1540 1541 sce-noc@b600000 { 1542 compatible = "nvidia,tegra194-sce-noc"; 1543 reg = <0x0 0xb600000 0x0 0x1000>; 1544 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1546 nvidia,axi2apb = <&axi2apb>; 1547 nvidia,apbmisc = <&apbmisc>; 1548 status = "okay"; 1549 }; 1550 1551 rce-noc@be00000 { 1552 compatible = "nvidia,tegra194-rce-noc"; 1553 reg = <0x0 0xbe00000 0x0 0x1000>; 1554 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1556 nvidia,axi2apb = <&axi2apb>; 1557 nvidia,apbmisc = <&apbmisc>; 1558 status = "okay"; 1559 }; 1560 1561 hsp_aon: hsp@c150000 { 1562 compatible = "nvidia,tegra194-hsp"; 1563 reg = <0x0 0x0c150000 0x0 0x90000>; 1564 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1568 /* 1569 * Shared interrupt 0 is routed only to AON/SPE, so 1570 * we only have 4 shared interrupts for the CCPLEX. 1571 */ 1572 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1573 #mbox-cells = <2>; 1574 }; 1575 1576 hte_aon: hardware-timestamp@c1e0000 { 1577 compatible = "nvidia,tegra194-gte-aon"; 1578 reg = <0x0 0xc1e0000 0x0 0x10000>; 1579 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1580 nvidia,int-threshold = <1>; 1581 nvidia,slices = <3>; 1582 #timestamp-cells = <1>; 1583 status = "okay"; 1584 }; 1585 1586 gen2_i2c: i2c@c240000 { 1587 compatible = "nvidia,tegra194-i2c"; 1588 reg = <0x0 0x0c240000 0x0 0x10000>; 1589 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1593 clock-names = "div-clk"; 1594 resets = <&bpmp TEGRA194_RESET_I2C2>; 1595 reset-names = "i2c"; 1596 dmas = <&gpcdma 22>, <&gpcdma 22>; 1597 dma-names = "rx", "tx"; 1598 status = "disabled"; 1599 }; 1600 1601 gen8_i2c: i2c@c250000 { 1602 compatible = "nvidia,tegra194-i2c"; 1603 reg = <0x0 0x0c250000 0x0 0x10000>; 1604 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1608 clock-names = "div-clk"; 1609 resets = <&bpmp TEGRA194_RESET_I2C8>; 1610 reset-names = "i2c"; 1611 dmas = <&gpcdma 0>, <&gpcdma 0>; 1612 dma-names = "rx", "tx"; 1613 status = "disabled"; 1614 }; 1615 1616 uartc: serial@c280000 { 1617 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1618 reg = <0x0 0x0c280000 0x0 0x40>; 1619 reg-shift = <2>; 1620 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1621 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1622 clock-names = "serial"; 1623 resets = <&bpmp TEGRA194_RESET_UARTC>; 1624 reset-names = "serial"; 1625 status = "disabled"; 1626 }; 1627 1628 uartg: serial@c290000 { 1629 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1630 reg = <0x0 0x0c290000 0x0 0x40>; 1631 reg-shift = <2>; 1632 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1634 clock-names = "serial"; 1635 resets = <&bpmp TEGRA194_RESET_UARTG>; 1636 reset-names = "serial"; 1637 status = "disabled"; 1638 }; 1639 1640 rtc: rtc@c2a0000 { 1641 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1642 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1643 interrupt-parent = <&pmc>; 1644 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1645 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1646 clock-names = "rtc"; 1647 status = "disabled"; 1648 }; 1649 1650 gpio_aon: gpio@c2f0000 { 1651 compatible = "nvidia,tegra194-gpio-aon"; 1652 reg-names = "security", "gpio"; 1653 reg = <0x0 0xc2f0000 0x0 0x1000>, 1654 <0x0 0xc2f1000 0x0 0x1000>; 1655 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1659 gpio-controller; 1660 #gpio-cells = <2>; 1661 interrupt-controller; 1662 #interrupt-cells = <2>; 1663 gpio-ranges = <&pinmux_aon 0 0 30>; 1664 }; 1665 1666 pinmux_aon: pinmux@c300000 { 1667 compatible = "nvidia,tegra194-pinmux-aon"; 1668 reg = <0x0 0xc300000 0x0 0x4000>; 1669 1670 status = "okay"; 1671 }; 1672 1673 pwm4: pwm@c340000 { 1674 compatible = "nvidia,tegra194-pwm", 1675 "nvidia,tegra186-pwm"; 1676 reg = <0x0 0xc340000 0x0 0x10000>; 1677 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1678 resets = <&bpmp TEGRA194_RESET_PWM4>; 1679 reset-names = "pwm"; 1680 status = "disabled"; 1681 #pwm-cells = <2>; 1682 }; 1683 1684 pmc: pmc@c360000 { 1685 compatible = "nvidia,tegra194-pmc"; 1686 reg = <0x0 0x0c360000 0x0 0x10000>, 1687 <0x0 0x0c370000 0x0 0x10000>, 1688 <0x0 0x0c380000 0x0 0x10000>, 1689 <0x0 0x0c390000 0x0 0x10000>, 1690 <0x0 0x0c3a0000 0x0 0x10000>; 1691 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1692 1693 #interrupt-cells = <2>; 1694 interrupt-controller; 1695 1696 sdmmc1_1v8: sdmmc1-1v8 { 1697 pins = "sdmmc1-hv"; 1698 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1699 }; 1700 1701 sdmmc1_3v3: sdmmc1-3v3 { 1702 pins = "sdmmc1-hv"; 1703 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1704 }; 1705 1706 sdmmc3_1v8: sdmmc3-1v8 { 1707 pins = "sdmmc3-hv"; 1708 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1709 }; 1710 1711 sdmmc3_3v3: sdmmc3-3v3 { 1712 pins = "sdmmc3-hv"; 1713 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1714 }; 1715 }; 1716 1717 aon-noc@c600000 { 1718 compatible = "nvidia,tegra194-aon-noc"; 1719 reg = <0x0 0xc600000 0x0 0x1000>; 1720 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1722 nvidia,apbmisc = <&apbmisc>; 1723 status = "okay"; 1724 }; 1725 1726 bpmp-noc@d600000 { 1727 compatible = "nvidia,tegra194-bpmp-noc"; 1728 reg = <0x0 0xd600000 0x0 0x1000>; 1729 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1731 nvidia,axi2apb = <&axi2apb>; 1732 nvidia,apbmisc = <&apbmisc>; 1733 status = "okay"; 1734 }; 1735 1736 iommu@10000000 { 1737 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1738 reg = <0x0 0x10000000 0x0 0x800000>; 1739 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1804 stream-match-mask = <0x7f80>; 1805 #global-interrupts = <1>; 1806 #iommu-cells = <1>; 1807 1808 nvidia,memory-controller = <&mc>; 1809 status = "disabled"; 1810 }; 1811 1812 smmu: iommu@12000000 { 1813 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1814 reg = <0x0 0x12000000 0x0 0x800000>, 1815 <0x0 0x11000000 0x0 0x800000>; 1816 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1882 stream-match-mask = <0x7f80>; 1883 #global-interrupts = <2>; 1884 #iommu-cells = <1>; 1885 1886 nvidia,memory-controller = <&mc>; 1887 status = "okay"; 1888 }; 1889 1890 host1x@13e00000 { 1891 compatible = "nvidia,tegra194-host1x"; 1892 reg = <0x0 0x13e00000 0x0 0x10000>, 1893 <0x0 0x13e10000 0x0 0x10000>; 1894 reg-names = "hypervisor", "vm"; 1895 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1897 interrupt-names = "syncpt", "host1x"; 1898 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1899 clock-names = "host1x"; 1900 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1901 reset-names = "host1x"; 1902 1903 #address-cells = <2>; 1904 #size-cells = <2>; 1905 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1906 1907 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1908 interconnect-names = "dma-mem"; 1909 iommus = <&smmu TEGRA194_SID_HOST1X>; 1910 dma-coherent; 1911 1912 /* Context isolation domains */ 1913 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1914 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1915 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1916 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1917 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1918 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1919 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1920 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1921 1922 nvdec@15140000 { 1923 compatible = "nvidia,tegra194-nvdec"; 1924 reg = <0x0 0x15140000 0x0 0x00040000>; 1925 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1926 clock-names = "nvdec"; 1927 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1928 reset-names = "nvdec"; 1929 1930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1931 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1932 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1933 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1934 interconnect-names = "dma-mem", "read-1", "write"; 1935 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1936 dma-coherent; 1937 1938 nvidia,host1x-class = <0xf5>; 1939 }; 1940 1941 display-hub@15200000 { 1942 compatible = "nvidia,tegra194-display"; 1943 reg = <0x0 0x15200000 0x0 0x00040000>; 1944 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1945 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1946 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1947 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1948 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1949 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1950 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1951 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1952 "wgrp3", "wgrp4", "wgrp5"; 1953 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1954 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1955 clock-names = "disp", "hub"; 1956 status = "disabled"; 1957 1958 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1959 1960 #address-cells = <2>; 1961 #size-cells = <2>; 1962 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1963 1964 display@15200000 { 1965 compatible = "nvidia,tegra194-dc"; 1966 reg = <0x0 0x15200000 0x0 0x10000>; 1967 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1969 clock-names = "dc"; 1970 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1971 reset-names = "dc"; 1972 1973 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1974 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1975 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1976 interconnect-names = "dma-mem", "read-1"; 1977 1978 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1979 nvidia,head = <0>; 1980 }; 1981 1982 display@15210000 { 1983 compatible = "nvidia,tegra194-dc"; 1984 reg = <0x0 0x15210000 0x0 0x10000>; 1985 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1986 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1987 clock-names = "dc"; 1988 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1989 reset-names = "dc"; 1990 1991 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1992 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1993 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1994 interconnect-names = "dma-mem", "read-1"; 1995 1996 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1997 nvidia,head = <1>; 1998 }; 1999 2000 display@15220000 { 2001 compatible = "nvidia,tegra194-dc"; 2002 reg = <0x0 0x15220000 0x0 0x10000>; 2003 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2004 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2005 clock-names = "dc"; 2006 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2007 reset-names = "dc"; 2008 2009 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2010 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2011 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2012 interconnect-names = "dma-mem", "read-1"; 2013 2014 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2015 nvidia,head = <2>; 2016 }; 2017 2018 display@15230000 { 2019 compatible = "nvidia,tegra194-dc"; 2020 reg = <0x0 0x15230000 0x0 0x10000>; 2021 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2022 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2023 clock-names = "dc"; 2024 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2025 reset-names = "dc"; 2026 2027 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2028 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2029 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2030 interconnect-names = "dma-mem", "read-1"; 2031 2032 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2033 nvidia,head = <3>; 2034 }; 2035 }; 2036 2037 vic@15340000 { 2038 compatible = "nvidia,tegra194-vic"; 2039 reg = <0x0 0x15340000 0x0 0x00040000>; 2040 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2041 clocks = <&bpmp TEGRA194_CLK_VIC>; 2042 clock-names = "vic"; 2043 resets = <&bpmp TEGRA194_RESET_VIC>; 2044 reset-names = "vic"; 2045 2046 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2047 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2048 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2049 interconnect-names = "dma-mem", "write"; 2050 iommus = <&smmu TEGRA194_SID_VIC>; 2051 dma-coherent; 2052 }; 2053 2054 nvjpg@15380000 { 2055 compatible = "nvidia,tegra194-nvjpg"; 2056 reg = <0x0 0x15380000 0x0 0x40000>; 2057 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2058 clock-names = "nvjpg"; 2059 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2060 reset-names = "nvjpg"; 2061 2062 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2063 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2064 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2065 interconnect-names = "dma-mem", "write"; 2066 iommus = <&smmu TEGRA194_SID_NVJPG>; 2067 dma-coherent; 2068 }; 2069 2070 nvdec@15480000 { 2071 compatible = "nvidia,tegra194-nvdec"; 2072 reg = <0x0 0x15480000 0x0 0x00040000>; 2073 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2074 clock-names = "nvdec"; 2075 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2076 reset-names = "nvdec"; 2077 2078 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2079 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2080 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2081 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2082 interconnect-names = "dma-mem", "read-1", "write"; 2083 iommus = <&smmu TEGRA194_SID_NVDEC>; 2084 dma-coherent; 2085 2086 nvidia,host1x-class = <0xf0>; 2087 }; 2088 2089 nvenc@154c0000 { 2090 compatible = "nvidia,tegra194-nvenc"; 2091 reg = <0x0 0x154c0000 0x0 0x40000>; 2092 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2093 clock-names = "nvenc"; 2094 resets = <&bpmp TEGRA194_RESET_NVENC>; 2095 reset-names = "nvenc"; 2096 2097 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2098 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2099 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2100 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2101 interconnect-names = "dma-mem", "read-1", "write"; 2102 iommus = <&smmu TEGRA194_SID_NVENC>; 2103 dma-coherent; 2104 2105 nvidia,host1x-class = <0x21>; 2106 }; 2107 2108 dpaux0: dpaux@155c0000 { 2109 compatible = "nvidia,tegra194-dpaux"; 2110 reg = <0x0 0x155c0000 0x0 0x10000>; 2111 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2112 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2113 <&bpmp TEGRA194_CLK_PLLDP>; 2114 clock-names = "dpaux", "parent"; 2115 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2116 reset-names = "dpaux"; 2117 status = "disabled"; 2118 2119 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2120 2121 state_dpaux0_aux: pinmux-aux { 2122 groups = "dpaux-io"; 2123 function = "aux"; 2124 }; 2125 2126 state_dpaux0_i2c: pinmux-i2c { 2127 groups = "dpaux-io"; 2128 function = "i2c"; 2129 }; 2130 2131 state_dpaux0_off: pinmux-off { 2132 groups = "dpaux-io"; 2133 function = "off"; 2134 }; 2135 2136 i2c-bus { 2137 #address-cells = <1>; 2138 #size-cells = <0>; 2139 }; 2140 }; 2141 2142 dpaux1: dpaux@155d0000 { 2143 compatible = "nvidia,tegra194-dpaux"; 2144 reg = <0x0 0x155d0000 0x0 0x10000>; 2145 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2146 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2147 <&bpmp TEGRA194_CLK_PLLDP>; 2148 clock-names = "dpaux", "parent"; 2149 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2150 reset-names = "dpaux"; 2151 status = "disabled"; 2152 2153 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2154 2155 state_dpaux1_aux: pinmux-aux { 2156 groups = "dpaux-io"; 2157 function = "aux"; 2158 }; 2159 2160 state_dpaux1_i2c: pinmux-i2c { 2161 groups = "dpaux-io"; 2162 function = "i2c"; 2163 }; 2164 2165 state_dpaux1_off: pinmux-off { 2166 groups = "dpaux-io"; 2167 function = "off"; 2168 }; 2169 2170 i2c-bus { 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 }; 2174 }; 2175 2176 dpaux2: dpaux@155e0000 { 2177 compatible = "nvidia,tegra194-dpaux"; 2178 reg = <0x0 0x155e0000 0x0 0x10000>; 2179 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2180 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2181 <&bpmp TEGRA194_CLK_PLLDP>; 2182 clock-names = "dpaux", "parent"; 2183 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2184 reset-names = "dpaux"; 2185 status = "disabled"; 2186 2187 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2188 2189 state_dpaux2_aux: pinmux-aux { 2190 groups = "dpaux-io"; 2191 function = "aux"; 2192 }; 2193 2194 state_dpaux2_i2c: pinmux-i2c { 2195 groups = "dpaux-io"; 2196 function = "i2c"; 2197 }; 2198 2199 state_dpaux2_off: pinmux-off { 2200 groups = "dpaux-io"; 2201 function = "off"; 2202 }; 2203 2204 i2c-bus { 2205 #address-cells = <1>; 2206 #size-cells = <0>; 2207 }; 2208 }; 2209 2210 dpaux3: dpaux@155f0000 { 2211 compatible = "nvidia,tegra194-dpaux"; 2212 reg = <0x0 0x155f0000 0x0 0x10000>; 2213 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2214 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2215 <&bpmp TEGRA194_CLK_PLLDP>; 2216 clock-names = "dpaux", "parent"; 2217 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2218 reset-names = "dpaux"; 2219 status = "disabled"; 2220 2221 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2222 2223 state_dpaux3_aux: pinmux-aux { 2224 groups = "dpaux-io"; 2225 function = "aux"; 2226 }; 2227 2228 state_dpaux3_i2c: pinmux-i2c { 2229 groups = "dpaux-io"; 2230 function = "i2c"; 2231 }; 2232 2233 state_dpaux3_off: pinmux-off { 2234 groups = "dpaux-io"; 2235 function = "off"; 2236 }; 2237 2238 i2c-bus { 2239 #address-cells = <1>; 2240 #size-cells = <0>; 2241 }; 2242 }; 2243 2244 nvenc@15a80000 { 2245 compatible = "nvidia,tegra194-nvenc"; 2246 reg = <0x0 0x15a80000 0x0 0x00040000>; 2247 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2248 clock-names = "nvenc"; 2249 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2250 reset-names = "nvenc"; 2251 2252 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2253 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2254 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2255 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2256 interconnect-names = "dma-mem", "read-1", "write"; 2257 iommus = <&smmu TEGRA194_SID_NVENC1>; 2258 dma-coherent; 2259 2260 nvidia,host1x-class = <0x22>; 2261 }; 2262 2263 sor0: sor@15b00000 { 2264 compatible = "nvidia,tegra194-sor"; 2265 reg = <0x0 0x15b00000 0x0 0x40000>; 2266 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2267 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2268 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2269 <&bpmp TEGRA194_CLK_PLLD>, 2270 <&bpmp TEGRA194_CLK_PLLDP>, 2271 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2272 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2273 clock-names = "sor", "out", "parent", "dp", "safe", 2274 "pad"; 2275 resets = <&bpmp TEGRA194_RESET_SOR0>; 2276 reset-names = "sor"; 2277 pinctrl-0 = <&state_dpaux0_aux>; 2278 pinctrl-1 = <&state_dpaux0_i2c>; 2279 pinctrl-2 = <&state_dpaux0_off>; 2280 pinctrl-names = "aux", "i2c", "off"; 2281 status = "disabled"; 2282 2283 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2284 nvidia,interface = <0>; 2285 }; 2286 2287 sor1: sor@15b40000 { 2288 compatible = "nvidia,tegra194-sor"; 2289 reg = <0x0 0x15b40000 0x0 0x40000>; 2290 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2291 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2292 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2293 <&bpmp TEGRA194_CLK_PLLD2>, 2294 <&bpmp TEGRA194_CLK_PLLDP>, 2295 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2296 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2297 clock-names = "sor", "out", "parent", "dp", "safe", 2298 "pad"; 2299 resets = <&bpmp TEGRA194_RESET_SOR1>; 2300 reset-names = "sor"; 2301 pinctrl-0 = <&state_dpaux1_aux>; 2302 pinctrl-1 = <&state_dpaux1_i2c>; 2303 pinctrl-2 = <&state_dpaux1_off>; 2304 pinctrl-names = "aux", "i2c", "off"; 2305 status = "disabled"; 2306 2307 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2308 nvidia,interface = <1>; 2309 }; 2310 2311 sor2: sor@15b80000 { 2312 compatible = "nvidia,tegra194-sor"; 2313 reg = <0x0 0x15b80000 0x0 0x40000>; 2314 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2315 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2316 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2317 <&bpmp TEGRA194_CLK_PLLD3>, 2318 <&bpmp TEGRA194_CLK_PLLDP>, 2319 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2320 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2321 clock-names = "sor", "out", "parent", "dp", "safe", 2322 "pad"; 2323 resets = <&bpmp TEGRA194_RESET_SOR2>; 2324 reset-names = "sor"; 2325 pinctrl-0 = <&state_dpaux2_aux>; 2326 pinctrl-1 = <&state_dpaux2_i2c>; 2327 pinctrl-2 = <&state_dpaux2_off>; 2328 pinctrl-names = "aux", "i2c", "off"; 2329 status = "disabled"; 2330 2331 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2332 nvidia,interface = <2>; 2333 }; 2334 2335 sor3: sor@15bc0000 { 2336 compatible = "nvidia,tegra194-sor"; 2337 reg = <0x0 0x15bc0000 0x0 0x40000>; 2338 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2339 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2340 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2341 <&bpmp TEGRA194_CLK_PLLD4>, 2342 <&bpmp TEGRA194_CLK_PLLDP>, 2343 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2344 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2345 clock-names = "sor", "out", "parent", "dp", "safe", 2346 "pad"; 2347 resets = <&bpmp TEGRA194_RESET_SOR3>; 2348 reset-names = "sor"; 2349 pinctrl-0 = <&state_dpaux3_aux>; 2350 pinctrl-1 = <&state_dpaux3_i2c>; 2351 pinctrl-2 = <&state_dpaux3_off>; 2352 pinctrl-names = "aux", "i2c", "off"; 2353 status = "disabled"; 2354 2355 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2356 nvidia,interface = <3>; 2357 }; 2358 }; 2359 2360 pcie@14100000 { 2361 compatible = "nvidia,tegra194-pcie"; 2362 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2363 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2364 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2365 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2366 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2367 reg-names = "appl", "config", "atu_dma", "dbi"; 2368 2369 status = "disabled"; 2370 2371 #address-cells = <3>; 2372 #size-cells = <2>; 2373 device_type = "pci"; 2374 num-lanes = <1>; 2375 linux,pci-domain = <1>; 2376 2377 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2378 clock-names = "core"; 2379 2380 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2381 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2382 reset-names = "apb", "core"; 2383 2384 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2385 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2386 interrupt-names = "intr", "msi"; 2387 2388 #interrupt-cells = <1>; 2389 interrupt-map-mask = <0 0 0 0>; 2390 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2391 2392 nvidia,bpmp = <&bpmp 1>; 2393 2394 nvidia,aspm-cmrt-us = <60>; 2395 nvidia,aspm-pwr-on-t-us = <20>; 2396 nvidia,aspm-l0s-entrance-latency-us = <3>; 2397 2398 bus-range = <0x0 0xff>; 2399 2400 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2401 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2402 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2403 2404 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2405 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2406 interconnect-names = "dma-mem", "write"; 2407 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2408 iommu-map-mask = <0x0>; 2409 dma-coherent; 2410 }; 2411 2412 pcie@14120000 { 2413 compatible = "nvidia,tegra194-pcie"; 2414 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2415 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2416 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2417 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2418 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2419 reg-names = "appl", "config", "atu_dma", "dbi"; 2420 2421 status = "disabled"; 2422 2423 #address-cells = <3>; 2424 #size-cells = <2>; 2425 device_type = "pci"; 2426 num-lanes = <1>; 2427 linux,pci-domain = <2>; 2428 2429 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2430 clock-names = "core"; 2431 2432 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2433 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2434 reset-names = "apb", "core"; 2435 2436 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2437 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2438 interrupt-names = "intr", "msi"; 2439 2440 #interrupt-cells = <1>; 2441 interrupt-map-mask = <0 0 0 0>; 2442 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2443 2444 nvidia,bpmp = <&bpmp 2>; 2445 2446 nvidia,aspm-cmrt-us = <60>; 2447 nvidia,aspm-pwr-on-t-us = <20>; 2448 nvidia,aspm-l0s-entrance-latency-us = <3>; 2449 2450 bus-range = <0x0 0xff>; 2451 2452 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2453 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2454 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2455 2456 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2457 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2458 interconnect-names = "dma-mem", "write"; 2459 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2460 iommu-map-mask = <0x0>; 2461 dma-coherent; 2462 }; 2463 2464 pcie@14140000 { 2465 compatible = "nvidia,tegra194-pcie"; 2466 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2467 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2468 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2469 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2470 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2471 reg-names = "appl", "config", "atu_dma", "dbi"; 2472 2473 status = "disabled"; 2474 2475 #address-cells = <3>; 2476 #size-cells = <2>; 2477 device_type = "pci"; 2478 num-lanes = <1>; 2479 linux,pci-domain = <3>; 2480 2481 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2482 clock-names = "core"; 2483 2484 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2485 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2486 reset-names = "apb", "core"; 2487 2488 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2489 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2490 interrupt-names = "intr", "msi"; 2491 2492 #interrupt-cells = <1>; 2493 interrupt-map-mask = <0 0 0 0>; 2494 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2495 2496 nvidia,bpmp = <&bpmp 3>; 2497 2498 nvidia,aspm-cmrt-us = <60>; 2499 nvidia,aspm-pwr-on-t-us = <20>; 2500 nvidia,aspm-l0s-entrance-latency-us = <3>; 2501 2502 bus-range = <0x0 0xff>; 2503 2504 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2505 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2506 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2507 2508 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2509 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2510 interconnect-names = "dma-mem", "write"; 2511 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2512 iommu-map-mask = <0x0>; 2513 dma-coherent; 2514 }; 2515 2516 pcie@14160000 { 2517 compatible = "nvidia,tegra194-pcie"; 2518 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2519 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2520 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2521 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2522 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2523 reg-names = "appl", "config", "atu_dma", "dbi"; 2524 2525 status = "disabled"; 2526 2527 #address-cells = <3>; 2528 #size-cells = <2>; 2529 device_type = "pci"; 2530 num-lanes = <4>; 2531 linux,pci-domain = <4>; 2532 2533 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2534 clock-names = "core"; 2535 2536 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2537 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2538 reset-names = "apb", "core"; 2539 2540 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2541 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2542 interrupt-names = "intr", "msi"; 2543 2544 #interrupt-cells = <1>; 2545 interrupt-map-mask = <0 0 0 0>; 2546 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2547 2548 nvidia,bpmp = <&bpmp 4>; 2549 2550 nvidia,aspm-cmrt-us = <60>; 2551 nvidia,aspm-pwr-on-t-us = <20>; 2552 nvidia,aspm-l0s-entrance-latency-us = <3>; 2553 2554 bus-range = <0x0 0xff>; 2555 2556 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2557 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2558 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2559 2560 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2561 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2562 interconnect-names = "dma-mem", "write"; 2563 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2564 iommu-map-mask = <0x0>; 2565 dma-coherent; 2566 }; 2567 2568 pcie-ep@14160000 { 2569 compatible = "nvidia,tegra194-pcie-ep"; 2570 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2571 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2572 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2573 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2574 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2575 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2576 2577 status = "disabled"; 2578 2579 num-lanes = <4>; 2580 num-ib-windows = <2>; 2581 num-ob-windows = <8>; 2582 2583 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2584 clock-names = "core"; 2585 2586 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2587 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2588 reset-names = "apb", "core"; 2589 2590 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2591 interrupt-names = "intr"; 2592 2593 nvidia,bpmp = <&bpmp 4>; 2594 2595 nvidia,aspm-cmrt-us = <60>; 2596 nvidia,aspm-pwr-on-t-us = <20>; 2597 nvidia,aspm-l0s-entrance-latency-us = <3>; 2598 2599 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2600 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2601 interconnect-names = "dma-mem", "write"; 2602 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2603 iommu-map-mask = <0x0>; 2604 dma-coherent; 2605 }; 2606 2607 pcie@14180000 { 2608 compatible = "nvidia,tegra194-pcie"; 2609 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2610 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2611 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2612 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2613 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2614 reg-names = "appl", "config", "atu_dma", "dbi"; 2615 2616 status = "disabled"; 2617 2618 #address-cells = <3>; 2619 #size-cells = <2>; 2620 device_type = "pci"; 2621 num-lanes = <8>; 2622 linux,pci-domain = <0>; 2623 2624 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2625 clock-names = "core"; 2626 2627 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2628 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2629 reset-names = "apb", "core"; 2630 2631 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2632 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2633 interrupt-names = "intr", "msi"; 2634 2635 #interrupt-cells = <1>; 2636 interrupt-map-mask = <0 0 0 0>; 2637 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2638 2639 nvidia,bpmp = <&bpmp 0>; 2640 2641 nvidia,aspm-cmrt-us = <60>; 2642 nvidia,aspm-pwr-on-t-us = <20>; 2643 nvidia,aspm-l0s-entrance-latency-us = <3>; 2644 2645 bus-range = <0x0 0xff>; 2646 2647 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2648 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2649 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2650 2651 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2652 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2653 interconnect-names = "dma-mem", "write"; 2654 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2655 iommu-map-mask = <0x0>; 2656 dma-coherent; 2657 }; 2658 2659 pcie-ep@14180000 { 2660 compatible = "nvidia,tegra194-pcie-ep"; 2661 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2662 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2663 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2664 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2665 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2666 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2667 2668 status = "disabled"; 2669 2670 num-lanes = <8>; 2671 num-ib-windows = <2>; 2672 num-ob-windows = <8>; 2673 2674 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2675 clock-names = "core"; 2676 2677 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2678 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2679 reset-names = "apb", "core"; 2680 2681 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2682 interrupt-names = "intr"; 2683 2684 nvidia,bpmp = <&bpmp 0>; 2685 2686 nvidia,aspm-cmrt-us = <60>; 2687 nvidia,aspm-pwr-on-t-us = <20>; 2688 nvidia,aspm-l0s-entrance-latency-us = <3>; 2689 2690 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2691 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2692 interconnect-names = "dma-mem", "write"; 2693 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2694 iommu-map-mask = <0x0>; 2695 dma-coherent; 2696 }; 2697 2698 pcie@141a0000 { 2699 compatible = "nvidia,tegra194-pcie"; 2700 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2701 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2702 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2703 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2704 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2705 reg-names = "appl", "config", "atu_dma", "dbi"; 2706 2707 status = "disabled"; 2708 2709 #address-cells = <3>; 2710 #size-cells = <2>; 2711 device_type = "pci"; 2712 num-lanes = <8>; 2713 linux,pci-domain = <5>; 2714 2715 pinctrl-names = "default"; 2716 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2717 2718 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2719 clock-names = "core"; 2720 2721 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2722 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2723 reset-names = "apb", "core"; 2724 2725 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2726 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2727 interrupt-names = "intr", "msi"; 2728 2729 nvidia,bpmp = <&bpmp 5>; 2730 2731 #interrupt-cells = <1>; 2732 interrupt-map-mask = <0 0 0 0>; 2733 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2734 2735 nvidia,aspm-cmrt-us = <60>; 2736 nvidia,aspm-pwr-on-t-us = <20>; 2737 nvidia,aspm-l0s-entrance-latency-us = <3>; 2738 2739 bus-range = <0x0 0xff>; 2740 2741 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2742 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2743 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2744 2745 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2746 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2747 interconnect-names = "dma-mem", "write"; 2748 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2749 iommu-map-mask = <0x0>; 2750 dma-coherent; 2751 }; 2752 2753 pcie-ep@141a0000 { 2754 compatible = "nvidia,tegra194-pcie-ep"; 2755 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2756 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2757 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2758 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2759 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2760 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2761 2762 status = "disabled"; 2763 2764 num-lanes = <8>; 2765 num-ib-windows = <2>; 2766 num-ob-windows = <8>; 2767 2768 pinctrl-names = "default"; 2769 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2770 2771 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2772 clock-names = "core"; 2773 2774 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2775 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2776 reset-names = "apb", "core"; 2777 2778 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2779 interrupt-names = "intr"; 2780 2781 nvidia,bpmp = <&bpmp 5>; 2782 2783 nvidia,aspm-cmrt-us = <60>; 2784 nvidia,aspm-pwr-on-t-us = <20>; 2785 nvidia,aspm-l0s-entrance-latency-us = <3>; 2786 2787 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2788 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2789 interconnect-names = "dma-mem", "write"; 2790 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2791 iommu-map-mask = <0x0>; 2792 dma-coherent; 2793 }; 2794 2795 gpu@17000000 { 2796 compatible = "nvidia,gv11b"; 2797 reg = <0x0 0x17000000 0x0 0x1000000>, 2798 <0x0 0x18000000 0x0 0x1000000>; 2799 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2801 interrupt-names = "stall", "nonstall"; 2802 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2803 <&bpmp TEGRA194_CLK_GPU_PWR>, 2804 <&bpmp TEGRA194_CLK_FUSE>; 2805 clock-names = "gpu", "pwr", "fuse"; 2806 resets = <&bpmp TEGRA194_RESET_GPU>; 2807 reset-names = "gpu"; 2808 dma-coherent; 2809 2810 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2811 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2812 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2813 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2814 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2815 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2816 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2817 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2818 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2819 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2820 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2821 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2822 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2823 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2824 "read-1", "read-1-hp", "write-1", 2825 "read-2", "read-2-hp", "write-2", 2826 "read-3", "read-3-hp", "write-3"; 2827 }; 2828 }; 2829 2830 sram@40000000 { 2831 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2832 reg = <0x0 0x40000000 0x0 0x50000>; 2833 2834 #address-cells = <1>; 2835 #size-cells = <1>; 2836 ranges = <0x0 0x0 0x40000000 0x50000>; 2837 2838 no-memory-wc; 2839 2840 cpu_bpmp_tx: sram@4e000 { 2841 reg = <0x4e000 0x1000>; 2842 label = "cpu-bpmp-tx"; 2843 pool; 2844 }; 2845 2846 cpu_bpmp_rx: sram@4f000 { 2847 reg = <0x4f000 0x1000>; 2848 label = "cpu-bpmp-rx"; 2849 pool; 2850 }; 2851 }; 2852 2853 bpmp: bpmp { 2854 compatible = "nvidia,tegra186-bpmp"; 2855 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2856 TEGRA_HSP_DB_MASTER_BPMP>; 2857 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2858 #clock-cells = <1>; 2859 #reset-cells = <1>; 2860 #power-domain-cells = <1>; 2861 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2862 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2863 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2864 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2865 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2866 iommus = <&smmu TEGRA194_SID_BPMP>; 2867 2868 bpmp_i2c: i2c { 2869 compatible = "nvidia,tegra186-bpmp-i2c"; 2870 nvidia,bpmp-bus-id = <5>; 2871 #address-cells = <1>; 2872 #size-cells = <0>; 2873 }; 2874 2875 bpmp_thermal: thermal { 2876 compatible = "nvidia,tegra186-bpmp-thermal"; 2877 #thermal-sensor-cells = <1>; 2878 }; 2879 }; 2880 2881 cpus { 2882 compatible = "nvidia,tegra194-ccplex"; 2883 nvidia,bpmp = <&bpmp>; 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 2887 cpu0_0: cpu@0 { 2888 compatible = "nvidia,tegra194-carmel"; 2889 device_type = "cpu"; 2890 reg = <0x000>; 2891 enable-method = "psci"; 2892 i-cache-size = <131072>; 2893 i-cache-line-size = <64>; 2894 i-cache-sets = <512>; 2895 d-cache-size = <65536>; 2896 d-cache-line-size = <64>; 2897 d-cache-sets = <256>; 2898 next-level-cache = <&l2c_0>; 2899 }; 2900 2901 cpu0_1: cpu@1 { 2902 compatible = "nvidia,tegra194-carmel"; 2903 device_type = "cpu"; 2904 reg = <0x001>; 2905 enable-method = "psci"; 2906 i-cache-size = <131072>; 2907 i-cache-line-size = <64>; 2908 i-cache-sets = <512>; 2909 d-cache-size = <65536>; 2910 d-cache-line-size = <64>; 2911 d-cache-sets = <256>; 2912 next-level-cache = <&l2c_0>; 2913 }; 2914 2915 cpu1_0: cpu@100 { 2916 compatible = "nvidia,tegra194-carmel"; 2917 device_type = "cpu"; 2918 reg = <0x100>; 2919 enable-method = "psci"; 2920 i-cache-size = <131072>; 2921 i-cache-line-size = <64>; 2922 i-cache-sets = <512>; 2923 d-cache-size = <65536>; 2924 d-cache-line-size = <64>; 2925 d-cache-sets = <256>; 2926 next-level-cache = <&l2c_1>; 2927 }; 2928 2929 cpu1_1: cpu@101 { 2930 compatible = "nvidia,tegra194-carmel"; 2931 device_type = "cpu"; 2932 reg = <0x101>; 2933 enable-method = "psci"; 2934 i-cache-size = <131072>; 2935 i-cache-line-size = <64>; 2936 i-cache-sets = <512>; 2937 d-cache-size = <65536>; 2938 d-cache-line-size = <64>; 2939 d-cache-sets = <256>; 2940 next-level-cache = <&l2c_1>; 2941 }; 2942 2943 cpu2_0: cpu@200 { 2944 compatible = "nvidia,tegra194-carmel"; 2945 device_type = "cpu"; 2946 reg = <0x200>; 2947 enable-method = "psci"; 2948 i-cache-size = <131072>; 2949 i-cache-line-size = <64>; 2950 i-cache-sets = <512>; 2951 d-cache-size = <65536>; 2952 d-cache-line-size = <64>; 2953 d-cache-sets = <256>; 2954 next-level-cache = <&l2c_2>; 2955 }; 2956 2957 cpu2_1: cpu@201 { 2958 compatible = "nvidia,tegra194-carmel"; 2959 device_type = "cpu"; 2960 reg = <0x201>; 2961 enable-method = "psci"; 2962 i-cache-size = <131072>; 2963 i-cache-line-size = <64>; 2964 i-cache-sets = <512>; 2965 d-cache-size = <65536>; 2966 d-cache-line-size = <64>; 2967 d-cache-sets = <256>; 2968 next-level-cache = <&l2c_2>; 2969 }; 2970 2971 cpu3_0: cpu@300 { 2972 compatible = "nvidia,tegra194-carmel"; 2973 device_type = "cpu"; 2974 reg = <0x300>; 2975 enable-method = "psci"; 2976 i-cache-size = <131072>; 2977 i-cache-line-size = <64>; 2978 i-cache-sets = <512>; 2979 d-cache-size = <65536>; 2980 d-cache-line-size = <64>; 2981 d-cache-sets = <256>; 2982 next-level-cache = <&l2c_3>; 2983 }; 2984 2985 cpu3_1: cpu@301 { 2986 compatible = "nvidia,tegra194-carmel"; 2987 device_type = "cpu"; 2988 reg = <0x301>; 2989 enable-method = "psci"; 2990 i-cache-size = <131072>; 2991 i-cache-line-size = <64>; 2992 i-cache-sets = <512>; 2993 d-cache-size = <65536>; 2994 d-cache-line-size = <64>; 2995 d-cache-sets = <256>; 2996 next-level-cache = <&l2c_3>; 2997 }; 2998 2999 cpu-map { 3000 cluster0 { 3001 core0 { 3002 cpu = <&cpu0_0>; 3003 }; 3004 3005 core1 { 3006 cpu = <&cpu0_1>; 3007 }; 3008 }; 3009 3010 cluster1 { 3011 core0 { 3012 cpu = <&cpu1_0>; 3013 }; 3014 3015 core1 { 3016 cpu = <&cpu1_1>; 3017 }; 3018 }; 3019 3020 cluster2 { 3021 core0 { 3022 cpu = <&cpu2_0>; 3023 }; 3024 3025 core1 { 3026 cpu = <&cpu2_1>; 3027 }; 3028 }; 3029 3030 cluster3 { 3031 core0 { 3032 cpu = <&cpu3_0>; 3033 }; 3034 3035 core1 { 3036 cpu = <&cpu3_1>; 3037 }; 3038 }; 3039 }; 3040 3041 l2c_0: l2-cache0 { 3042 compatible = "cache"; 3043 cache-unified; 3044 cache-size = <2097152>; 3045 cache-line-size = <64>; 3046 cache-sets = <2048>; 3047 cache-level = <2>; 3048 next-level-cache = <&l3c>; 3049 }; 3050 3051 l2c_1: l2-cache1 { 3052 compatible = "cache"; 3053 cache-unified; 3054 cache-size = <2097152>; 3055 cache-line-size = <64>; 3056 cache-sets = <2048>; 3057 cache-level = <2>; 3058 next-level-cache = <&l3c>; 3059 }; 3060 3061 l2c_2: l2-cache2 { 3062 compatible = "cache"; 3063 cache-unified; 3064 cache-size = <2097152>; 3065 cache-line-size = <64>; 3066 cache-sets = <2048>; 3067 cache-level = <2>; 3068 next-level-cache = <&l3c>; 3069 }; 3070 3071 l2c_3: l2-cache3 { 3072 compatible = "cache"; 3073 cache-unified; 3074 cache-size = <2097152>; 3075 cache-line-size = <64>; 3076 cache-sets = <2048>; 3077 cache-level = <2>; 3078 next-level-cache = <&l3c>; 3079 }; 3080 3081 l3c: l3-cache { 3082 compatible = "cache"; 3083 cache-unified; 3084 cache-size = <4194304>; 3085 cache-line-size = <64>; 3086 cache-level = <3>; 3087 cache-sets = <4096>; 3088 }; 3089 }; 3090 3091 pmu { 3092 compatible = "nvidia,carmel-pmu"; 3093 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3101 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3102 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3103 }; 3104 3105 psci { 3106 compatible = "arm,psci-1.0"; 3107 status = "okay"; 3108 method = "smc"; 3109 }; 3110 3111 tcu: serial { 3112 compatible = "nvidia,tegra194-tcu"; 3113 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3114 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3115 mbox-names = "rx", "tx"; 3116 }; 3117 3118 sound { 3119 status = "disabled"; 3120 3121 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3122 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3123 clock-names = "pll_a", "plla_out0"; 3124 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3125 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3126 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3127 assigned-clock-parents = <0>, 3128 <&bpmp TEGRA194_CLK_PLLA>, 3129 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3130 /* 3131 * PLLA supports dynamic ramp. Below initial rate is chosen 3132 * for this to work and oscillate between base rates required 3133 * for 8x and 11.025x sample rate streams. 3134 */ 3135 assigned-clock-rates = <258000000>; 3136 }; 3137 3138 thermal-zones { 3139 cpu-thermal { 3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3141 status = "disabled"; 3142 }; 3143 3144 gpu-thermal { 3145 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3146 status = "disabled"; 3147 }; 3148 3149 aux-thermal { 3150 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3151 status = "disabled"; 3152 }; 3153 3154 pllx-thermal { 3155 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3156 status = "disabled"; 3157 }; 3158 3159 ao-thermal { 3160 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3161 status = "disabled"; 3162 }; 3163 3164 tj-thermal { 3165 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3166 status = "disabled"; 3167 }; 3168 }; 3169 3170 timer { 3171 compatible = "arm,armv8-timer"; 3172 interrupts = <GIC_PPI 13 3173 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3174 <GIC_PPI 14 3175 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3176 <GIC_PPI 11 3177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3178 <GIC_PPI 10 3179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3180 interrupt-parent = <&gic>; 3181 always-on; 3182 }; 3183}; 3184