1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/reset/qcom,gcc-msm8916.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ 20 sdhc2 = &sdhc_2; /* SDC2 SD card slot */ 21 }; 22 23 chosen { }; 24 25 memory { 26 device_type = "memory"; 27 /* We expect the bootloader to fill in the reg */ 28 reg = <0 0 0 0>; 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 tz-apps@86000000 { 37 reg = <0x0 0x86000000 0x0 0x300000>; 38 no-map; 39 }; 40 41 smem_mem: smem_region@86300000 { 42 reg = <0x0 0x86300000 0x0 0x100000>; 43 no-map; 44 }; 45 46 hypervisor@86400000 { 47 reg = <0x0 0x86400000 0x0 0x100000>; 48 no-map; 49 }; 50 51 tz@86500000 { 52 reg = <0x0 0x86500000 0x0 0x180000>; 53 no-map; 54 }; 55 56 reserved@8668000 { 57 reg = <0x0 0x86680000 0x0 0x80000>; 58 no-map; 59 }; 60 61 rmtfs@86700000 { 62 compatible = "qcom,rmtfs-mem"; 63 reg = <0x0 0x86700000 0x0 0xe0000>; 64 no-map; 65 66 qcom,client-id = <1>; 67 }; 68 69 rfsa@867e00000 { 70 reg = <0x0 0x867e0000 0x0 0x20000>; 71 no-map; 72 }; 73 74 mpss_mem: mpss@86800000 { 75 reg = <0x0 0x86800000 0x0 0x2b00000>; 76 no-map; 77 }; 78 79 wcnss_mem: wcnss@89300000 { 80 reg = <0x0 0x89300000 0x0 0x600000>; 81 no-map; 82 }; 83 84 venus_mem: venus@89900000 { 85 reg = <0x0 0x89900000 0x0 0x600000>; 86 no-map; 87 }; 88 89 mba_mem: mba@8ea00000 { 90 no-map; 91 reg = <0 0x8ea00000 0 0x100000>; 92 }; 93 }; 94 95 cpus { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 CPU0: cpu@0 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a53"; 102 reg = <0x0>; 103 next-level-cache = <&L2_0>; 104 enable-method = "psci"; 105 cpu-idle-states = <&CPU_SPC>; 106 clocks = <&apcs>; 107 operating-points-v2 = <&cpu_opp_table>; 108 #cooling-cells = <2>; 109 }; 110 111 CPU1: cpu@1 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x1>; 115 next-level-cache = <&L2_0>; 116 enable-method = "psci"; 117 cpu-idle-states = <&CPU_SPC>; 118 clocks = <&apcs>; 119 operating-points-v2 = <&cpu_opp_table>; 120 #cooling-cells = <2>; 121 }; 122 123 CPU2: cpu@2 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a53"; 126 reg = <0x2>; 127 next-level-cache = <&L2_0>; 128 enable-method = "psci"; 129 cpu-idle-states = <&CPU_SPC>; 130 clocks = <&apcs>; 131 operating-points-v2 = <&cpu_opp_table>; 132 #cooling-cells = <2>; 133 }; 134 135 CPU3: cpu@3 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x3>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 cpu-idle-states = <&CPU_SPC>; 142 clocks = <&apcs>; 143 operating-points-v2 = <&cpu_opp_table>; 144 #cooling-cells = <2>; 145 }; 146 147 L2_0: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 }; 151 152 idle-states { 153 CPU_SPC: spc { 154 compatible = "arm,idle-state"; 155 arm,psci-suspend-param = <0x40000002>; 156 entry-latency-us = <130>; 157 exit-latency-us = <150>; 158 min-residency-us = <2000>; 159 local-timer-stop; 160 }; 161 }; 162 }; 163 164 psci { 165 compatible = "arm,psci-1.0"; 166 method = "smc"; 167 }; 168 169 pmu { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 172 }; 173 174 thermal-zones { 175 cpu0_1-thermal { 176 polling-delay-passive = <250>; 177 polling-delay = <1000>; 178 179 thermal-sensors = <&tsens 4>; 180 181 trips { 182 cpu0_1_alert0: trip-point@0 { 183 temperature = <75000>; 184 hysteresis = <2000>; 185 type = "passive"; 186 }; 187 cpu0_1_crit: cpu_crit { 188 temperature = <110000>; 189 hysteresis = <2000>; 190 type = "critical"; 191 }; 192 }; 193 194 cooling-maps { 195 map0 { 196 trip = <&cpu0_1_alert0>; 197 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 198 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 200 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 201 }; 202 }; 203 }; 204 205 cpu2_3-thermal { 206 polling-delay-passive = <250>; 207 polling-delay = <1000>; 208 209 thermal-sensors = <&tsens 3>; 210 211 trips { 212 cpu2_3_alert0: trip-point@0 { 213 temperature = <75000>; 214 hysteresis = <2000>; 215 type = "passive"; 216 }; 217 cpu2_3_crit: cpu_crit { 218 temperature = <110000>; 219 hysteresis = <2000>; 220 type = "critical"; 221 }; 222 }; 223 224 cooling-maps { 225 map0 { 226 trip = <&cpu2_3_alert0>; 227 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 228 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 229 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 230 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 231 }; 232 }; 233 }; 234 235 gpu-thermal { 236 polling-delay-passive = <250>; 237 polling-delay = <1000>; 238 239 thermal-sensors = <&tsens 2>; 240 241 trips { 242 gpu_alert0: trip-point@0 { 243 temperature = <75000>; 244 hysteresis = <2000>; 245 type = "passive"; 246 }; 247 gpu_crit: gpu_crit { 248 temperature = <95000>; 249 hysteresis = <2000>; 250 type = "critical"; 251 }; 252 }; 253 }; 254 255 camera-thermal { 256 polling-delay-passive = <250>; 257 polling-delay = <1000>; 258 259 thermal-sensors = <&tsens 1>; 260 261 trips { 262 cam_alert0: trip-point@0 { 263 temperature = <75000>; 264 hysteresis = <2000>; 265 type = "hot"; 266 }; 267 }; 268 }; 269 270 modem-thermal { 271 polling-delay-passive = <250>; 272 polling-delay = <1000>; 273 274 thermal-sensors = <&tsens 0>; 275 276 trips { 277 modem_alert0: trip-point@0 { 278 temperature = <85000>; 279 hysteresis = <2000>; 280 type = "hot"; 281 }; 282 }; 283 }; 284 285 }; 286 287 cpu_opp_table: cpu_opp_table { 288 compatible = "operating-points-v2"; 289 opp-shared; 290 291 opp-200000000 { 292 opp-hz = /bits/ 64 <200000000>; 293 }; 294 opp-400000000 { 295 opp-hz = /bits/ 64 <400000000>; 296 }; 297 opp-800000000 { 298 opp-hz = /bits/ 64 <800000000>; 299 }; 300 opp-998400000 { 301 opp-hz = /bits/ 64 <998400000>; 302 }; 303 }; 304 305 gpu_opp_table: opp_table { 306 compatible = "operating-points-v2"; 307 308 opp-400000000 { 309 opp-hz = /bits/ 64 <400000000>; 310 }; 311 opp-19200000 { 312 opp-hz = /bits/ 64 <19200000>; 313 }; 314 }; 315 316 timer { 317 compatible = "arm,armv8-timer"; 318 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 319 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 320 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 321 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 322 }; 323 324 clocks { 325 xo_board: xo_board { 326 compatible = "fixed-clock"; 327 #clock-cells = <0>; 328 clock-frequency = <19200000>; 329 }; 330 331 sleep_clk: sleep_clk { 332 compatible = "fixed-clock"; 333 #clock-cells = <0>; 334 clock-frequency = <32768>; 335 }; 336 }; 337 338 smem { 339 compatible = "qcom,smem"; 340 341 memory-region = <&smem_mem>; 342 qcom,rpm-msg-ram = <&rpm_msg_ram>; 343 344 hwlocks = <&tcsr_mutex 3>; 345 }; 346 347 firmware { 348 scm: scm { 349 compatible = "qcom,scm"; 350 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; 351 clock-names = "core", "bus", "iface"; 352 #reset-cells = <1>; 353 354 qcom,dload-mode = <&tcsr 0x6100>; 355 }; 356 }; 357 358 soc: soc { 359 #address-cells = <1>; 360 #size-cells = <1>; 361 ranges = <0 0 0 0xffffffff>; 362 compatible = "simple-bus"; 363 364 restart@4ab000 { 365 compatible = "qcom,pshold"; 366 reg = <0x4ab000 0x4>; 367 }; 368 369 msmgpio: pinctrl@1000000 { 370 compatible = "qcom,msm8916-pinctrl"; 371 reg = <0x1000000 0x300000>; 372 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 }; 378 379 gcc: clock-controller@1800000 { 380 compatible = "qcom,gcc-msm8916"; 381 #clock-cells = <1>; 382 #reset-cells = <1>; 383 #power-domain-cells = <1>; 384 reg = <0x1800000 0x80000>; 385 }; 386 387 tcsr_mutex_regs: syscon@1905000 { 388 compatible = "syscon"; 389 reg = <0x1905000 0x20000>; 390 }; 391 392 tcsr: syscon@1937000 { 393 compatible = "qcom,tcsr-msm8916", "syscon"; 394 reg = <0x1937000 0x30000>; 395 }; 396 397 tcsr_mutex: hwlock { 398 compatible = "qcom,tcsr-mutex"; 399 syscon = <&tcsr_mutex_regs 0 0x1000>; 400 #hwlock-cells = <1>; 401 }; 402 403 rpm_msg_ram: memory@60000 { 404 compatible = "qcom,rpm-msg-ram"; 405 reg = <0x60000 0x8000>; 406 }; 407 408 blsp1_uart1: serial@78af000 { 409 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 410 reg = <0x78af000 0x200>; 411 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 413 clock-names = "core", "iface"; 414 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 415 dma-names = "rx", "tx"; 416 status = "disabled"; 417 }; 418 419 a53pll: clock@b016000 { 420 compatible = "qcom,msm8916-a53pll"; 421 reg = <0xb016000 0x40>; 422 #clock-cells = <0>; 423 }; 424 425 apcs: mailbox@b011000 { 426 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 427 reg = <0xb011000 0x1000>; 428 #mbox-cells = <1>; 429 clocks = <&a53pll>; 430 #clock-cells = <0>; 431 }; 432 433 blsp1_uart2: serial@78b0000 { 434 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 435 reg = <0x78b0000 0x200>; 436 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 438 clock-names = "core", "iface"; 439 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 440 dma-names = "rx", "tx"; 441 status = "disabled"; 442 }; 443 444 blsp_dma: dma@7884000 { 445 compatible = "qcom,bam-v1.7.0"; 446 reg = <0x07884000 0x23000>; 447 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 449 clock-names = "bam_clk"; 450 #dma-cells = <1>; 451 qcom,ee = <0>; 452 status = "disabled"; 453 }; 454 455 blsp_spi1: spi@78b5000 { 456 compatible = "qcom,spi-qup-v2.2.1"; 457 reg = <0x078b5000 0x500>; 458 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 460 <&gcc GCC_BLSP1_AHB_CLK>; 461 clock-names = "core", "iface"; 462 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 463 dma-names = "rx", "tx"; 464 pinctrl-names = "default", "sleep"; 465 pinctrl-0 = <&spi1_default>; 466 pinctrl-1 = <&spi1_sleep>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 blsp_spi2: spi@78b6000 { 473 compatible = "qcom,spi-qup-v2.2.1"; 474 reg = <0x078b6000 0x500>; 475 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 477 <&gcc GCC_BLSP1_AHB_CLK>; 478 clock-names = "core", "iface"; 479 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 480 dma-names = "rx", "tx"; 481 pinctrl-names = "default", "sleep"; 482 pinctrl-0 = <&spi2_default>; 483 pinctrl-1 = <&spi2_sleep>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 blsp_spi3: spi@78b7000 { 490 compatible = "qcom,spi-qup-v2.2.1"; 491 reg = <0x078b7000 0x500>; 492 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 494 <&gcc GCC_BLSP1_AHB_CLK>; 495 clock-names = "core", "iface"; 496 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 497 dma-names = "rx", "tx"; 498 pinctrl-names = "default", "sleep"; 499 pinctrl-0 = <&spi3_default>; 500 pinctrl-1 = <&spi3_sleep>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 status = "disabled"; 504 }; 505 506 blsp_spi4: spi@78b8000 { 507 compatible = "qcom,spi-qup-v2.2.1"; 508 reg = <0x078b8000 0x500>; 509 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 511 <&gcc GCC_BLSP1_AHB_CLK>; 512 clock-names = "core", "iface"; 513 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 514 dma-names = "rx", "tx"; 515 pinctrl-names = "default", "sleep"; 516 pinctrl-0 = <&spi4_default>; 517 pinctrl-1 = <&spi4_sleep>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 status = "disabled"; 521 }; 522 523 blsp_spi5: spi@78b9000 { 524 compatible = "qcom,spi-qup-v2.2.1"; 525 reg = <0x078b9000 0x500>; 526 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 528 <&gcc GCC_BLSP1_AHB_CLK>; 529 clock-names = "core", "iface"; 530 dmas = <&blsp_dma 13>, <&blsp_dma 12>; 531 dma-names = "rx", "tx"; 532 pinctrl-names = "default", "sleep"; 533 pinctrl-0 = <&spi5_default>; 534 pinctrl-1 = <&spi5_sleep>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 status = "disabled"; 538 }; 539 540 blsp_spi6: spi@78ba000 { 541 compatible = "qcom,spi-qup-v2.2.1"; 542 reg = <0x078ba000 0x500>; 543 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 545 <&gcc GCC_BLSP1_AHB_CLK>; 546 clock-names = "core", "iface"; 547 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 548 dma-names = "rx", "tx"; 549 pinctrl-names = "default", "sleep"; 550 pinctrl-0 = <&spi6_default>; 551 pinctrl-1 = <&spi6_sleep>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 blsp_i2c2: i2c@78b6000 { 558 compatible = "qcom,i2c-qup-v2.2.1"; 559 reg = <0x078b6000 0x500>; 560 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 562 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 563 clock-names = "iface", "core"; 564 pinctrl-names = "default", "sleep"; 565 pinctrl-0 = <&i2c2_default>; 566 pinctrl-1 = <&i2c2_sleep>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 blsp_i2c4: i2c@78b8000 { 573 compatible = "qcom,i2c-qup-v2.2.1"; 574 reg = <0x078b8000 0x500>; 575 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 577 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 578 clock-names = "iface", "core"; 579 pinctrl-names = "default", "sleep"; 580 pinctrl-0 = <&i2c4_default>; 581 pinctrl-1 = <&i2c4_sleep>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 blsp_i2c6: i2c@78ba000 { 588 compatible = "qcom,i2c-qup-v2.2.1"; 589 reg = <0x078ba000 0x500>; 590 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 592 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 593 clock-names = "iface", "core"; 594 pinctrl-names = "default", "sleep"; 595 pinctrl-0 = <&i2c6_default>; 596 pinctrl-1 = <&i2c6_sleep>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 lpass: lpass@7708000 { 603 status = "disabled"; 604 compatible = "qcom,lpass-cpu-apq8016"; 605 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 606 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 607 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 608 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 609 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 610 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 611 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 612 613 clock-names = "ahbix-clk", 614 "pcnoc-mport-clk", 615 "pcnoc-sway-clk", 616 "mi2s-bit-clk0", 617 "mi2s-bit-clk1", 618 "mi2s-bit-clk2", 619 "mi2s-bit-clk3"; 620 #sound-dai-cells = <1>; 621 622 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "lpass-irq-lpaif"; 624 reg = <0x07708000 0x10000>; 625 reg-names = "lpass-lpaif"; 626 }; 627 628 lpass_codec: codec{ 629 compatible = "qcom,msm8916-wcd-digital-codec"; 630 reg = <0x0771c000 0x400>; 631 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 632 <&gcc GCC_CODEC_DIGCODEC_CLK>; 633 clock-names = "ahbix-clk", "mclk"; 634 #sound-dai-cells = <1>; 635 }; 636 637 sdhc_1: sdhci@7824000 { 638 compatible = "qcom,sdhci-msm-v4"; 639 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 640 reg-names = "hc_mem", "core_mem"; 641 642 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; 643 interrupt-names = "hc_irq", "pwr_irq"; 644 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 645 <&gcc GCC_SDCC1_AHB_CLK>, 646 <&xo_board>; 647 clock-names = "core", "iface", "xo"; 648 mmc-ddr-1_8v; 649 bus-width = <8>; 650 non-removable; 651 status = "disabled"; 652 }; 653 654 sdhc_2: sdhci@7864000 { 655 compatible = "qcom,sdhci-msm-v4"; 656 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 657 reg-names = "hc_mem", "core_mem"; 658 659 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; 660 interrupt-names = "hc_irq", "pwr_irq"; 661 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 662 <&gcc GCC_SDCC2_AHB_CLK>, 663 <&xo_board>; 664 clock-names = "core", "iface", "xo"; 665 bus-width = <4>; 666 status = "disabled"; 667 }; 668 669 otg: usb@78d9000 { 670 compatible = "qcom,ci-hdrc"; 671 reg = <0x78d9000 0x200>, 672 <0x78d9200 0x200>; 673 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 676 <&gcc GCC_USB_HS_SYSTEM_CLK>; 677 clock-names = "iface", "core"; 678 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 679 assigned-clock-rates = <80000000>; 680 resets = <&gcc GCC_USB_HS_BCR>; 681 reset-names = "core"; 682 phy_type = "ulpi"; 683 dr_mode = "otg"; 684 ahb-burst-config = <0>; 685 phy-names = "usb-phy"; 686 phys = <&usb_hs_phy>; 687 status = "disabled"; 688 #reset-cells = <1>; 689 690 ulpi { 691 usb_hs_phy: phy { 692 compatible = "qcom,usb-hs-phy-msm8916", 693 "qcom,usb-hs-phy"; 694 #phy-cells = <0>; 695 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 696 clock-names = "ref", "sleep"; 697 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 698 reset-names = "phy", "por"; 699 qcom,init-seq = /bits/ 8 <0x0 0x44 700 0x1 0x6b 0x2 0x24 0x3 0x13>; 701 }; 702 }; 703 }; 704 705 intc: interrupt-controller@b000000 { 706 compatible = "qcom,msm-qgic2"; 707 interrupt-controller; 708 #interrupt-cells = <3>; 709 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 710 }; 711 712 timer@b020000 { 713 #address-cells = <1>; 714 #size-cells = <1>; 715 ranges; 716 compatible = "arm,armv7-timer-mem"; 717 reg = <0xb020000 0x1000>; 718 clock-frequency = <19200000>; 719 720 frame@b021000 { 721 frame-number = <0>; 722 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 724 reg = <0xb021000 0x1000>, 725 <0xb022000 0x1000>; 726 }; 727 728 frame@b023000 { 729 frame-number = <1>; 730 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 731 reg = <0xb023000 0x1000>; 732 status = "disabled"; 733 }; 734 735 frame@b024000 { 736 frame-number = <2>; 737 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 738 reg = <0xb024000 0x1000>; 739 status = "disabled"; 740 }; 741 742 frame@b025000 { 743 frame-number = <3>; 744 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 745 reg = <0xb025000 0x1000>; 746 status = "disabled"; 747 }; 748 749 frame@b026000 { 750 frame-number = <4>; 751 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 752 reg = <0xb026000 0x1000>; 753 status = "disabled"; 754 }; 755 756 frame@b027000 { 757 frame-number = <5>; 758 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 759 reg = <0xb027000 0x1000>; 760 status = "disabled"; 761 }; 762 763 frame@b028000 { 764 frame-number = <6>; 765 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 766 reg = <0xb028000 0x1000>; 767 status = "disabled"; 768 }; 769 }; 770 771 spmi_bus: spmi@200f000 { 772 compatible = "qcom,spmi-pmic-arb"; 773 reg = <0x200f000 0x001000>, 774 <0x2400000 0x400000>, 775 <0x2c00000 0x400000>, 776 <0x3800000 0x200000>, 777 <0x200a000 0x002100>; 778 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 779 interrupt-names = "periph_irq"; 780 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 781 qcom,ee = <0>; 782 qcom,channel = <0>; 783 #address-cells = <2>; 784 #size-cells = <0>; 785 interrupt-controller; 786 #interrupt-cells = <4>; 787 }; 788 789 rng@22000 { 790 compatible = "qcom,prng"; 791 reg = <0x00022000 0x200>; 792 clocks = <&gcc GCC_PRNG_AHB_CLK>; 793 clock-names = "core"; 794 }; 795 796 qfprom: qfprom@5c000 { 797 compatible = "qcom,qfprom"; 798 reg = <0x5c000 0x1000>; 799 #address-cells = <1>; 800 #size-cells = <1>; 801 tsens_caldata: caldata@d0 { 802 reg = <0xd0 0x8>; 803 }; 804 tsens_calsel: calsel@ec { 805 reg = <0xec 0x4>; 806 }; 807 }; 808 809 tsens: thermal-sensor@4a9000 { 810 compatible = "qcom,msm8916-tsens"; 811 reg = <0x4a9000 0x1000>, /* TM */ 812 <0x4a8000 0x1000>; /* SROT */ 813 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; 814 nvmem-cell-names = "calib", "calib_sel"; 815 #qcom,sensors = <5>; 816 #thermal-sensor-cells = <1>; 817 }; 818 819 apps_iommu: iommu@1ef0000 { 820 #address-cells = <1>; 821 #size-cells = <1>; 822 #iommu-cells = <1>; 823 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 824 ranges = <0 0x1e20000 0x40000>; 825 reg = <0x1ef0000 0x3000>; 826 clocks = <&gcc GCC_SMMU_CFG_CLK>, 827 <&gcc GCC_APSS_TCU_CLK>; 828 clock-names = "iface", "bus"; 829 qcom,iommu-secure-id = <17>; 830 831 // vfe: 832 iommu-ctx@3000 { 833 compatible = "qcom,msm-iommu-v1-sec"; 834 reg = <0x3000 0x1000>; 835 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 836 }; 837 838 // mdp_0: 839 iommu-ctx@4000 { 840 compatible = "qcom,msm-iommu-v1-ns"; 841 reg = <0x4000 0x1000>; 842 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 843 }; 844 845 // venus_ns: 846 iommu-ctx@5000 { 847 compatible = "qcom,msm-iommu-v1-sec"; 848 reg = <0x5000 0x1000>; 849 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 850 }; 851 }; 852 853 gpu_iommu: iommu@1f08000 { 854 #address-cells = <1>; 855 #size-cells = <1>; 856 #iommu-cells = <1>; 857 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 858 ranges = <0 0x1f08000 0x10000>; 859 clocks = <&gcc GCC_SMMU_CFG_CLK>, 860 <&gcc GCC_GFX_TCU_CLK>; 861 clock-names = "iface", "bus"; 862 qcom,iommu-secure-id = <18>; 863 864 // gfx3d_user: 865 iommu-ctx@1000 { 866 compatible = "qcom,msm-iommu-v1-ns"; 867 reg = <0x1000 0x1000>; 868 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 869 }; 870 871 // gfx3d_priv: 872 iommu-ctx@2000 { 873 compatible = "qcom,msm-iommu-v1-ns"; 874 reg = <0x2000 0x1000>; 875 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 876 }; 877 }; 878 879 gpu@1c00000 { 880 compatible = "qcom,adreno-306.0", "qcom,adreno"; 881 reg = <0x01c00000 0x20000>; 882 reg-names = "kgsl_3d0_reg_memory"; 883 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-names = "kgsl_3d0_irq"; 885 clock-names = 886 "core", 887 "iface", 888 "mem", 889 "mem_iface", 890 "alt_mem_iface", 891 "gfx3d"; 892 clocks = 893 <&gcc GCC_OXILI_GFX3D_CLK>, 894 <&gcc GCC_OXILI_AHB_CLK>, 895 <&gcc GCC_OXILI_GMEM_CLK>, 896 <&gcc GCC_BIMC_GFX_CLK>, 897 <&gcc GCC_BIMC_GPU_CLK>, 898 <&gcc GFX3D_CLK_SRC>; 899 power-domains = <&gcc OXILI_GDSC>; 900 operating-points-v2 = <&gpu_opp_table>; 901 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 902 }; 903 904 mdss: mdss@1a00000 { 905 compatible = "qcom,mdss"; 906 reg = <0x1a00000 0x1000>, 907 <0x1ac8000 0x3000>; 908 reg-names = "mdss_phys", "vbif_phys"; 909 910 power-domains = <&gcc MDSS_GDSC>; 911 912 clocks = <&gcc GCC_MDSS_AHB_CLK>, 913 <&gcc GCC_MDSS_AXI_CLK>, 914 <&gcc GCC_MDSS_VSYNC_CLK>; 915 clock-names = "iface", 916 "bus", 917 "vsync"; 918 919 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 920 921 interrupt-controller; 922 #interrupt-cells = <1>; 923 924 #address-cells = <1>; 925 #size-cells = <1>; 926 ranges; 927 928 mdp: mdp@1a01000 { 929 compatible = "qcom,mdp5"; 930 reg = <0x1a01000 0x89000>; 931 reg-names = "mdp_phys"; 932 933 interrupt-parent = <&mdss>; 934 interrupts = <0 0>; 935 936 clocks = <&gcc GCC_MDSS_AHB_CLK>, 937 <&gcc GCC_MDSS_AXI_CLK>, 938 <&gcc GCC_MDSS_MDP_CLK>, 939 <&gcc GCC_MDSS_VSYNC_CLK>; 940 clock-names = "iface", 941 "bus", 942 "core", 943 "vsync"; 944 945 iommus = <&apps_iommu 4>; 946 947 ports { 948 #address-cells = <1>; 949 #size-cells = <0>; 950 951 port@0 { 952 reg = <0>; 953 mdp5_intf1_out: endpoint { 954 remote-endpoint = <&dsi0_in>; 955 }; 956 }; 957 }; 958 }; 959 960 dsi0: dsi@1a98000 { 961 compatible = "qcom,mdss-dsi-ctrl"; 962 reg = <0x1a98000 0x25c>; 963 reg-names = "dsi_ctrl"; 964 965 interrupt-parent = <&mdss>; 966 interrupts = <4 0>; 967 968 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 969 <&gcc PCLK0_CLK_SRC>; 970 assigned-clock-parents = <&dsi_phy0 0>, 971 <&dsi_phy0 1>; 972 973 clocks = <&gcc GCC_MDSS_MDP_CLK>, 974 <&gcc GCC_MDSS_AHB_CLK>, 975 <&gcc GCC_MDSS_AXI_CLK>, 976 <&gcc GCC_MDSS_BYTE0_CLK>, 977 <&gcc GCC_MDSS_PCLK0_CLK>, 978 <&gcc GCC_MDSS_ESC0_CLK>; 979 clock-names = "mdp_core", 980 "iface", 981 "bus", 982 "byte", 983 "pixel", 984 "core"; 985 phys = <&dsi_phy0>; 986 phy-names = "dsi-phy"; 987 988 ports { 989 #address-cells = <1>; 990 #size-cells = <0>; 991 992 port@0 { 993 reg = <0>; 994 dsi0_in: endpoint { 995 remote-endpoint = <&mdp5_intf1_out>; 996 }; 997 }; 998 999 port@1 { 1000 reg = <1>; 1001 dsi0_out: endpoint { 1002 }; 1003 }; 1004 }; 1005 }; 1006 1007 dsi_phy0: dsi-phy@1a98300 { 1008 compatible = "qcom,dsi-phy-28nm-lp"; 1009 reg = <0x1a98300 0xd4>, 1010 <0x1a98500 0x280>, 1011 <0x1a98780 0x30>; 1012 reg-names = "dsi_pll", 1013 "dsi_phy", 1014 "dsi_phy_regulator"; 1015 1016 #clock-cells = <1>; 1017 #phy-cells = <0>; 1018 1019 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1020 <&xo_board>; 1021 clock-names = "iface", "ref"; 1022 }; 1023 }; 1024 1025 1026 hexagon@4080000 { 1027 compatible = "qcom,q6v5-pil"; 1028 reg = <0x04080000 0x100>, 1029 <0x04020000 0x040>; 1030 1031 reg-names = "qdsp6", "rmb"; 1032 1033 interrupts-extended = <&intc 0 24 1>, 1034 <&hexagon_smp2p_in 0 0>, 1035 <&hexagon_smp2p_in 1 0>, 1036 <&hexagon_smp2p_in 2 0>, 1037 <&hexagon_smp2p_in 3 0>; 1038 interrupt-names = "wdog", "fatal", "ready", 1039 "handover", "stop-ack"; 1040 1041 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1042 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1043 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1044 <&xo_board>; 1045 clock-names = "iface", "bus", "mem", "xo"; 1046 1047 qcom,smem-states = <&hexagon_smp2p_out 0>; 1048 qcom,smem-state-names = "stop"; 1049 1050 resets = <&scm 0>; 1051 reset-names = "mss_restart"; 1052 1053 cx-supply = <&pm8916_s1>; 1054 mx-supply = <&pm8916_l3>; 1055 pll-supply = <&pm8916_l7>; 1056 1057 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1058 1059 status = "disabled"; 1060 1061 mba { 1062 memory-region = <&mba_mem>; 1063 }; 1064 1065 mpss { 1066 memory-region = <&mpss_mem>; 1067 }; 1068 1069 smd-edge { 1070 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; 1071 1072 qcom,smd-edge = <0>; 1073 qcom,ipc = <&apcs 8 12>; 1074 qcom,remote-pid = <1>; 1075 1076 label = "hexagon"; 1077 }; 1078 }; 1079 1080 pronto: wcnss@a21b000 { 1081 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1082 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1083 reg-names = "ccu", "dxe", "pmu"; 1084 1085 memory-region = <&wcnss_mem>; 1086 1087 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, 1088 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1089 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1090 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1091 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1092 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1093 1094 vddmx-supply = <&pm8916_l3>; 1095 vddpx-supply = <&pm8916_l7>; 1096 1097 qcom,state = <&wcnss_smp2p_out 0>; 1098 qcom,state-names = "stop"; 1099 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&wcnss_pin_a>; 1102 1103 status = "disabled"; 1104 1105 iris { 1106 compatible = "qcom,wcn3620"; 1107 1108 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1109 clock-names = "xo"; 1110 1111 vddxo-supply = <&pm8916_l7>; 1112 vddrfa-supply = <&pm8916_s3>; 1113 vddpa-supply = <&pm8916_l9>; 1114 vdddig-supply = <&pm8916_l5>; 1115 }; 1116 1117 smd-edge { 1118 interrupts = <0 142 1>; 1119 1120 qcom,ipc = <&apcs 8 17>; 1121 qcom,smd-edge = <6>; 1122 qcom,remote-pid = <4>; 1123 1124 label = "pronto"; 1125 1126 wcnss { 1127 compatible = "qcom,wcnss"; 1128 qcom,smd-channels = "WCNSS_CTRL"; 1129 1130 qcom,mmio = <&pronto>; 1131 1132 bt { 1133 compatible = "qcom,wcnss-bt"; 1134 }; 1135 1136 wifi { 1137 compatible = "qcom,wcnss-wlan"; 1138 1139 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, 1140 <0 146 IRQ_TYPE_LEVEL_HIGH>; 1141 interrupt-names = "tx", "rx"; 1142 1143 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1144 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1145 }; 1146 }; 1147 }; 1148 }; 1149 1150 tpiu@820000 { 1151 compatible = "arm,coresight-tpiu", "arm,primecell"; 1152 reg = <0x820000 0x1000>; 1153 1154 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1155 clock-names = "apb_pclk", "atclk"; 1156 1157 in-ports { 1158 port { 1159 tpiu_in: endpoint { 1160 remote-endpoint = <&replicator_out1>; 1161 }; 1162 }; 1163 }; 1164 }; 1165 1166 funnel@821000 { 1167 compatible = "arm,coresight-funnel", "arm,primecell"; 1168 reg = <0x821000 0x1000>; 1169 1170 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1171 clock-names = "apb_pclk", "atclk"; 1172 1173 in-ports { 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 1177 /* 1178 * Not described input ports: 1179 * 0 - connected to Resource and Power Manger CPU ETM 1180 * 1 - not-connected 1181 * 2 - connected to Modem CPU ETM 1182 * 3 - not-connected 1183 * 5 - not-connected 1184 * 6 - connected trought funnel to Wireless CPU ETM 1185 * 7 - connected to STM component 1186 */ 1187 1188 port@4 { 1189 reg = <4>; 1190 funnel0_in4: endpoint { 1191 remote-endpoint = <&funnel1_out>; 1192 }; 1193 }; 1194 }; 1195 1196 out-ports { 1197 port { 1198 funnel0_out: endpoint { 1199 remote-endpoint = <&etf_in>; 1200 }; 1201 }; 1202 }; 1203 }; 1204 1205 replicator@824000 { 1206 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1207 reg = <0x824000 0x1000>; 1208 1209 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1210 clock-names = "apb_pclk", "atclk"; 1211 1212 out-ports { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 port@0 { 1217 reg = <0>; 1218 replicator_out0: endpoint { 1219 remote-endpoint = <&etr_in>; 1220 }; 1221 }; 1222 port@1 { 1223 reg = <1>; 1224 replicator_out1: endpoint { 1225 remote-endpoint = <&tpiu_in>; 1226 }; 1227 }; 1228 }; 1229 1230 in-ports { 1231 port { 1232 replicator_in: endpoint { 1233 remote-endpoint = <&etf_out>; 1234 }; 1235 }; 1236 }; 1237 }; 1238 1239 etf@825000 { 1240 compatible = "arm,coresight-tmc", "arm,primecell"; 1241 reg = <0x825000 0x1000>; 1242 1243 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1244 clock-names = "apb_pclk", "atclk"; 1245 1246 in-ports { 1247 port { 1248 etf_in: endpoint { 1249 remote-endpoint = <&funnel0_out>; 1250 }; 1251 }; 1252 }; 1253 1254 out-ports { 1255 port { 1256 etf_out: endpoint { 1257 remote-endpoint = <&replicator_in>; 1258 }; 1259 }; 1260 }; 1261 }; 1262 1263 etr@826000 { 1264 compatible = "arm,coresight-tmc", "arm,primecell"; 1265 reg = <0x826000 0x1000>; 1266 1267 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1268 clock-names = "apb_pclk", "atclk"; 1269 1270 in-ports { 1271 port { 1272 etr_in: endpoint { 1273 remote-endpoint = <&replicator_out0>; 1274 }; 1275 }; 1276 }; 1277 }; 1278 1279 funnel@841000 { /* APSS funnel only 4 inputs are used */ 1280 compatible = "arm,coresight-funnel", "arm,primecell"; 1281 reg = <0x841000 0x1000>; 1282 1283 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1284 clock-names = "apb_pclk", "atclk"; 1285 1286 in-ports { 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 1290 port@0 { 1291 reg = <0>; 1292 funnel1_in0: endpoint { 1293 remote-endpoint = <&etm0_out>; 1294 }; 1295 }; 1296 port@1 { 1297 reg = <1>; 1298 funnel1_in1: endpoint { 1299 remote-endpoint = <&etm1_out>; 1300 }; 1301 }; 1302 port@2 { 1303 reg = <2>; 1304 funnel1_in2: endpoint { 1305 remote-endpoint = <&etm2_out>; 1306 }; 1307 }; 1308 port@3 { 1309 reg = <3>; 1310 funnel1_in3: endpoint { 1311 remote-endpoint = <&etm3_out>; 1312 }; 1313 }; 1314 }; 1315 1316 out-ports { 1317 port { 1318 funnel1_out: endpoint { 1319 remote-endpoint = <&funnel0_in4>; 1320 }; 1321 }; 1322 }; 1323 }; 1324 1325 debug@850000 { 1326 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1327 reg = <0x850000 0x1000>; 1328 clocks = <&rpmcc RPM_QDSS_CLK>; 1329 clock-names = "apb_pclk"; 1330 cpu = <&CPU0>; 1331 }; 1332 1333 debug@852000 { 1334 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1335 reg = <0x852000 0x1000>; 1336 clocks = <&rpmcc RPM_QDSS_CLK>; 1337 clock-names = "apb_pclk"; 1338 cpu = <&CPU1>; 1339 }; 1340 1341 debug@854000 { 1342 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1343 reg = <0x854000 0x1000>; 1344 clocks = <&rpmcc RPM_QDSS_CLK>; 1345 clock-names = "apb_pclk"; 1346 cpu = <&CPU2>; 1347 }; 1348 1349 debug@856000 { 1350 compatible = "arm,coresight-cpu-debug","arm,primecell"; 1351 reg = <0x856000 0x1000>; 1352 clocks = <&rpmcc RPM_QDSS_CLK>; 1353 clock-names = "apb_pclk"; 1354 cpu = <&CPU3>; 1355 }; 1356 1357 etm@85c000 { 1358 compatible = "arm,coresight-etm4x", "arm,primecell"; 1359 reg = <0x85c000 0x1000>; 1360 1361 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1362 clock-names = "apb_pclk", "atclk"; 1363 1364 cpu = <&CPU0>; 1365 1366 out-ports { 1367 port { 1368 etm0_out: endpoint { 1369 remote-endpoint = <&funnel1_in0>; 1370 }; 1371 }; 1372 }; 1373 }; 1374 1375 etm@85d000 { 1376 compatible = "arm,coresight-etm4x", "arm,primecell"; 1377 reg = <0x85d000 0x1000>; 1378 1379 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1380 clock-names = "apb_pclk", "atclk"; 1381 1382 cpu = <&CPU1>; 1383 1384 out-ports { 1385 port { 1386 etm1_out: endpoint { 1387 remote-endpoint = <&funnel1_in1>; 1388 }; 1389 }; 1390 }; 1391 }; 1392 1393 etm@85e000 { 1394 compatible = "arm,coresight-etm4x", "arm,primecell"; 1395 reg = <0x85e000 0x1000>; 1396 1397 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1398 clock-names = "apb_pclk", "atclk"; 1399 1400 cpu = <&CPU2>; 1401 1402 out-ports { 1403 port { 1404 etm2_out: endpoint { 1405 remote-endpoint = <&funnel1_in2>; 1406 }; 1407 }; 1408 }; 1409 }; 1410 1411 etm@85f000 { 1412 compatible = "arm,coresight-etm4x", "arm,primecell"; 1413 reg = <0x85f000 0x1000>; 1414 1415 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1416 clock-names = "apb_pclk", "atclk"; 1417 1418 cpu = <&CPU3>; 1419 1420 out-ports { 1421 port { 1422 etm3_out: endpoint { 1423 remote-endpoint = <&funnel1_in3>; 1424 }; 1425 }; 1426 }; 1427 }; 1428 1429 venus: video-codec@1d00000 { 1430 compatible = "qcom,msm8916-venus"; 1431 reg = <0x01d00000 0xff000>; 1432 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1433 power-domains = <&gcc VENUS_GDSC>; 1434 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1435 <&gcc GCC_VENUS0_AHB_CLK>, 1436 <&gcc GCC_VENUS0_AXI_CLK>; 1437 clock-names = "core", "iface", "bus"; 1438 iommus = <&apps_iommu 5>; 1439 memory-region = <&venus_mem>; 1440 status = "okay"; 1441 1442 video-decoder { 1443 compatible = "venus-decoder"; 1444 }; 1445 1446 video-encoder { 1447 compatible = "venus-encoder"; 1448 }; 1449 }; 1450 1451 camss: camss@1b00000 { 1452 compatible = "qcom,msm8916-camss"; 1453 reg = <0x1b0ac00 0x200>, 1454 <0x1b00030 0x4>, 1455 <0x1b0b000 0x200>, 1456 <0x1b00038 0x4>, 1457 <0x1b08000 0x100>, 1458 <0x1b08400 0x100>, 1459 <0x1b0a000 0x500>, 1460 <0x1b00020 0x10>, 1461 <0x1b10000 0x1000>; 1462 reg-names = "csiphy0", 1463 "csiphy0_clk_mux", 1464 "csiphy1", 1465 "csiphy1_clk_mux", 1466 "csid0", 1467 "csid1", 1468 "ispif", 1469 "csi_clk_mux", 1470 "vfe0"; 1471 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1472 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1473 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1474 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1475 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1476 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1477 interrupt-names = "csiphy0", 1478 "csiphy1", 1479 "csid0", 1480 "csid1", 1481 "ispif", 1482 "vfe0"; 1483 power-domains = <&gcc VFE_GDSC>; 1484 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1485 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1486 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1487 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1488 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1489 <&gcc GCC_CAMSS_CSI0_CLK>, 1490 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1491 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1492 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1493 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1494 <&gcc GCC_CAMSS_CSI1_CLK>, 1495 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1496 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1497 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1498 <&gcc GCC_CAMSS_AHB_CLK>, 1499 <&gcc GCC_CAMSS_VFE0_CLK>, 1500 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1501 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1502 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1503 clock-names = "top_ahb", 1504 "ispif_ahb", 1505 "csiphy0_timer", 1506 "csiphy1_timer", 1507 "csi0_ahb", 1508 "csi0", 1509 "csi0_phy", 1510 "csi0_pix", 1511 "csi0_rdi", 1512 "csi1_ahb", 1513 "csi1", 1514 "csi1_phy", 1515 "csi1_pix", 1516 "csi1_rdi", 1517 "ahb", 1518 "vfe0", 1519 "csi_vfe0", 1520 "vfe_ahb", 1521 "vfe_axi"; 1522 vdda-supply = <&pm8916_l2>; 1523 iommus = <&apps_iommu 3>; 1524 status = "disabled"; 1525 ports { 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 }; 1529 }; 1530 }; 1531 1532 smd { 1533 compatible = "qcom,smd"; 1534 1535 rpm { 1536 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 1537 qcom,ipc = <&apcs 8 0>; 1538 qcom,smd-edge = <15>; 1539 1540 rpm_requests { 1541 compatible = "qcom,rpm-msm8916"; 1542 qcom,smd-channels = "rpm_requests"; 1543 1544 rpmcc: qcom,rpmcc { 1545 compatible = "qcom,rpmcc-msm8916"; 1546 #clock-cells = <1>; 1547 }; 1548 1549 smd_rpm_regulators: pm8916-regulators { 1550 compatible = "qcom,rpm-pm8916-regulators"; 1551 1552 pm8916_s1: s1 {}; 1553 pm8916_s3: s3 {}; 1554 pm8916_s4: s4 {}; 1555 1556 pm8916_l1: l1 {}; 1557 pm8916_l2: l2 {}; 1558 pm8916_l3: l3 {}; 1559 pm8916_l4: l4 {}; 1560 pm8916_l5: l5 {}; 1561 pm8916_l6: l6 {}; 1562 pm8916_l7: l7 {}; 1563 pm8916_l8: l8 {}; 1564 pm8916_l9: l9 {}; 1565 pm8916_l10: l10 {}; 1566 pm8916_l11: l11 {}; 1567 pm8916_l12: l12 {}; 1568 pm8916_l13: l13 {}; 1569 pm8916_l14: l14 {}; 1570 pm8916_l15: l15 {}; 1571 pm8916_l16: l16 {}; 1572 pm8916_l17: l17 {}; 1573 pm8916_l18: l18 {}; 1574 }; 1575 }; 1576 }; 1577 }; 1578 1579 hexagon-smp2p { 1580 compatible = "qcom,smp2p"; 1581 qcom,smem = <435>, <428>; 1582 1583 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; 1584 1585 qcom,ipc = <&apcs 8 14>; 1586 1587 qcom,local-pid = <0>; 1588 qcom,remote-pid = <1>; 1589 1590 hexagon_smp2p_out: master-kernel { 1591 qcom,entry-name = "master-kernel"; 1592 1593 #qcom,smem-state-cells = <1>; 1594 }; 1595 1596 hexagon_smp2p_in: slave-kernel { 1597 qcom,entry-name = "slave-kernel"; 1598 1599 interrupt-controller; 1600 #interrupt-cells = <2>; 1601 }; 1602 }; 1603 1604 wcnss-smp2p { 1605 compatible = "qcom,smp2p"; 1606 qcom,smem = <451>, <431>; 1607 1608 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; 1609 1610 qcom,ipc = <&apcs 8 18>; 1611 1612 qcom,local-pid = <0>; 1613 qcom,remote-pid = <4>; 1614 1615 wcnss_smp2p_out: master-kernel { 1616 qcom,entry-name = "master-kernel"; 1617 1618 #qcom,smem-state-cells = <1>; 1619 }; 1620 1621 wcnss_smp2p_in: slave-kernel { 1622 qcom,entry-name = "slave-kernel"; 1623 1624 interrupt-controller; 1625 #interrupt-cells = <2>; 1626 }; 1627 }; 1628 1629 smsm { 1630 compatible = "qcom,smsm"; 1631 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 1635 qcom,ipc-1 = <&apcs 8 13>; 1636 qcom,ipc-3 = <&apcs 8 19>; 1637 1638 apps_smsm: apps@0 { 1639 reg = <0>; 1640 1641 #qcom,smem-state-cells = <1>; 1642 }; 1643 1644 hexagon_smsm: hexagon@1 { 1645 reg = <1>; 1646 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; 1647 1648 interrupt-controller; 1649 #interrupt-cells = <2>; 1650 }; 1651 1652 wcnss_smsm: wcnss@6 { 1653 reg = <6>; 1654 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; 1655 1656 interrupt-controller; 1657 #interrupt-cells = <2>; 1658 }; 1659 }; 1660}; 1661 1662#include "msm8916-pins.dtsi" 1663