1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8996.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,apr.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <19200000>; 28 clock-output-names = "xo_board"; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32764>; 35 clock-output-names = "sleep_clk"; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 cpu-idle-states = <&CPU_SLEEP_0>; 49 capacity-dmips-mhz = <1024>; 50 clocks = <&kryocc 0>; 51 operating-points-v2 = <&cluster0_opp>; 52 #cooling-cells = <2>; 53 next-level-cache = <&L2_0>; 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 }; 58 }; 59 60 CPU1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo"; 63 reg = <0x0 0x1>; 64 enable-method = "psci"; 65 cpu-idle-states = <&CPU_SLEEP_0>; 66 capacity-dmips-mhz = <1024>; 67 clocks = <&kryocc 0>; 68 operating-points-v2 = <&cluster0_opp>; 69 #cooling-cells = <2>; 70 next-level-cache = <&L2_0>; 71 }; 72 73 CPU2: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 cpu-idle-states = <&CPU_SLEEP_0>; 79 capacity-dmips-mhz = <1024>; 80 clocks = <&kryocc 1>; 81 operating-points-v2 = <&cluster1_opp>; 82 #cooling-cells = <2>; 83 next-level-cache = <&L2_1>; 84 L2_1: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 }; 88 }; 89 90 CPU3: cpu@101 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo"; 93 reg = <0x0 0x101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&CPU_SLEEP_0>; 96 capacity-dmips-mhz = <1024>; 97 clocks = <&kryocc 1>; 98 operating-points-v2 = <&cluster1_opp>; 99 #cooling-cells = <2>; 100 next-level-cache = <&L2_1>; 101 }; 102 103 cpu-map { 104 cluster0 { 105 core0 { 106 cpu = <&CPU0>; 107 }; 108 109 core1 { 110 cpu = <&CPU1>; 111 }; 112 }; 113 114 cluster1 { 115 core0 { 116 cpu = <&CPU2>; 117 }; 118 119 core1 { 120 cpu = <&CPU3>; 121 }; 122 }; 123 }; 124 125 idle-states { 126 entry-method = "psci"; 127 128 CPU_SLEEP_0: cpu-sleep-0 { 129 compatible = "arm,idle-state"; 130 idle-state-name = "standalone-power-collapse"; 131 arm,psci-suspend-param = <0x00000004>; 132 entry-latency-us = <130>; 133 exit-latency-us = <80>; 134 min-residency-us = <300>; 135 }; 136 }; 137 }; 138 139 cluster0_opp: opp-table-cluster0 { 140 compatible = "operating-points-v2-kryo-cpu"; 141 nvmem-cells = <&speedbin_efuse>; 142 opp-shared; 143 144 /* Nominal fmax for now */ 145 opp-307200000 { 146 opp-hz = /bits/ 64 <307200000>; 147 opp-supported-hw = <0x77>; 148 clock-latency-ns = <200000>; 149 }; 150 opp-422400000 { 151 opp-hz = /bits/ 64 <422400000>; 152 opp-supported-hw = <0x77>; 153 clock-latency-ns = <200000>; 154 }; 155 opp-480000000 { 156 opp-hz = /bits/ 64 <480000000>; 157 opp-supported-hw = <0x77>; 158 clock-latency-ns = <200000>; 159 }; 160 opp-556800000 { 161 opp-hz = /bits/ 64 <556800000>; 162 opp-supported-hw = <0x77>; 163 clock-latency-ns = <200000>; 164 }; 165 opp-652800000 { 166 opp-hz = /bits/ 64 <652800000>; 167 opp-supported-hw = <0x77>; 168 clock-latency-ns = <200000>; 169 }; 170 opp-729600000 { 171 opp-hz = /bits/ 64 <729600000>; 172 opp-supported-hw = <0x77>; 173 clock-latency-ns = <200000>; 174 }; 175 opp-844800000 { 176 opp-hz = /bits/ 64 <844800000>; 177 opp-supported-hw = <0x77>; 178 clock-latency-ns = <200000>; 179 }; 180 opp-960000000 { 181 opp-hz = /bits/ 64 <960000000>; 182 opp-supported-hw = <0x77>; 183 clock-latency-ns = <200000>; 184 }; 185 opp-1036800000 { 186 opp-hz = /bits/ 64 <1036800000>; 187 opp-supported-hw = <0x77>; 188 clock-latency-ns = <200000>; 189 }; 190 opp-1113600000 { 191 opp-hz = /bits/ 64 <1113600000>; 192 opp-supported-hw = <0x77>; 193 clock-latency-ns = <200000>; 194 }; 195 opp-1190400000 { 196 opp-hz = /bits/ 64 <1190400000>; 197 opp-supported-hw = <0x77>; 198 clock-latency-ns = <200000>; 199 }; 200 opp-1228800000 { 201 opp-hz = /bits/ 64 <1228800000>; 202 opp-supported-hw = <0x77>; 203 clock-latency-ns = <200000>; 204 }; 205 opp-1324800000 { 206 opp-hz = /bits/ 64 <1324800000>; 207 opp-supported-hw = <0x77>; 208 clock-latency-ns = <200000>; 209 }; 210 opp-1401600000 { 211 opp-hz = /bits/ 64 <1401600000>; 212 opp-supported-hw = <0x77>; 213 clock-latency-ns = <200000>; 214 }; 215 opp-1478400000 { 216 opp-hz = /bits/ 64 <1478400000>; 217 opp-supported-hw = <0x77>; 218 clock-latency-ns = <200000>; 219 }; 220 opp-1593600000 { 221 opp-hz = /bits/ 64 <1593600000>; 222 opp-supported-hw = <0x77>; 223 clock-latency-ns = <200000>; 224 }; 225 }; 226 227 cluster1_opp: opp-table-cluster1 { 228 compatible = "operating-points-v2-kryo-cpu"; 229 nvmem-cells = <&speedbin_efuse>; 230 opp-shared; 231 232 /* Nominal fmax for now */ 233 opp-307200000 { 234 opp-hz = /bits/ 64 <307200000>; 235 opp-supported-hw = <0x77>; 236 clock-latency-ns = <200000>; 237 }; 238 opp-403200000 { 239 opp-hz = /bits/ 64 <403200000>; 240 opp-supported-hw = <0x77>; 241 clock-latency-ns = <200000>; 242 }; 243 opp-480000000 { 244 opp-hz = /bits/ 64 <480000000>; 245 opp-supported-hw = <0x77>; 246 clock-latency-ns = <200000>; 247 }; 248 opp-556800000 { 249 opp-hz = /bits/ 64 <556800000>; 250 opp-supported-hw = <0x77>; 251 clock-latency-ns = <200000>; 252 }; 253 opp-652800000 { 254 opp-hz = /bits/ 64 <652800000>; 255 opp-supported-hw = <0x77>; 256 clock-latency-ns = <200000>; 257 }; 258 opp-729600000 { 259 opp-hz = /bits/ 64 <729600000>; 260 opp-supported-hw = <0x77>; 261 clock-latency-ns = <200000>; 262 }; 263 opp-806400000 { 264 opp-hz = /bits/ 64 <806400000>; 265 opp-supported-hw = <0x77>; 266 clock-latency-ns = <200000>; 267 }; 268 opp-883200000 { 269 opp-hz = /bits/ 64 <883200000>; 270 opp-supported-hw = <0x77>; 271 clock-latency-ns = <200000>; 272 }; 273 opp-940800000 { 274 opp-hz = /bits/ 64 <940800000>; 275 opp-supported-hw = <0x77>; 276 clock-latency-ns = <200000>; 277 }; 278 opp-1036800000 { 279 opp-hz = /bits/ 64 <1036800000>; 280 opp-supported-hw = <0x77>; 281 clock-latency-ns = <200000>; 282 }; 283 opp-1113600000 { 284 opp-hz = /bits/ 64 <1113600000>; 285 opp-supported-hw = <0x77>; 286 clock-latency-ns = <200000>; 287 }; 288 opp-1190400000 { 289 opp-hz = /bits/ 64 <1190400000>; 290 opp-supported-hw = <0x77>; 291 clock-latency-ns = <200000>; 292 }; 293 opp-1248000000 { 294 opp-hz = /bits/ 64 <1248000000>; 295 opp-supported-hw = <0x77>; 296 clock-latency-ns = <200000>; 297 }; 298 opp-1324800000 { 299 opp-hz = /bits/ 64 <1324800000>; 300 opp-supported-hw = <0x77>; 301 clock-latency-ns = <200000>; 302 }; 303 opp-1401600000 { 304 opp-hz = /bits/ 64 <1401600000>; 305 opp-supported-hw = <0x77>; 306 clock-latency-ns = <200000>; 307 }; 308 opp-1478400000 { 309 opp-hz = /bits/ 64 <1478400000>; 310 opp-supported-hw = <0x77>; 311 clock-latency-ns = <200000>; 312 }; 313 opp-1555200000 { 314 opp-hz = /bits/ 64 <1555200000>; 315 opp-supported-hw = <0x77>; 316 clock-latency-ns = <200000>; 317 }; 318 opp-1632000000 { 319 opp-hz = /bits/ 64 <1632000000>; 320 opp-supported-hw = <0x77>; 321 clock-latency-ns = <200000>; 322 }; 323 opp-1708800000 { 324 opp-hz = /bits/ 64 <1708800000>; 325 opp-supported-hw = <0x77>; 326 clock-latency-ns = <200000>; 327 }; 328 opp-1785600000 { 329 opp-hz = /bits/ 64 <1785600000>; 330 opp-supported-hw = <0x77>; 331 clock-latency-ns = <200000>; 332 }; 333 opp-1824000000 { 334 opp-hz = /bits/ 64 <1824000000>; 335 opp-supported-hw = <0x77>; 336 clock-latency-ns = <200000>; 337 }; 338 opp-1920000000 { 339 opp-hz = /bits/ 64 <1920000000>; 340 opp-supported-hw = <0x77>; 341 clock-latency-ns = <200000>; 342 }; 343 opp-1996800000 { 344 opp-hz = /bits/ 64 <1996800000>; 345 opp-supported-hw = <0x77>; 346 clock-latency-ns = <200000>; 347 }; 348 opp-2073600000 { 349 opp-hz = /bits/ 64 <2073600000>; 350 opp-supported-hw = <0x77>; 351 clock-latency-ns = <200000>; 352 }; 353 opp-2150400000 { 354 opp-hz = /bits/ 64 <2150400000>; 355 opp-supported-hw = <0x77>; 356 clock-latency-ns = <200000>; 357 }; 358 }; 359 360 firmware { 361 scm { 362 compatible = "qcom,scm-msm8996", "qcom,scm"; 363 qcom,dload-mode = <&tcsr_2 0x13000>; 364 }; 365 }; 366 367 memory@80000000 { 368 device_type = "memory"; 369 /* We expect the bootloader to fill in the reg */ 370 reg = <0x0 0x80000000 0x0 0x0>; 371 }; 372 373 psci { 374 compatible = "arm,psci-1.0"; 375 method = "smc"; 376 }; 377 378 reserved-memory { 379 #address-cells = <2>; 380 #size-cells = <2>; 381 ranges; 382 383 hyp_mem: memory@85800000 { 384 reg = <0x0 0x85800000 0x0 0x600000>; 385 no-map; 386 }; 387 388 xbl_mem: memory@85e00000 { 389 reg = <0x0 0x85e00000 0x0 0x200000>; 390 no-map; 391 }; 392 393 smem_mem: smem-mem@86000000 { 394 reg = <0x0 0x86000000 0x0 0x200000>; 395 no-map; 396 }; 397 398 tz_mem: memory@86200000 { 399 reg = <0x0 0x86200000 0x0 0x2600000>; 400 no-map; 401 }; 402 403 rmtfs_mem: rmtfs { 404 compatible = "qcom,rmtfs-mem"; 405 406 size = <0x0 0x200000>; 407 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 408 no-map; 409 410 qcom,client-id = <1>; 411 qcom,vmid = <15>; 412 }; 413 414 mpss_mem: mpss@88800000 { 415 reg = <0x0 0x88800000 0x0 0x6200000>; 416 no-map; 417 }; 418 419 adsp_mem: adsp@8ea00000 { 420 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 421 no-map; 422 }; 423 424 slpi_mem: slpi@90500000 { 425 reg = <0x0 0x90500000 0x0 0xa00000>; 426 no-map; 427 }; 428 429 gpu_mem: gpu@90f00000 { 430 compatible = "shared-dma-pool"; 431 reg = <0x0 0x90f00000 0x0 0x100000>; 432 no-map; 433 }; 434 435 venus_mem: venus@91000000 { 436 reg = <0x0 0x91000000 0x0 0x500000>; 437 no-map; 438 }; 439 440 mba_mem: mba@91500000 { 441 reg = <0x0 0x91500000 0x0 0x200000>; 442 no-map; 443 }; 444 }; 445 446 rpm-glink { 447 compatible = "qcom,glink-rpm"; 448 449 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 450 451 qcom,rpm-msg-ram = <&rpm_msg_ram>; 452 453 mboxes = <&apcs_glb 0>; 454 455 rpm_requests: rpm-requests { 456 compatible = "qcom,rpm-msm8996"; 457 qcom,glink-channels = "rpm_requests"; 458 459 rpmcc: qcom,rpmcc { 460 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 461 #clock-cells = <1>; 462 clocks = <&xo_board>; 463 clock-names = "xo"; 464 }; 465 466 rpmpd: power-controller { 467 compatible = "qcom,msm8996-rpmpd"; 468 #power-domain-cells = <1>; 469 operating-points-v2 = <&rpmpd_opp_table>; 470 471 rpmpd_opp_table: opp-table { 472 compatible = "operating-points-v2"; 473 474 rpmpd_opp1: opp1 { 475 opp-level = <1>; 476 }; 477 478 rpmpd_opp2: opp2 { 479 opp-level = <2>; 480 }; 481 482 rpmpd_opp3: opp3 { 483 opp-level = <3>; 484 }; 485 486 rpmpd_opp4: opp4 { 487 opp-level = <4>; 488 }; 489 490 rpmpd_opp5: opp5 { 491 opp-level = <5>; 492 }; 493 494 rpmpd_opp6: opp6 { 495 opp-level = <6>; 496 }; 497 }; 498 }; 499 }; 500 }; 501 502 smem { 503 compatible = "qcom,smem"; 504 memory-region = <&smem_mem>; 505 hwlocks = <&tcsr_mutex 3>; 506 }; 507 508 smp2p-adsp { 509 compatible = "qcom,smp2p"; 510 qcom,smem = <443>, <429>; 511 512 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 513 514 mboxes = <&apcs_glb 10>; 515 516 qcom,local-pid = <0>; 517 qcom,remote-pid = <2>; 518 519 adsp_smp2p_out: master-kernel { 520 qcom,entry-name = "master-kernel"; 521 #qcom,smem-state-cells = <1>; 522 }; 523 524 adsp_smp2p_in: slave-kernel { 525 qcom,entry-name = "slave-kernel"; 526 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 }; 531 532 smp2p-mpss { 533 compatible = "qcom,smp2p"; 534 qcom,smem = <435>, <428>; 535 536 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 537 538 mboxes = <&apcs_glb 14>; 539 540 qcom,local-pid = <0>; 541 qcom,remote-pid = <1>; 542 543 mpss_smp2p_out: master-kernel { 544 qcom,entry-name = "master-kernel"; 545 #qcom,smem-state-cells = <1>; 546 }; 547 548 mpss_smp2p_in: slave-kernel { 549 qcom,entry-name = "slave-kernel"; 550 551 interrupt-controller; 552 #interrupt-cells = <2>; 553 }; 554 }; 555 556 smp2p-slpi { 557 compatible = "qcom,smp2p"; 558 qcom,smem = <481>, <430>; 559 560 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 561 562 mboxes = <&apcs_glb 26>; 563 564 qcom,local-pid = <0>; 565 qcom,remote-pid = <3>; 566 567 slpi_smp2p_out: master-kernel { 568 qcom,entry-name = "master-kernel"; 569 #qcom,smem-state-cells = <1>; 570 }; 571 572 slpi_smp2p_in: slave-kernel { 573 qcom,entry-name = "slave-kernel"; 574 575 interrupt-controller; 576 #interrupt-cells = <2>; 577 }; 578 }; 579 580 soc: soc { 581 #address-cells = <1>; 582 #size-cells = <1>; 583 ranges = <0 0 0 0xffffffff>; 584 compatible = "simple-bus"; 585 586 pcie_phy: phy-wrapper@34000 { 587 compatible = "qcom,msm8996-qmp-pcie-phy"; 588 reg = <0x00034000 0x488>; 589 #address-cells = <1>; 590 #size-cells = <1>; 591 ranges = <0x0 0x00034000 0x4000>; 592 593 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 594 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 595 <&gcc GCC_PCIE_CLKREF_CLK>; 596 clock-names = "aux", "cfg_ahb", "ref"; 597 598 resets = <&gcc GCC_PCIE_PHY_BCR>, 599 <&gcc GCC_PCIE_PHY_COM_BCR>, 600 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 601 reset-names = "phy", "common", "cfg"; 602 603 status = "disabled"; 604 605 pciephy_0: phy@1000 { 606 reg = <0x1000 0x130>, 607 <0x1200 0x200>, 608 <0x1400 0x1dc>; 609 610 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 611 clock-names = "pipe0"; 612 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 613 reset-names = "lane0"; 614 615 #clock-cells = <0>; 616 clock-output-names = "pcie_0_pipe_clk_src"; 617 618 #phy-cells = <0>; 619 }; 620 621 pciephy_1: phy@2000 { 622 reg = <0x2000 0x130>, 623 <0x2200 0x200>, 624 <0x2400 0x1dc>; 625 626 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 627 clock-names = "pipe1"; 628 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 629 reset-names = "lane1"; 630 631 #clock-cells = <0>; 632 clock-output-names = "pcie_1_pipe_clk_src"; 633 634 #phy-cells = <0>; 635 }; 636 637 pciephy_2: phy@3000 { 638 reg = <0x3000 0x130>, 639 <0x3200 0x200>, 640 <0x3400 0x1dc>; 641 642 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 643 clock-names = "pipe2"; 644 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 645 reset-names = "lane2"; 646 647 #clock-cells = <0>; 648 clock-output-names = "pcie_2_pipe_clk_src"; 649 650 #phy-cells = <0>; 651 }; 652 }; 653 654 rpm_msg_ram: sram@68000 { 655 compatible = "qcom,rpm-msg-ram"; 656 reg = <0x00068000 0x6000>; 657 }; 658 659 qfprom@74000 { 660 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 661 reg = <0x00074000 0x8ff>; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 665 qusb2p_hstx_trim: hstx_trim@24e { 666 reg = <0x24e 0x2>; 667 bits = <5 4>; 668 }; 669 670 qusb2s_hstx_trim: hstx_trim@24f { 671 reg = <0x24f 0x1>; 672 bits = <1 4>; 673 }; 674 675 speedbin_efuse: speedbin@133 { 676 reg = <0x133 0x1>; 677 bits = <5 3>; 678 }; 679 }; 680 681 rng: rng@83000 { 682 compatible = "qcom,prng-ee"; 683 reg = <0x00083000 0x1000>; 684 clocks = <&gcc GCC_PRNG_AHB_CLK>; 685 clock-names = "core"; 686 }; 687 688 gcc: clock-controller@300000 { 689 compatible = "qcom,gcc-msm8996"; 690 #clock-cells = <1>; 691 #reset-cells = <1>; 692 #power-domain-cells = <1>; 693 reg = <0x00300000 0x90000>; 694 695 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 696 <&rpmcc RPM_SMD_LN_BB_CLK>, 697 <&sleep_clk>, 698 <&pciephy_0>, 699 <&pciephy_1>, 700 <&pciephy_2>, 701 <&ssusb_phy_0>, 702 <0>, <0>, <0>; 703 clock-names = "cxo", 704 "cxo2", 705 "sleep_clk", 706 "pcie_0_pipe_clk_src", 707 "pcie_1_pipe_clk_src", 708 "pcie_2_pipe_clk_src", 709 "usb3_phy_pipe_clk_src", 710 "ufs_rx_symbol_0_clk_src", 711 "ufs_rx_symbol_1_clk_src", 712 "ufs_tx_symbol_0_clk_src"; 713 }; 714 715 bimc: interconnect@408000 { 716 compatible = "qcom,msm8996-bimc"; 717 reg = <0x00408000 0x5a000>; 718 #interconnect-cells = <1>; 719 clock-names = "bus", "bus_a"; 720 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 721 <&rpmcc RPM_SMD_BIMC_A_CLK>; 722 }; 723 724 tsens0: thermal-sensor@4a9000 { 725 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 726 reg = <0x004a9000 0x1000>, /* TM */ 727 <0x004a8000 0x1000>; /* SROT */ 728 #qcom,sensors = <13>; 729 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "uplow", "critical"; 732 #thermal-sensor-cells = <1>; 733 }; 734 735 tsens1: thermal-sensor@4ad000 { 736 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 737 reg = <0x004ad000 0x1000>, /* TM */ 738 <0x004ac000 0x1000>; /* SROT */ 739 #qcom,sensors = <8>; 740 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 742 interrupt-names = "uplow", "critical"; 743 #thermal-sensor-cells = <1>; 744 }; 745 746 cryptobam: dma-controller@644000 { 747 compatible = "qcom,bam-v1.7.0"; 748 reg = <0x00644000 0x24000>; 749 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&gcc GCC_CE1_CLK>; 751 clock-names = "bam_clk"; 752 #dma-cells = <1>; 753 qcom,ee = <0>; 754 qcom,controlled-remotely; 755 }; 756 757 crypto: crypto@67a000 { 758 compatible = "qcom,crypto-v5.4"; 759 reg = <0x0067a000 0x6000>; 760 clocks = <&gcc GCC_CE1_AHB_CLK>, 761 <&gcc GCC_CE1_AXI_CLK>, 762 <&gcc GCC_CE1_CLK>; 763 clock-names = "iface", "bus", "core"; 764 dmas = <&cryptobam 6>, <&cryptobam 7>; 765 dma-names = "rx", "tx"; 766 }; 767 768 cnoc: interconnect@500000 { 769 compatible = "qcom,msm8996-cnoc"; 770 reg = <0x00500000 0x1000>; 771 #interconnect-cells = <1>; 772 clock-names = "bus", "bus_a"; 773 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 774 <&rpmcc RPM_SMD_CNOC_A_CLK>; 775 }; 776 777 snoc: interconnect@524000 { 778 compatible = "qcom,msm8996-snoc"; 779 reg = <0x00524000 0x1c000>; 780 #interconnect-cells = <1>; 781 clock-names = "bus", "bus_a"; 782 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 783 <&rpmcc RPM_SMD_SNOC_A_CLK>; 784 }; 785 786 a0noc: interconnect@543000 { 787 compatible = "qcom,msm8996-a0noc"; 788 reg = <0x00543000 0x6000>; 789 #interconnect-cells = <1>; 790 clock-names = "aggre0_snoc_axi", 791 "aggre0_cnoc_ahb", 792 "aggre0_noc_mpu_cfg"; 793 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 794 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 795 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 796 power-domains = <&gcc AGGRE0_NOC_GDSC>; 797 }; 798 799 a1noc: interconnect@562000 { 800 compatible = "qcom,msm8996-a1noc"; 801 reg = <0x00562000 0x5000>; 802 #interconnect-cells = <1>; 803 clock-names = "bus", "bus_a"; 804 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 805 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 806 }; 807 808 a2noc: interconnect@583000 { 809 compatible = "qcom,msm8996-a2noc"; 810 reg = <0x00583000 0x7000>; 811 #interconnect-cells = <1>; 812 clock-names = "bus", "bus_a"; 813 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 814 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; 815 }; 816 817 mnoc: interconnect@5a4000 { 818 compatible = "qcom,msm8996-mnoc"; 819 reg = <0x005a4000 0x1c000>; 820 #interconnect-cells = <1>; 821 clock-names = "bus", "bus_a", "iface"; 822 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 823 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 824 <&mmcc AHB_CLK_SRC>; 825 }; 826 827 pnoc: interconnect@5c0000 { 828 compatible = "qcom,msm8996-pnoc"; 829 reg = <0x005c0000 0x3000>; 830 #interconnect-cells = <1>; 831 clock-names = "bus", "bus_a"; 832 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 833 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 834 }; 835 836 tcsr_mutex: hwlock@740000 { 837 compatible = "qcom,tcsr-mutex"; 838 reg = <0x00740000 0x20000>; 839 #hwlock-cells = <1>; 840 }; 841 842 tcsr_1: syscon@760000 { 843 compatible = "qcom,tcsr-msm8996", "syscon"; 844 reg = <0x00760000 0x20000>; 845 }; 846 847 tcsr_2: syscon@7a0000 { 848 compatible = "qcom,tcsr-msm8996", "syscon"; 849 reg = <0x007a0000 0x18000>; 850 }; 851 852 mmcc: clock-controller@8c0000 { 853 compatible = "qcom,mmcc-msm8996"; 854 #clock-cells = <1>; 855 #reset-cells = <1>; 856 #power-domain-cells = <1>; 857 reg = <0x008c0000 0x40000>; 858 clocks = <&xo_board>, 859 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 860 <&gcc GPLL0>, 861 <&dsi0_phy 1>, 862 <&dsi0_phy 0>, 863 <0>, 864 <0>, 865 <0>; 866 clock-names = "xo", 867 "gcc_mmss_noc_cfg_ahb_clk", 868 "gpll0", 869 "dsi0pll", 870 "dsi0pllbyte", 871 "dsi1pll", 872 "dsi1pllbyte", 873 "hdmipll"; 874 assigned-clocks = <&mmcc MMPLL9_PLL>, 875 <&mmcc MMPLL1_PLL>, 876 <&mmcc MMPLL3_PLL>, 877 <&mmcc MMPLL4_PLL>, 878 <&mmcc MMPLL5_PLL>; 879 assigned-clock-rates = <624000000>, 880 <810000000>, 881 <980000000>, 882 <960000000>, 883 <825000000>; 884 }; 885 886 mdss: mdss@900000 { 887 compatible = "qcom,mdss"; 888 889 reg = <0x00900000 0x1000>, 890 <0x009b0000 0x1040>, 891 <0x009b8000 0x1040>; 892 reg-names = "mdss_phys", 893 "vbif_phys", 894 "vbif_nrt_phys"; 895 896 power-domains = <&mmcc MDSS_GDSC>; 897 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 898 899 interrupt-controller; 900 #interrupt-cells = <1>; 901 902 clocks = <&mmcc MDSS_AHB_CLK>, 903 <&mmcc MDSS_MDP_CLK>; 904 clock-names = "iface", "core"; 905 906 #address-cells = <1>; 907 #size-cells = <1>; 908 ranges; 909 910 status = "disabled"; 911 912 mdp: mdp@901000 { 913 compatible = "qcom,mdp5"; 914 reg = <0x00901000 0x90000>; 915 reg-names = "mdp_phys"; 916 917 interrupt-parent = <&mdss>; 918 interrupts = <0>; 919 920 clocks = <&mmcc MDSS_AHB_CLK>, 921 <&mmcc MDSS_AXI_CLK>, 922 <&mmcc MDSS_MDP_CLK>, 923 <&mmcc SMMU_MDP_AXI_CLK>, 924 <&mmcc MDSS_VSYNC_CLK>; 925 clock-names = "iface", 926 "bus", 927 "core", 928 "iommu", 929 "vsync"; 930 931 iommus = <&mdp_smmu 0>; 932 933 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 934 <&mmcc MDSS_VSYNC_CLK>; 935 assigned-clock-rates = <300000000>, 936 <19200000>; 937 938 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 939 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 940 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 941 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 942 943 ports { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 947 port@0 { 948 reg = <0>; 949 mdp5_intf3_out: endpoint { 950 remote-endpoint = <&hdmi_in>; 951 }; 952 }; 953 954 port@1 { 955 reg = <1>; 956 mdp5_intf1_out: endpoint { 957 remote-endpoint = <&dsi0_in>; 958 }; 959 }; 960 961 port@2 { 962 reg = <2>; 963 mdp5_intf2_out: endpoint { 964 remote-endpoint = <&dsi1_in>; 965 }; 966 }; 967 }; 968 }; 969 970 dsi0: dsi@994000 { 971 compatible = "qcom,mdss-dsi-ctrl"; 972 reg = <0x00994000 0x400>; 973 reg-names = "dsi_ctrl"; 974 975 interrupt-parent = <&mdss>; 976 interrupts = <4>; 977 978 clocks = <&mmcc MDSS_MDP_CLK>, 979 <&mmcc MDSS_BYTE0_CLK>, 980 <&mmcc MDSS_AHB_CLK>, 981 <&mmcc MDSS_AXI_CLK>, 982 <&mmcc MMSS_MISC_AHB_CLK>, 983 <&mmcc MDSS_PCLK0_CLK>, 984 <&mmcc MDSS_ESC0_CLK>; 985 clock-names = "mdp_core", 986 "byte", 987 "iface", 988 "bus", 989 "core_mmss", 990 "pixel", 991 "core"; 992 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 993 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 994 995 phys = <&dsi0_phy>; 996 phy-names = "dsi"; 997 status = "disabled"; 998 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 ports { 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 1006 port@0 { 1007 reg = <0>; 1008 dsi0_in: endpoint { 1009 remote-endpoint = <&mdp5_intf1_out>; 1010 }; 1011 }; 1012 1013 port@1 { 1014 reg = <1>; 1015 dsi0_out: endpoint { 1016 }; 1017 }; 1018 }; 1019 }; 1020 1021 dsi0_phy: dsi-phy@994400 { 1022 compatible = "qcom,dsi-phy-14nm"; 1023 reg = <0x00994400 0x100>, 1024 <0x00994500 0x300>, 1025 <0x00994800 0x188>; 1026 reg-names = "dsi_phy", 1027 "dsi_phy_lane", 1028 "dsi_pll"; 1029 1030 #clock-cells = <1>; 1031 #phy-cells = <0>; 1032 1033 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1034 clock-names = "iface", "ref"; 1035 status = "disabled"; 1036 }; 1037 1038 dsi1: dsi@996000 { 1039 compatible = "qcom,mdss-dsi-ctrl"; 1040 reg = <0x00996000 0x400>; 1041 reg-names = "dsi_ctrl"; 1042 1043 interrupt-parent = <&mdss>; 1044 interrupts = <4>; 1045 1046 clocks = <&mmcc MDSS_MDP_CLK>, 1047 <&mmcc MDSS_BYTE1_CLK>, 1048 <&mmcc MDSS_AHB_CLK>, 1049 <&mmcc MDSS_AXI_CLK>, 1050 <&mmcc MMSS_MISC_AHB_CLK>, 1051 <&mmcc MDSS_PCLK1_CLK>, 1052 <&mmcc MDSS_ESC1_CLK>; 1053 clock-names = "mdp_core", 1054 "byte", 1055 "iface", 1056 "bus", 1057 "core_mmss", 1058 "pixel", 1059 "core"; 1060 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1061 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1062 1063 phys = <&dsi1_phy>; 1064 phy-names = "dsi"; 1065 status = "disabled"; 1066 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 1070 ports { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 port@0 { 1075 reg = <0>; 1076 dsi1_in: endpoint { 1077 remote-endpoint = <&mdp5_intf2_out>; 1078 }; 1079 }; 1080 1081 port@1 { 1082 reg = <1>; 1083 dsi1_out: endpoint { 1084 }; 1085 }; 1086 }; 1087 }; 1088 1089 dsi1_phy: dsi-phy@996400 { 1090 compatible = "qcom,dsi-phy-14nm"; 1091 reg = <0x00996400 0x100>, 1092 <0x00996500 0x300>, 1093 <0x00996800 0x188>; 1094 reg-names = "dsi_phy", 1095 "dsi_phy_lane", 1096 "dsi_pll"; 1097 1098 #clock-cells = <1>; 1099 #phy-cells = <0>; 1100 1101 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1102 clock-names = "iface", "ref"; 1103 status = "disabled"; 1104 }; 1105 1106 hdmi: hdmi-tx@9a0000 { 1107 compatible = "qcom,hdmi-tx-8996"; 1108 reg = <0x009a0000 0x50c>, 1109 <0x00070000 0x6158>, 1110 <0x009e0000 0xfff>; 1111 reg-names = "core_physical", 1112 "qfprom_physical", 1113 "hdcp_physical"; 1114 1115 interrupt-parent = <&mdss>; 1116 interrupts = <8>; 1117 1118 clocks = <&mmcc MDSS_MDP_CLK>, 1119 <&mmcc MDSS_AHB_CLK>, 1120 <&mmcc MDSS_HDMI_CLK>, 1121 <&mmcc MDSS_HDMI_AHB_CLK>, 1122 <&mmcc MDSS_EXTPCLK_CLK>; 1123 clock-names = 1124 "mdp_core", 1125 "iface", 1126 "core", 1127 "alt_iface", 1128 "extp"; 1129 1130 phys = <&hdmi_phy>; 1131 #sound-dai-cells = <1>; 1132 1133 status = "disabled"; 1134 1135 ports { 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 1139 port@0 { 1140 reg = <0>; 1141 hdmi_in: endpoint { 1142 remote-endpoint = <&mdp5_intf3_out>; 1143 }; 1144 }; 1145 }; 1146 }; 1147 1148 hdmi_phy: hdmi-phy@9a0600 { 1149 #phy-cells = <0>; 1150 compatible = "qcom,hdmi-phy-8996"; 1151 reg = <0x009a0600 0x1c4>, 1152 <0x009a0a00 0x124>, 1153 <0x009a0c00 0x124>, 1154 <0x009a0e00 0x124>, 1155 <0x009a1000 0x124>, 1156 <0x009a1200 0x0c8>; 1157 reg-names = "hdmi_pll", 1158 "hdmi_tx_l0", 1159 "hdmi_tx_l1", 1160 "hdmi_tx_l2", 1161 "hdmi_tx_l3", 1162 "hdmi_phy"; 1163 1164 clocks = <&mmcc MDSS_AHB_CLK>, 1165 <&gcc GCC_HDMI_CLKREF_CLK>, 1166 <&xo_board>; 1167 clock-names = "iface", 1168 "ref", 1169 "xo"; 1170 1171 #clock-cells = <0>; 1172 1173 status = "disabled"; 1174 }; 1175 }; 1176 1177 gpu: gpu@b00000 { 1178 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1179 1180 reg = <0x00b00000 0x3f000>; 1181 reg-names = "kgsl_3d0_reg_memory"; 1182 1183 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1184 1185 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1186 <&mmcc GPU_AHB_CLK>, 1187 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1188 <&gcc GCC_BIMC_GFX_CLK>, 1189 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1190 1191 clock-names = "core", 1192 "iface", 1193 "rbbmtimer", 1194 "mem", 1195 "mem_iface"; 1196 1197 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1198 interconnect-names = "gfx-mem"; 1199 1200 power-domains = <&mmcc GPU_GX_GDSC>; 1201 iommus = <&adreno_smmu 0>; 1202 1203 nvmem-cells = <&speedbin_efuse>; 1204 nvmem-cell-names = "speed_bin"; 1205 1206 operating-points-v2 = <&gpu_opp_table>; 1207 1208 status = "disabled"; 1209 1210 #cooling-cells = <2>; 1211 1212 gpu_opp_table: opp-table { 1213 compatible = "operating-points-v2"; 1214 1215 /* 1216 * 624Mhz and 560Mhz are only available on speed 1217 * bin (1 << 0). All the rest are available on 1218 * all bins of the hardware 1219 */ 1220 opp-624000000 { 1221 opp-hz = /bits/ 64 <624000000>; 1222 opp-supported-hw = <0x01>; 1223 }; 1224 opp-560000000 { 1225 opp-hz = /bits/ 64 <560000000>; 1226 opp-supported-hw = <0x01>; 1227 }; 1228 opp-510000000 { 1229 opp-hz = /bits/ 64 <510000000>; 1230 opp-supported-hw = <0xFF>; 1231 }; 1232 opp-401800000 { 1233 opp-hz = /bits/ 64 <401800000>; 1234 opp-supported-hw = <0xFF>; 1235 }; 1236 opp-315000000 { 1237 opp-hz = /bits/ 64 <315000000>; 1238 opp-supported-hw = <0xFF>; 1239 }; 1240 opp-214000000 { 1241 opp-hz = /bits/ 64 <214000000>; 1242 opp-supported-hw = <0xFF>; 1243 }; 1244 opp-133000000 { 1245 opp-hz = /bits/ 64 <133000000>; 1246 opp-supported-hw = <0xFF>; 1247 }; 1248 }; 1249 1250 zap-shader { 1251 memory-region = <&gpu_mem>; 1252 }; 1253 }; 1254 1255 tlmm: pinctrl@1010000 { 1256 compatible = "qcom,msm8996-pinctrl"; 1257 reg = <0x01010000 0x300000>; 1258 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1259 gpio-controller; 1260 gpio-ranges = <&tlmm 0 0 150>; 1261 #gpio-cells = <2>; 1262 interrupt-controller; 1263 #interrupt-cells = <2>; 1264 1265 blsp1_spi1_default: blsp1-spi1-default { 1266 spi { 1267 pins = "gpio0", "gpio1", "gpio3"; 1268 function = "blsp_spi1"; 1269 drive-strength = <12>; 1270 bias-disable; 1271 }; 1272 1273 cs { 1274 pins = "gpio2"; 1275 function = "gpio"; 1276 drive-strength = <16>; 1277 bias-disable; 1278 output-high; 1279 }; 1280 }; 1281 1282 blsp1_spi1_sleep: blsp1-spi1-sleep { 1283 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1284 function = "gpio"; 1285 drive-strength = <2>; 1286 bias-pull-down; 1287 }; 1288 1289 blsp2_uart2_2pins_default: blsp2-uart1-2pins { 1290 pins = "gpio4", "gpio5"; 1291 function = "blsp_uart8"; 1292 drive-strength = <16>; 1293 bias-disable; 1294 }; 1295 1296 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { 1297 pins = "gpio4", "gpio5"; 1298 function = "gpio"; 1299 drive-strength = <2>; 1300 bias-disable; 1301 }; 1302 1303 blsp2_i2c2_default: blsp2-i2c2 { 1304 pins = "gpio6", "gpio7"; 1305 function = "blsp_i2c8"; 1306 drive-strength = <16>; 1307 bias-disable; 1308 }; 1309 1310 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1311 pins = "gpio6", "gpio7"; 1312 function = "gpio"; 1313 drive-strength = <2>; 1314 bias-disable; 1315 }; 1316 1317 cci0_default: cci0-default { 1318 pins = "gpio17", "gpio18"; 1319 function = "cci_i2c"; 1320 drive-strength = <16>; 1321 bias-disable; 1322 }; 1323 1324 camera0_state_on: 1325 camera_rear_default: camera-rear-default { 1326 camera0_mclk: mclk0 { 1327 pins = "gpio13"; 1328 function = "cam_mclk"; 1329 drive-strength = <16>; 1330 bias-disable; 1331 }; 1332 1333 camera0_rst: rst { 1334 pins = "gpio25"; 1335 function = "gpio"; 1336 drive-strength = <16>; 1337 bias-disable; 1338 }; 1339 1340 camera0_pwdn: pwdn { 1341 pins = "gpio26"; 1342 function = "gpio"; 1343 drive-strength = <16>; 1344 bias-disable; 1345 }; 1346 }; 1347 1348 cci1_default: cci1-default { 1349 pins = "gpio19", "gpio20"; 1350 function = "cci_i2c"; 1351 drive-strength = <16>; 1352 bias-disable; 1353 }; 1354 1355 camera1_state_on: 1356 camera_board_default: camera-board-default { 1357 mclk1 { 1358 pins = "gpio14"; 1359 function = "cam_mclk"; 1360 drive-strength = <16>; 1361 bias-disable; 1362 }; 1363 1364 pwdn { 1365 pins = "gpio98"; 1366 function = "gpio"; 1367 drive-strength = <16>; 1368 bias-disable; 1369 }; 1370 1371 rst { 1372 pins = "gpio104"; 1373 function = "gpio"; 1374 drive-strength = <16>; 1375 bias-disable; 1376 }; 1377 }; 1378 1379 camera2_state_on: 1380 camera_front_default: camera-front-default { 1381 camera2_mclk: mclk2 { 1382 pins = "gpio15"; 1383 function = "cam_mclk"; 1384 drive-strength = <16>; 1385 bias-disable; 1386 }; 1387 1388 camera2_rst: rst { 1389 pins = "gpio23"; 1390 function = "gpio"; 1391 drive-strength = <16>; 1392 bias-disable; 1393 }; 1394 1395 pwdn { 1396 pins = "gpio133"; 1397 function = "gpio"; 1398 drive-strength = <16>; 1399 bias-disable; 1400 }; 1401 }; 1402 1403 pcie0_state_on: pcie0-state-on { 1404 perst { 1405 pins = "gpio35"; 1406 function = "gpio"; 1407 drive-strength = <2>; 1408 bias-pull-down; 1409 }; 1410 1411 clkreq { 1412 pins = "gpio36"; 1413 function = "pci_e0"; 1414 drive-strength = <2>; 1415 bias-pull-up; 1416 }; 1417 1418 wake { 1419 pins = "gpio37"; 1420 function = "gpio"; 1421 drive-strength = <2>; 1422 bias-pull-up; 1423 }; 1424 }; 1425 1426 pcie0_state_off: pcie0-state-off { 1427 perst { 1428 pins = "gpio35"; 1429 function = "gpio"; 1430 drive-strength = <2>; 1431 bias-pull-down; 1432 }; 1433 1434 clkreq { 1435 pins = "gpio36"; 1436 function = "gpio"; 1437 drive-strength = <2>; 1438 bias-disable; 1439 }; 1440 1441 wake { 1442 pins = "gpio37"; 1443 function = "gpio"; 1444 drive-strength = <2>; 1445 bias-disable; 1446 }; 1447 }; 1448 1449 blsp1_uart2_default: blsp1-uart2-default { 1450 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1451 function = "blsp_uart2"; 1452 drive-strength = <16>; 1453 bias-disable; 1454 }; 1455 1456 blsp1_uart2_sleep: blsp1-uart2-sleep { 1457 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1458 function = "gpio"; 1459 drive-strength = <2>; 1460 bias-disable; 1461 }; 1462 1463 blsp1_i2c3_default: blsp1-i2c2-default { 1464 pins = "gpio47", "gpio48"; 1465 function = "blsp_i2c3"; 1466 drive-strength = <16>; 1467 bias-disable; 1468 }; 1469 1470 blsp1_i2c3_sleep: blsp1-i2c2-sleep { 1471 pins = "gpio47", "gpio48"; 1472 function = "gpio"; 1473 drive-strength = <2>; 1474 bias-disable; 1475 }; 1476 1477 blsp2_uart3_4pins_default: blsp2-uart2-4pins { 1478 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1479 function = "blsp_uart9"; 1480 drive-strength = <16>; 1481 bias-disable; 1482 }; 1483 1484 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { 1485 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1486 function = "blsp_uart9"; 1487 drive-strength = <2>; 1488 bias-disable; 1489 }; 1490 1491 blsp2_i2c3_default: blsp2-i2c3 { 1492 pins = "gpio51", "gpio52"; 1493 function = "blsp_i2c9"; 1494 drive-strength = <16>; 1495 bias-disable; 1496 }; 1497 1498 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1499 pins = "gpio51", "gpio52"; 1500 function = "gpio"; 1501 drive-strength = <2>; 1502 bias-disable; 1503 }; 1504 1505 wcd_intr_default: wcd-intr-default{ 1506 pins = "gpio54"; 1507 function = "gpio"; 1508 drive-strength = <2>; 1509 bias-pull-down; 1510 input-enable; 1511 }; 1512 1513 blsp2_i2c1_default: blsp2-i2c1 { 1514 pins = "gpio55", "gpio56"; 1515 function = "blsp_i2c7"; 1516 drive-strength = <16>; 1517 bias-disable; 1518 }; 1519 1520 blsp2_i2c1_sleep: blsp2-i2c0-sleep { 1521 pins = "gpio55", "gpio56"; 1522 function = "gpio"; 1523 drive-strength = <2>; 1524 bias-disable; 1525 }; 1526 1527 blsp2_i2c5_default: blsp2-i2c5 { 1528 pins = "gpio60", "gpio61"; 1529 function = "blsp_i2c11"; 1530 drive-strength = <2>; 1531 bias-disable; 1532 }; 1533 1534 /* Sleep state for BLSP2_I2C5 is missing.. */ 1535 1536 cdc_reset_active: cdc-reset-active { 1537 pins = "gpio64"; 1538 function = "gpio"; 1539 drive-strength = <16>; 1540 bias-pull-down; 1541 output-high; 1542 }; 1543 1544 cdc_reset_sleep: cdc-reset-sleep { 1545 pins = "gpio64"; 1546 function = "gpio"; 1547 drive-strength = <16>; 1548 bias-disable; 1549 output-low; 1550 }; 1551 1552 blsp2_spi6_default: blsp2-spi5-default { 1553 spi { 1554 pins = "gpio85", "gpio86", "gpio88"; 1555 function = "blsp_spi12"; 1556 drive-strength = <12>; 1557 bias-disable; 1558 }; 1559 1560 cs { 1561 pins = "gpio87"; 1562 function = "gpio"; 1563 drive-strength = <16>; 1564 bias-disable; 1565 output-high; 1566 }; 1567 }; 1568 1569 blsp2_spi6_sleep: blsp2-spi5-sleep { 1570 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1571 function = "gpio"; 1572 drive-strength = <2>; 1573 bias-pull-down; 1574 }; 1575 1576 blsp2_i2c6_default: blsp2-i2c6 { 1577 pins = "gpio87", "gpio88"; 1578 function = "blsp_i2c12"; 1579 drive-strength = <16>; 1580 bias-disable; 1581 }; 1582 1583 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1584 pins = "gpio87", "gpio88"; 1585 function = "gpio"; 1586 drive-strength = <2>; 1587 bias-disable; 1588 }; 1589 1590 pcie1_state_on: pcie1-state-on { 1591 perst { 1592 pins = "gpio130"; 1593 function = "gpio"; 1594 drive-strength = <2>; 1595 bias-pull-down; 1596 }; 1597 1598 clkreq { 1599 pins = "gpio131"; 1600 function = "pci_e1"; 1601 drive-strength = <2>; 1602 bias-pull-up; 1603 }; 1604 1605 wake { 1606 pins = "gpio132"; 1607 function = "gpio"; 1608 drive-strength = <2>; 1609 bias-pull-down; 1610 }; 1611 }; 1612 1613 pcie1_state_off: pcie1-state-off { 1614 /* Perst is missing? */ 1615 clkreq { 1616 pins = "gpio131"; 1617 function = "gpio"; 1618 drive-strength = <2>; 1619 bias-disable; 1620 }; 1621 1622 wake { 1623 pins = "gpio132"; 1624 function = "gpio"; 1625 drive-strength = <2>; 1626 bias-disable; 1627 }; 1628 }; 1629 1630 pcie2_state_on: pcie2-state-on { 1631 perst { 1632 pins = "gpio114"; 1633 function = "gpio"; 1634 drive-strength = <2>; 1635 bias-pull-down; 1636 }; 1637 1638 clkreq { 1639 pins = "gpio115"; 1640 function = "pci_e2"; 1641 drive-strength = <2>; 1642 bias-pull-up; 1643 }; 1644 1645 wake { 1646 pins = "gpio116"; 1647 function = "gpio"; 1648 drive-strength = <2>; 1649 bias-pull-down; 1650 }; 1651 }; 1652 1653 pcie2_state_off: pcie2-state-off { 1654 /* Perst is missing? */ 1655 clkreq { 1656 pins = "gpio115"; 1657 function = "gpio"; 1658 drive-strength = <2>; 1659 bias-disable; 1660 }; 1661 1662 wake { 1663 pins = "gpio116"; 1664 function = "gpio"; 1665 drive-strength = <2>; 1666 bias-disable; 1667 }; 1668 }; 1669 1670 sdc1_state_on: sdc1-state-on { 1671 clk { 1672 pins = "sdc1_clk"; 1673 bias-disable; 1674 drive-strength = <16>; 1675 }; 1676 1677 cmd { 1678 pins = "sdc1_cmd"; 1679 bias-pull-up; 1680 drive-strength = <10>; 1681 }; 1682 1683 data { 1684 pins = "sdc1_data"; 1685 bias-pull-up; 1686 drive-strength = <10>; 1687 }; 1688 1689 rclk { 1690 pins = "sdc1_rclk"; 1691 bias-pull-down; 1692 }; 1693 }; 1694 1695 sdc1_state_off: sdc1-state-off { 1696 clk { 1697 pins = "sdc1_clk"; 1698 bias-disable; 1699 drive-strength = <2>; 1700 }; 1701 1702 cmd { 1703 pins = "sdc1_cmd"; 1704 bias-pull-up; 1705 drive-strength = <2>; 1706 }; 1707 1708 data { 1709 pins = "sdc1_data"; 1710 bias-pull-up; 1711 drive-strength = <2>; 1712 }; 1713 1714 rclk { 1715 pins = "sdc1_rclk"; 1716 bias-pull-down; 1717 }; 1718 }; 1719 1720 sdc2_state_on: sdc2-clk-on { 1721 clk { 1722 pins = "sdc2_clk"; 1723 bias-disable; 1724 drive-strength = <16>; 1725 }; 1726 1727 cmd { 1728 pins = "sdc2_cmd"; 1729 bias-pull-up; 1730 drive-strength = <10>; 1731 }; 1732 1733 data { 1734 pins = "sdc2_data"; 1735 bias-pull-up; 1736 drive-strength = <10>; 1737 }; 1738 }; 1739 1740 sdc2_state_off: sdc2-clk-off { 1741 clk { 1742 pins = "sdc2_clk"; 1743 bias-disable; 1744 drive-strength = <2>; 1745 }; 1746 1747 cmd { 1748 pins = "sdc2_cmd"; 1749 bias-pull-up; 1750 drive-strength = <2>; 1751 }; 1752 1753 data { 1754 pins = "sdc2_data"; 1755 bias-pull-up; 1756 drive-strength = <2>; 1757 }; 1758 }; 1759 }; 1760 1761 sram@290000 { 1762 compatible = "qcom,rpm-stats"; 1763 reg = <0x00290000 0x10000>; 1764 }; 1765 1766 spmi_bus: spmi@400f000 { 1767 compatible = "qcom,spmi-pmic-arb"; 1768 reg = <0x0400f000 0x1000>, 1769 <0x04400000 0x800000>, 1770 <0x04c00000 0x800000>, 1771 <0x05800000 0x200000>, 1772 <0x0400a000 0x002100>; 1773 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1774 interrupt-names = "periph_irq"; 1775 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1776 qcom,ee = <0>; 1777 qcom,channel = <0>; 1778 #address-cells = <2>; 1779 #size-cells = <0>; 1780 interrupt-controller; 1781 #interrupt-cells = <4>; 1782 }; 1783 1784 agnoc@0 { 1785 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1786 compatible = "simple-pm-bus"; 1787 #address-cells = <1>; 1788 #size-cells = <1>; 1789 ranges; 1790 1791 pcie0: pcie@600000 { 1792 compatible = "qcom,pcie-msm8996"; 1793 status = "disabled"; 1794 power-domains = <&gcc PCIE0_GDSC>; 1795 bus-range = <0x00 0xff>; 1796 num-lanes = <1>; 1797 1798 reg = <0x00600000 0x2000>, 1799 <0x0c000000 0xf1d>, 1800 <0x0c000f20 0xa8>, 1801 <0x0c100000 0x100000>; 1802 reg-names = "parf", "dbi", "elbi","config"; 1803 1804 phys = <&pciephy_0>; 1805 phy-names = "pciephy"; 1806 1807 #address-cells = <3>; 1808 #size-cells = <2>; 1809 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1810 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1811 1812 device_type = "pci"; 1813 1814 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1815 interrupt-names = "msi"; 1816 #interrupt-cells = <1>; 1817 interrupt-map-mask = <0 0 0 0x7>; 1818 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1819 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1820 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1821 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1822 1823 pinctrl-names = "default", "sleep"; 1824 pinctrl-0 = <&pcie0_state_on>; 1825 pinctrl-1 = <&pcie0_state_off>; 1826 1827 linux,pci-domain = <0>; 1828 1829 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1830 <&gcc GCC_PCIE_0_AUX_CLK>, 1831 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1832 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1833 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1834 1835 clock-names = "pipe", 1836 "aux", 1837 "cfg", 1838 "bus_master", 1839 "bus_slave"; 1840 1841 }; 1842 1843 pcie1: pcie@608000 { 1844 compatible = "qcom,pcie-msm8996"; 1845 power-domains = <&gcc PCIE1_GDSC>; 1846 bus-range = <0x00 0xff>; 1847 num-lanes = <1>; 1848 1849 status = "disabled"; 1850 1851 reg = <0x00608000 0x2000>, 1852 <0x0d000000 0xf1d>, 1853 <0x0d000f20 0xa8>, 1854 <0x0d100000 0x100000>; 1855 1856 reg-names = "parf", "dbi", "elbi","config"; 1857 1858 phys = <&pciephy_1>; 1859 phy-names = "pciephy"; 1860 1861 #address-cells = <3>; 1862 #size-cells = <2>; 1863 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1864 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1865 1866 device_type = "pci"; 1867 1868 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1869 interrupt-names = "msi"; 1870 #interrupt-cells = <1>; 1871 interrupt-map-mask = <0 0 0 0x7>; 1872 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1873 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1874 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1875 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1876 1877 pinctrl-names = "default", "sleep"; 1878 pinctrl-0 = <&pcie1_state_on>; 1879 pinctrl-1 = <&pcie1_state_off>; 1880 1881 linux,pci-domain = <1>; 1882 1883 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1884 <&gcc GCC_PCIE_1_AUX_CLK>, 1885 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1886 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1887 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1888 1889 clock-names = "pipe", 1890 "aux", 1891 "cfg", 1892 "bus_master", 1893 "bus_slave"; 1894 }; 1895 1896 pcie2: pcie@610000 { 1897 compatible = "qcom,pcie-msm8996"; 1898 power-domains = <&gcc PCIE2_GDSC>; 1899 bus-range = <0x00 0xff>; 1900 num-lanes = <1>; 1901 status = "disabled"; 1902 reg = <0x00610000 0x2000>, 1903 <0x0e000000 0xf1d>, 1904 <0x0e000f20 0xa8>, 1905 <0x0e100000 0x100000>; 1906 1907 reg-names = "parf", "dbi", "elbi","config"; 1908 1909 phys = <&pciephy_2>; 1910 phy-names = "pciephy"; 1911 1912 #address-cells = <3>; 1913 #size-cells = <2>; 1914 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1915 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1916 1917 device_type = "pci"; 1918 1919 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1920 interrupt-names = "msi"; 1921 #interrupt-cells = <1>; 1922 interrupt-map-mask = <0 0 0 0x7>; 1923 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1924 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1925 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1926 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1927 1928 pinctrl-names = "default", "sleep"; 1929 pinctrl-0 = <&pcie2_state_on>; 1930 pinctrl-1 = <&pcie2_state_off>; 1931 1932 linux,pci-domain = <2>; 1933 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1934 <&gcc GCC_PCIE_2_AUX_CLK>, 1935 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1936 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1937 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1938 1939 clock-names = "pipe", 1940 "aux", 1941 "cfg", 1942 "bus_master", 1943 "bus_slave"; 1944 }; 1945 }; 1946 1947 ufshc: ufshc@624000 { 1948 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1949 "jedec,ufs-2.0"; 1950 reg = <0x00624000 0x2500>; 1951 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1952 1953 phys = <&ufsphy_lane>; 1954 phy-names = "ufsphy"; 1955 1956 power-domains = <&gcc UFS_GDSC>; 1957 1958 clock-names = 1959 "core_clk_src", 1960 "core_clk", 1961 "bus_clk", 1962 "bus_aggr_clk", 1963 "iface_clk", 1964 "core_clk_unipro_src", 1965 "core_clk_unipro", 1966 "core_clk_ice", 1967 "ref_clk", 1968 "tx_lane0_sync_clk", 1969 "rx_lane0_sync_clk"; 1970 clocks = 1971 <&gcc UFS_AXI_CLK_SRC>, 1972 <&gcc GCC_UFS_AXI_CLK>, 1973 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 1974 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 1975 <&gcc GCC_UFS_AHB_CLK>, 1976 <&gcc UFS_ICE_CORE_CLK_SRC>, 1977 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1978 <&gcc GCC_UFS_ICE_CORE_CLK>, 1979 <&rpmcc RPM_SMD_LN_BB_CLK>, 1980 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1981 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 1982 freq-table-hz = 1983 <100000000 200000000>, 1984 <0 0>, 1985 <0 0>, 1986 <0 0>, 1987 <0 0>, 1988 <150000000 300000000>, 1989 <0 0>, 1990 <0 0>, 1991 <0 0>, 1992 <0 0>, 1993 <0 0>; 1994 1995 lanes-per-direction = <1>; 1996 #reset-cells = <1>; 1997 status = "disabled"; 1998 1999 ufs_variant { 2000 compatible = "qcom,ufs_variant"; 2001 }; 2002 }; 2003 2004 ufsphy: phy@627000 { 2005 compatible = "qcom,msm8996-qmp-ufs-phy"; 2006 reg = <0x00627000 0x1c4>; 2007 #address-cells = <1>; 2008 #size-cells = <1>; 2009 ranges; 2010 2011 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2012 clock-names = "ref"; 2013 2014 resets = <&ufshc 0>; 2015 reset-names = "ufsphy"; 2016 status = "disabled"; 2017 2018 ufsphy_lane: phy@627400 { 2019 reg = <0x627400 0x12c>, 2020 <0x627600 0x200>, 2021 <0x627c00 0x1b4>; 2022 #phy-cells = <0>; 2023 }; 2024 }; 2025 2026 camss: camss@a00000 { 2027 compatible = "qcom,msm8996-camss"; 2028 reg = <0x00a34000 0x1000>, 2029 <0x00a00030 0x4>, 2030 <0x00a35000 0x1000>, 2031 <0x00a00038 0x4>, 2032 <0x00a36000 0x1000>, 2033 <0x00a00040 0x4>, 2034 <0x00a30000 0x100>, 2035 <0x00a30400 0x100>, 2036 <0x00a30800 0x100>, 2037 <0x00a30c00 0x100>, 2038 <0x00a31000 0x500>, 2039 <0x00a00020 0x10>, 2040 <0x00a10000 0x1000>, 2041 <0x00a14000 0x1000>; 2042 reg-names = "csiphy0", 2043 "csiphy0_clk_mux", 2044 "csiphy1", 2045 "csiphy1_clk_mux", 2046 "csiphy2", 2047 "csiphy2_clk_mux", 2048 "csid0", 2049 "csid1", 2050 "csid2", 2051 "csid3", 2052 "ispif", 2053 "csi_clk_mux", 2054 "vfe0", 2055 "vfe1"; 2056 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2062 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2063 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2065 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2066 interrupt-names = "csiphy0", 2067 "csiphy1", 2068 "csiphy2", 2069 "csid0", 2070 "csid1", 2071 "csid2", 2072 "csid3", 2073 "ispif", 2074 "vfe0", 2075 "vfe1"; 2076 power-domains = <&mmcc VFE0_GDSC>, 2077 <&mmcc VFE1_GDSC>; 2078 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2079 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2080 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2081 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2082 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2083 <&mmcc CAMSS_CSI0_AHB_CLK>, 2084 <&mmcc CAMSS_CSI0_CLK>, 2085 <&mmcc CAMSS_CSI0PHY_CLK>, 2086 <&mmcc CAMSS_CSI0PIX_CLK>, 2087 <&mmcc CAMSS_CSI0RDI_CLK>, 2088 <&mmcc CAMSS_CSI1_AHB_CLK>, 2089 <&mmcc CAMSS_CSI1_CLK>, 2090 <&mmcc CAMSS_CSI1PHY_CLK>, 2091 <&mmcc CAMSS_CSI1PIX_CLK>, 2092 <&mmcc CAMSS_CSI1RDI_CLK>, 2093 <&mmcc CAMSS_CSI2_AHB_CLK>, 2094 <&mmcc CAMSS_CSI2_CLK>, 2095 <&mmcc CAMSS_CSI2PHY_CLK>, 2096 <&mmcc CAMSS_CSI2PIX_CLK>, 2097 <&mmcc CAMSS_CSI2RDI_CLK>, 2098 <&mmcc CAMSS_CSI3_AHB_CLK>, 2099 <&mmcc CAMSS_CSI3_CLK>, 2100 <&mmcc CAMSS_CSI3PHY_CLK>, 2101 <&mmcc CAMSS_CSI3PIX_CLK>, 2102 <&mmcc CAMSS_CSI3RDI_CLK>, 2103 <&mmcc CAMSS_AHB_CLK>, 2104 <&mmcc CAMSS_VFE0_CLK>, 2105 <&mmcc CAMSS_CSI_VFE0_CLK>, 2106 <&mmcc CAMSS_VFE0_AHB_CLK>, 2107 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2108 <&mmcc CAMSS_VFE1_CLK>, 2109 <&mmcc CAMSS_CSI_VFE1_CLK>, 2110 <&mmcc CAMSS_VFE1_AHB_CLK>, 2111 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2112 <&mmcc CAMSS_VFE_AHB_CLK>, 2113 <&mmcc CAMSS_VFE_AXI_CLK>; 2114 clock-names = "top_ahb", 2115 "ispif_ahb", 2116 "csiphy0_timer", 2117 "csiphy1_timer", 2118 "csiphy2_timer", 2119 "csi0_ahb", 2120 "csi0", 2121 "csi0_phy", 2122 "csi0_pix", 2123 "csi0_rdi", 2124 "csi1_ahb", 2125 "csi1", 2126 "csi1_phy", 2127 "csi1_pix", 2128 "csi1_rdi", 2129 "csi2_ahb", 2130 "csi2", 2131 "csi2_phy", 2132 "csi2_pix", 2133 "csi2_rdi", 2134 "csi3_ahb", 2135 "csi3", 2136 "csi3_phy", 2137 "csi3_pix", 2138 "csi3_rdi", 2139 "ahb", 2140 "vfe0", 2141 "csi_vfe0", 2142 "vfe0_ahb", 2143 "vfe0_stream", 2144 "vfe1", 2145 "csi_vfe1", 2146 "vfe1_ahb", 2147 "vfe1_stream", 2148 "vfe_ahb", 2149 "vfe_axi"; 2150 iommus = <&vfe_smmu 0>, 2151 <&vfe_smmu 1>, 2152 <&vfe_smmu 2>, 2153 <&vfe_smmu 3>; 2154 status = "disabled"; 2155 ports { 2156 #address-cells = <1>; 2157 #size-cells = <0>; 2158 }; 2159 }; 2160 2161 cci: cci@a0c000 { 2162 compatible = "qcom,msm8996-cci"; 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 reg = <0xa0c000 0x1000>; 2166 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2167 power-domains = <&mmcc CAMSS_GDSC>; 2168 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2169 <&mmcc CAMSS_CCI_AHB_CLK>, 2170 <&mmcc CAMSS_CCI_CLK>, 2171 <&mmcc CAMSS_AHB_CLK>; 2172 clock-names = "camss_top_ahb", 2173 "cci_ahb", 2174 "cci", 2175 "camss_ahb"; 2176 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2177 <&mmcc CAMSS_CCI_CLK>; 2178 assigned-clock-rates = <80000000>, <37500000>; 2179 pinctrl-names = "default"; 2180 pinctrl-0 = <&cci0_default &cci1_default>; 2181 status = "disabled"; 2182 2183 cci_i2c0: i2c-bus@0 { 2184 reg = <0>; 2185 clock-frequency = <400000>; 2186 #address-cells = <1>; 2187 #size-cells = <0>; 2188 }; 2189 2190 cci_i2c1: i2c-bus@1 { 2191 reg = <1>; 2192 clock-frequency = <400000>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 }; 2196 }; 2197 2198 adreno_smmu: iommu@b40000 { 2199 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2200 reg = <0x00b40000 0x10000>; 2201 2202 #global-interrupts = <1>; 2203 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2206 #iommu-cells = <1>; 2207 2208 clocks = <&mmcc GPU_AHB_CLK>, 2209 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 2210 clock-names = "iface", "bus"; 2211 2212 power-domains = <&mmcc GPU_GDSC>; 2213 }; 2214 2215 venus: video-codec@c00000 { 2216 compatible = "qcom,msm8996-venus"; 2217 reg = <0x00c00000 0xff000>; 2218 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2219 power-domains = <&mmcc VENUS_GDSC>; 2220 clocks = <&mmcc VIDEO_CORE_CLK>, 2221 <&mmcc VIDEO_AHB_CLK>, 2222 <&mmcc VIDEO_AXI_CLK>, 2223 <&mmcc VIDEO_MAXI_CLK>; 2224 clock-names = "core", "iface", "bus", "mbus"; 2225 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2226 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2227 interconnect-names = "video-mem", "cpu-cfg"; 2228 iommus = <&venus_smmu 0x00>, 2229 <&venus_smmu 0x01>, 2230 <&venus_smmu 0x0a>, 2231 <&venus_smmu 0x07>, 2232 <&venus_smmu 0x0e>, 2233 <&venus_smmu 0x0f>, 2234 <&venus_smmu 0x08>, 2235 <&venus_smmu 0x09>, 2236 <&venus_smmu 0x0b>, 2237 <&venus_smmu 0x0c>, 2238 <&venus_smmu 0x0d>, 2239 <&venus_smmu 0x10>, 2240 <&venus_smmu 0x11>, 2241 <&venus_smmu 0x21>, 2242 <&venus_smmu 0x28>, 2243 <&venus_smmu 0x29>, 2244 <&venus_smmu 0x2b>, 2245 <&venus_smmu 0x2c>, 2246 <&venus_smmu 0x2d>, 2247 <&venus_smmu 0x31>; 2248 memory-region = <&venus_mem>; 2249 status = "disabled"; 2250 2251 video-decoder { 2252 compatible = "venus-decoder"; 2253 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2254 clock-names = "core"; 2255 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2256 }; 2257 2258 video-encoder { 2259 compatible = "venus-encoder"; 2260 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2261 clock-names = "core"; 2262 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2263 }; 2264 }; 2265 2266 mdp_smmu: iommu@d00000 { 2267 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2268 reg = <0x00d00000 0x10000>; 2269 2270 #global-interrupts = <1>; 2271 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2274 #iommu-cells = <1>; 2275 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 2276 <&mmcc SMMU_MDP_AXI_CLK>; 2277 clock-names = "iface", "bus"; 2278 2279 power-domains = <&mmcc MDSS_GDSC>; 2280 }; 2281 2282 venus_smmu: iommu@d40000 { 2283 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2284 reg = <0x00d40000 0x20000>; 2285 #global-interrupts = <1>; 2286 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2294 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2295 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 2296 <&mmcc SMMU_VIDEO_AXI_CLK>; 2297 clock-names = "iface", "bus"; 2298 #iommu-cells = <1>; 2299 status = "okay"; 2300 }; 2301 2302 vfe_smmu: iommu@da0000 { 2303 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2304 reg = <0x00da0000 0x10000>; 2305 2306 #global-interrupts = <1>; 2307 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2308 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2310 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2311 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 2312 <&mmcc SMMU_VFE_AXI_CLK>; 2313 clock-names = "iface", 2314 "bus"; 2315 #iommu-cells = <1>; 2316 }; 2317 2318 lpass_q6_smmu: iommu@1600000 { 2319 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2320 reg = <0x01600000 0x20000>; 2321 #iommu-cells = <1>; 2322 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2323 2324 #global-interrupts = <1>; 2325 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2326 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2327 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2328 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2329 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2330 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2331 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2333 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2338 2339 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 2340 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 2341 clock-names = "iface", "bus"; 2342 }; 2343 2344 slpi_pil: remoteproc@1c00000 { 2345 compatible = "qcom,msm8996-slpi-pil"; 2346 reg = <0x01c00000 0x4000>; 2347 2348 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2349 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2350 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2351 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2352 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2353 interrupt-names = "wdog", 2354 "fatal", 2355 "ready", 2356 "handover", 2357 "stop-ack"; 2358 2359 clocks = <&xo_board>, 2360 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2361 clock-names = "xo", "aggre2"; 2362 2363 memory-region = <&slpi_mem>; 2364 2365 qcom,smem-states = <&slpi_smp2p_out 0>; 2366 qcom,smem-state-names = "stop"; 2367 2368 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2369 power-domain-names = "ssc_cx"; 2370 2371 status = "disabled"; 2372 2373 smd-edge { 2374 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2375 2376 label = "dsps"; 2377 mboxes = <&apcs_glb 25>; 2378 qcom,smd-edge = <3>; 2379 qcom,remote-pid = <3>; 2380 }; 2381 }; 2382 2383 mss_pil: remoteproc@2080000 { 2384 compatible = "qcom,msm8996-mss-pil"; 2385 reg = <0x2080000 0x100>, 2386 <0x2180000 0x020>; 2387 reg-names = "qdsp6", "rmb"; 2388 2389 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2390 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2391 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2392 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2393 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2394 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2395 interrupt-names = "wdog", "fatal", "ready", 2396 "handover", "stop-ack", 2397 "shutdown-ack"; 2398 2399 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2400 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2401 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2402 <&xo_board>, 2403 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2404 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2405 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2406 <&rpmcc RPM_SMD_PCNOC_CLK>, 2407 <&rpmcc RPM_SMD_QDSS_CLK>; 2408 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2409 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2410 2411 resets = <&gcc GCC_MSS_RESTART>; 2412 reset-names = "mss_restart"; 2413 2414 power-domains = <&rpmpd MSM8996_VDDCX>, 2415 <&rpmpd MSM8996_VDDMX>; 2416 power-domain-names = "cx", "mx"; 2417 2418 qcom,smem-states = <&mpss_smp2p_out 0>; 2419 qcom,smem-state-names = "stop"; 2420 2421 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2422 2423 status = "disabled"; 2424 2425 mba { 2426 memory-region = <&mba_mem>; 2427 }; 2428 2429 mpss { 2430 memory-region = <&mpss_mem>; 2431 }; 2432 2433 smd-edge { 2434 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2435 2436 label = "mpss"; 2437 mboxes = <&apcs_glb 12>; 2438 qcom,smd-edge = <0>; 2439 qcom,remote-pid = <1>; 2440 }; 2441 }; 2442 2443 stm@3002000 { 2444 compatible = "arm,coresight-stm", "arm,primecell"; 2445 reg = <0x3002000 0x1000>, 2446 <0x8280000 0x180000>; 2447 reg-names = "stm-base", "stm-stimulus-base"; 2448 2449 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2450 clock-names = "apb_pclk", "atclk"; 2451 2452 out-ports { 2453 port { 2454 stm_out: endpoint { 2455 remote-endpoint = 2456 <&funnel0_in>; 2457 }; 2458 }; 2459 }; 2460 }; 2461 2462 tpiu@3020000 { 2463 compatible = "arm,coresight-tpiu", "arm,primecell"; 2464 reg = <0x3020000 0x1000>; 2465 2466 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2467 clock-names = "apb_pclk", "atclk"; 2468 2469 in-ports { 2470 port { 2471 tpiu_in: endpoint { 2472 remote-endpoint = 2473 <&replicator_out1>; 2474 }; 2475 }; 2476 }; 2477 }; 2478 2479 funnel@3021000 { 2480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2481 reg = <0x3021000 0x1000>; 2482 2483 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2484 clock-names = "apb_pclk", "atclk"; 2485 2486 in-ports { 2487 #address-cells = <1>; 2488 #size-cells = <0>; 2489 2490 port@7 { 2491 reg = <7>; 2492 funnel0_in: endpoint { 2493 remote-endpoint = 2494 <&stm_out>; 2495 }; 2496 }; 2497 }; 2498 2499 out-ports { 2500 port { 2501 funnel0_out: endpoint { 2502 remote-endpoint = 2503 <&merge_funnel_in0>; 2504 }; 2505 }; 2506 }; 2507 }; 2508 2509 funnel@3022000 { 2510 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2511 reg = <0x3022000 0x1000>; 2512 2513 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2514 clock-names = "apb_pclk", "atclk"; 2515 2516 in-ports { 2517 #address-cells = <1>; 2518 #size-cells = <0>; 2519 2520 port@6 { 2521 reg = <6>; 2522 funnel1_in: endpoint { 2523 remote-endpoint = 2524 <&apss_merge_funnel_out>; 2525 }; 2526 }; 2527 }; 2528 2529 out-ports { 2530 port { 2531 funnel1_out: endpoint { 2532 remote-endpoint = 2533 <&merge_funnel_in1>; 2534 }; 2535 }; 2536 }; 2537 }; 2538 2539 funnel@3023000 { 2540 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2541 reg = <0x3023000 0x1000>; 2542 2543 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2544 clock-names = "apb_pclk", "atclk"; 2545 2546 2547 out-ports { 2548 port { 2549 funnel2_out: endpoint { 2550 remote-endpoint = 2551 <&merge_funnel_in2>; 2552 }; 2553 }; 2554 }; 2555 }; 2556 2557 funnel@3025000 { 2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2559 reg = <0x3025000 0x1000>; 2560 2561 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2562 clock-names = "apb_pclk", "atclk"; 2563 2564 in-ports { 2565 #address-cells = <1>; 2566 #size-cells = <0>; 2567 2568 port@0 { 2569 reg = <0>; 2570 merge_funnel_in0: endpoint { 2571 remote-endpoint = 2572 <&funnel0_out>; 2573 }; 2574 }; 2575 2576 port@1 { 2577 reg = <1>; 2578 merge_funnel_in1: endpoint { 2579 remote-endpoint = 2580 <&funnel1_out>; 2581 }; 2582 }; 2583 2584 port@2 { 2585 reg = <2>; 2586 merge_funnel_in2: endpoint { 2587 remote-endpoint = 2588 <&funnel2_out>; 2589 }; 2590 }; 2591 }; 2592 2593 out-ports { 2594 port { 2595 merge_funnel_out: endpoint { 2596 remote-endpoint = 2597 <&etf_in>; 2598 }; 2599 }; 2600 }; 2601 }; 2602 2603 replicator@3026000 { 2604 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2605 reg = <0x3026000 0x1000>; 2606 2607 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2608 clock-names = "apb_pclk", "atclk"; 2609 2610 in-ports { 2611 port { 2612 replicator_in: endpoint { 2613 remote-endpoint = 2614 <&etf_out>; 2615 }; 2616 }; 2617 }; 2618 2619 out-ports { 2620 #address-cells = <1>; 2621 #size-cells = <0>; 2622 2623 port@0 { 2624 reg = <0>; 2625 replicator_out0: endpoint { 2626 remote-endpoint = 2627 <&etr_in>; 2628 }; 2629 }; 2630 2631 port@1 { 2632 reg = <1>; 2633 replicator_out1: endpoint { 2634 remote-endpoint = 2635 <&tpiu_in>; 2636 }; 2637 }; 2638 }; 2639 }; 2640 2641 etf@3027000 { 2642 compatible = "arm,coresight-tmc", "arm,primecell"; 2643 reg = <0x3027000 0x1000>; 2644 2645 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2646 clock-names = "apb_pclk", "atclk"; 2647 2648 in-ports { 2649 port { 2650 etf_in: endpoint { 2651 remote-endpoint = 2652 <&merge_funnel_out>; 2653 }; 2654 }; 2655 }; 2656 2657 out-ports { 2658 port { 2659 etf_out: endpoint { 2660 remote-endpoint = 2661 <&replicator_in>; 2662 }; 2663 }; 2664 }; 2665 }; 2666 2667 etr@3028000 { 2668 compatible = "arm,coresight-tmc", "arm,primecell"; 2669 reg = <0x3028000 0x1000>; 2670 2671 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2672 clock-names = "apb_pclk", "atclk"; 2673 arm,scatter-gather; 2674 2675 in-ports { 2676 port { 2677 etr_in: endpoint { 2678 remote-endpoint = 2679 <&replicator_out0>; 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 debug@3810000 { 2686 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2687 reg = <0x3810000 0x1000>; 2688 2689 clocks = <&rpmcc RPM_QDSS_CLK>; 2690 clock-names = "apb_pclk"; 2691 2692 cpu = <&CPU0>; 2693 }; 2694 2695 etm@3840000 { 2696 compatible = "arm,coresight-etm4x", "arm,primecell"; 2697 reg = <0x3840000 0x1000>; 2698 2699 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2700 clock-names = "apb_pclk", "atclk"; 2701 2702 cpu = <&CPU0>; 2703 2704 out-ports { 2705 port { 2706 etm0_out: endpoint { 2707 remote-endpoint = 2708 <&apss_funnel0_in0>; 2709 }; 2710 }; 2711 }; 2712 }; 2713 2714 debug@3910000 { 2715 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2716 reg = <0x3910000 0x1000>; 2717 2718 clocks = <&rpmcc RPM_QDSS_CLK>; 2719 clock-names = "apb_pclk"; 2720 2721 cpu = <&CPU1>; 2722 }; 2723 2724 etm@3940000 { 2725 compatible = "arm,coresight-etm4x", "arm,primecell"; 2726 reg = <0x3940000 0x1000>; 2727 2728 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2729 clock-names = "apb_pclk", "atclk"; 2730 2731 cpu = <&CPU1>; 2732 2733 out-ports { 2734 port { 2735 etm1_out: endpoint { 2736 remote-endpoint = 2737 <&apss_funnel0_in1>; 2738 }; 2739 }; 2740 }; 2741 }; 2742 2743 funnel@39b0000 { /* APSS Funnel 0 */ 2744 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2745 reg = <0x39b0000 0x1000>; 2746 2747 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2748 clock-names = "apb_pclk", "atclk"; 2749 2750 in-ports { 2751 #address-cells = <1>; 2752 #size-cells = <0>; 2753 2754 port@0 { 2755 reg = <0>; 2756 apss_funnel0_in0: endpoint { 2757 remote-endpoint = <&etm0_out>; 2758 }; 2759 }; 2760 2761 port@1 { 2762 reg = <1>; 2763 apss_funnel0_in1: endpoint { 2764 remote-endpoint = <&etm1_out>; 2765 }; 2766 }; 2767 }; 2768 2769 out-ports { 2770 port { 2771 apss_funnel0_out: endpoint { 2772 remote-endpoint = 2773 <&apss_merge_funnel_in0>; 2774 }; 2775 }; 2776 }; 2777 }; 2778 2779 debug@3a10000 { 2780 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2781 reg = <0x3a10000 0x1000>; 2782 2783 clocks = <&rpmcc RPM_QDSS_CLK>; 2784 clock-names = "apb_pclk"; 2785 2786 cpu = <&CPU2>; 2787 }; 2788 2789 etm@3a40000 { 2790 compatible = "arm,coresight-etm4x", "arm,primecell"; 2791 reg = <0x3a40000 0x1000>; 2792 2793 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2794 clock-names = "apb_pclk", "atclk"; 2795 2796 cpu = <&CPU2>; 2797 2798 out-ports { 2799 port { 2800 etm2_out: endpoint { 2801 remote-endpoint = 2802 <&apss_funnel1_in0>; 2803 }; 2804 }; 2805 }; 2806 }; 2807 2808 debug@3b10000 { 2809 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2810 reg = <0x3b10000 0x1000>; 2811 2812 clocks = <&rpmcc RPM_QDSS_CLK>; 2813 clock-names = "apb_pclk"; 2814 2815 cpu = <&CPU3>; 2816 }; 2817 2818 etm@3b40000 { 2819 compatible = "arm,coresight-etm4x", "arm,primecell"; 2820 reg = <0x3b40000 0x1000>; 2821 2822 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2823 clock-names = "apb_pclk", "atclk"; 2824 2825 cpu = <&CPU3>; 2826 2827 out-ports { 2828 port { 2829 etm3_out: endpoint { 2830 remote-endpoint = 2831 <&apss_funnel1_in1>; 2832 }; 2833 }; 2834 }; 2835 }; 2836 2837 funnel@3bb0000 { /* APSS Funnel 1 */ 2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2839 reg = <0x3bb0000 0x1000>; 2840 2841 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2842 clock-names = "apb_pclk", "atclk"; 2843 2844 in-ports { 2845 #address-cells = <1>; 2846 #size-cells = <0>; 2847 2848 port@0 { 2849 reg = <0>; 2850 apss_funnel1_in0: endpoint { 2851 remote-endpoint = <&etm2_out>; 2852 }; 2853 }; 2854 2855 port@1 { 2856 reg = <1>; 2857 apss_funnel1_in1: endpoint { 2858 remote-endpoint = <&etm3_out>; 2859 }; 2860 }; 2861 }; 2862 2863 out-ports { 2864 port { 2865 apss_funnel1_out: endpoint { 2866 remote-endpoint = 2867 <&apss_merge_funnel_in1>; 2868 }; 2869 }; 2870 }; 2871 }; 2872 2873 funnel@3bc0000 { 2874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2875 reg = <0x3bc0000 0x1000>; 2876 2877 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2878 clock-names = "apb_pclk", "atclk"; 2879 2880 in-ports { 2881 #address-cells = <1>; 2882 #size-cells = <0>; 2883 2884 port@0 { 2885 reg = <0>; 2886 apss_merge_funnel_in0: endpoint { 2887 remote-endpoint = 2888 <&apss_funnel0_out>; 2889 }; 2890 }; 2891 2892 port@1 { 2893 reg = <1>; 2894 apss_merge_funnel_in1: endpoint { 2895 remote-endpoint = 2896 <&apss_funnel1_out>; 2897 }; 2898 }; 2899 }; 2900 2901 out-ports { 2902 port { 2903 apss_merge_funnel_out: endpoint { 2904 remote-endpoint = 2905 <&funnel1_in>; 2906 }; 2907 }; 2908 }; 2909 }; 2910 2911 kryocc: clock-controller@6400000 { 2912 compatible = "qcom,msm8996-apcc"; 2913 reg = <0x06400000 0x90000>; 2914 2915 clock-names = "xo"; 2916 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 2917 2918 #clock-cells = <1>; 2919 }; 2920 2921 usb3: usb@6af8800 { 2922 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2923 reg = <0x06af8800 0x400>; 2924 #address-cells = <1>; 2925 #size-cells = <1>; 2926 ranges; 2927 2928 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2930 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2931 2932 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2933 <&gcc GCC_USB30_MASTER_CLK>, 2934 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2935 <&gcc GCC_USB30_SLEEP_CLK>, 2936 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2937 clock-names = "cfg_noc", 2938 "core", 2939 "iface", 2940 "sleep", 2941 "mock_utmi"; 2942 2943 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2944 <&gcc GCC_USB30_MASTER_CLK>; 2945 assigned-clock-rates = <19200000>, <120000000>; 2946 2947 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2948 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2949 interconnect-names = "usb-ddr", "apps-usb"; 2950 2951 power-domains = <&gcc USB30_GDSC>; 2952 status = "disabled"; 2953 2954 usb3_dwc3: usb@6a00000 { 2955 compatible = "snps,dwc3"; 2956 reg = <0x06a00000 0xcc00>; 2957 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 2958 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 2959 phy-names = "usb2-phy", "usb3-phy"; 2960 snps,dis_u2_susphy_quirk; 2961 snps,dis_enblslpm_quirk; 2962 }; 2963 }; 2964 2965 usb3phy: phy@7410000 { 2966 compatible = "qcom,msm8996-qmp-usb3-phy"; 2967 reg = <0x07410000 0x1c4>; 2968 #address-cells = <1>; 2969 #size-cells = <1>; 2970 ranges; 2971 2972 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2973 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2974 <&gcc GCC_USB3_CLKREF_CLK>; 2975 clock-names = "aux", "cfg_ahb", "ref"; 2976 2977 resets = <&gcc GCC_USB3_PHY_BCR>, 2978 <&gcc GCC_USB3PHY_PHY_BCR>; 2979 reset-names = "phy", "common"; 2980 status = "disabled"; 2981 2982 ssusb_phy_0: phy@7410200 { 2983 reg = <0x07410200 0x200>, 2984 <0x07410400 0x130>, 2985 <0x07410600 0x1a8>; 2986 #phy-cells = <0>; 2987 2988 #clock-cells = <0>; 2989 clock-output-names = "usb3_phy_pipe_clk_src"; 2990 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 2991 clock-names = "pipe0"; 2992 }; 2993 }; 2994 2995 hsusb_phy1: phy@7411000 { 2996 compatible = "qcom,msm8996-qusb2-phy"; 2997 reg = <0x07411000 0x180>; 2998 #phy-cells = <0>; 2999 3000 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3001 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3002 clock-names = "cfg_ahb", "ref"; 3003 3004 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3005 nvmem-cells = <&qusb2p_hstx_trim>; 3006 status = "disabled"; 3007 }; 3008 3009 hsusb_phy2: phy@7412000 { 3010 compatible = "qcom,msm8996-qusb2-phy"; 3011 reg = <0x07412000 0x180>; 3012 #phy-cells = <0>; 3013 3014 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3015 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3016 clock-names = "cfg_ahb", "ref"; 3017 3018 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3019 nvmem-cells = <&qusb2s_hstx_trim>; 3020 status = "disabled"; 3021 }; 3022 3023 sdhc1: mmc@7464900 { 3024 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3025 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3026 reg-names = "hc", "core"; 3027 3028 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3030 interrupt-names = "hc_irq", "pwr_irq"; 3031 3032 clock-names = "iface", "core", "xo"; 3033 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3034 <&gcc GCC_SDCC1_APPS_CLK>, 3035 <&rpmcc RPM_SMD_BB_CLK1>; 3036 resets = <&gcc GCC_SDCC1_BCR>; 3037 3038 pinctrl-names = "default", "sleep"; 3039 pinctrl-0 = <&sdc1_state_on>; 3040 pinctrl-1 = <&sdc1_state_off>; 3041 3042 bus-width = <8>; 3043 non-removable; 3044 status = "disabled"; 3045 }; 3046 3047 sdhc2: mmc@74a4900 { 3048 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3049 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3050 reg-names = "hc", "core"; 3051 3052 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3054 interrupt-names = "hc_irq", "pwr_irq"; 3055 3056 clock-names = "iface", "core", "xo"; 3057 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3058 <&gcc GCC_SDCC2_APPS_CLK>, 3059 <&rpmcc RPM_SMD_BB_CLK1>; 3060 resets = <&gcc GCC_SDCC2_BCR>; 3061 3062 pinctrl-names = "default", "sleep"; 3063 pinctrl-0 = <&sdc2_state_on>; 3064 pinctrl-1 = <&sdc2_state_off>; 3065 3066 bus-width = <4>; 3067 status = "disabled"; 3068 }; 3069 3070 blsp1_dma: dma-controller@7544000 { 3071 compatible = "qcom,bam-v1.7.0"; 3072 reg = <0x07544000 0x2b000>; 3073 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3074 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3075 clock-names = "bam_clk"; 3076 qcom,controlled-remotely; 3077 #dma-cells = <1>; 3078 qcom,ee = <0>; 3079 }; 3080 3081 blsp1_uart2: serial@7570000 { 3082 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3083 reg = <0x07570000 0x1000>; 3084 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3085 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3086 <&gcc GCC_BLSP1_AHB_CLK>; 3087 clock-names = "core", "iface"; 3088 pinctrl-names = "default", "sleep"; 3089 pinctrl-0 = <&blsp1_uart2_default>; 3090 pinctrl-1 = <&blsp1_uart2_sleep>; 3091 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3092 dma-names = "tx", "rx"; 3093 status = "disabled"; 3094 }; 3095 3096 blsp1_spi1: spi@7575000 { 3097 compatible = "qcom,spi-qup-v2.2.1"; 3098 reg = <0x07575000 0x600>; 3099 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3100 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3101 <&gcc GCC_BLSP1_AHB_CLK>; 3102 clock-names = "core", "iface"; 3103 pinctrl-names = "default", "sleep"; 3104 pinctrl-0 = <&blsp1_spi1_default>; 3105 pinctrl-1 = <&blsp1_spi1_sleep>; 3106 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3107 dma-names = "tx", "rx"; 3108 #address-cells = <1>; 3109 #size-cells = <0>; 3110 status = "disabled"; 3111 }; 3112 3113 blsp1_i2c3: i2c@7577000 { 3114 compatible = "qcom,i2c-qup-v2.2.1"; 3115 reg = <0x07577000 0x1000>; 3116 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3117 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3118 <&gcc GCC_BLSP1_AHB_CLK>; 3119 clock-names = "core", "iface"; 3120 pinctrl-names = "default", "sleep"; 3121 pinctrl-0 = <&blsp1_i2c3_default>; 3122 pinctrl-1 = <&blsp1_i2c3_sleep>; 3123 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3124 dma-names = "tx", "rx"; 3125 #address-cells = <1>; 3126 #size-cells = <0>; 3127 status = "disabled"; 3128 }; 3129 3130 blsp2_dma: dma-controller@7584000 { 3131 compatible = "qcom,bam-v1.7.0"; 3132 reg = <0x07584000 0x2b000>; 3133 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3134 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3135 clock-names = "bam_clk"; 3136 qcom,controlled-remotely; 3137 #dma-cells = <1>; 3138 qcom,ee = <0>; 3139 }; 3140 3141 blsp2_uart2: serial@75b0000 { 3142 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3143 reg = <0x075b0000 0x1000>; 3144 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3145 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3146 <&gcc GCC_BLSP2_AHB_CLK>; 3147 clock-names = "core", "iface"; 3148 status = "disabled"; 3149 }; 3150 3151 blsp2_uart3: serial@75b1000 { 3152 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3153 reg = <0x075b1000 0x1000>; 3154 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3155 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3156 <&gcc GCC_BLSP2_AHB_CLK>; 3157 clock-names = "core", "iface"; 3158 status = "disabled"; 3159 }; 3160 3161 blsp2_i2c1: i2c@75b5000 { 3162 compatible = "qcom,i2c-qup-v2.2.1"; 3163 reg = <0x075b5000 0x1000>; 3164 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3165 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3166 <&gcc GCC_BLSP2_AHB_CLK>; 3167 clock-names = "core", "iface"; 3168 pinctrl-names = "default", "sleep"; 3169 pinctrl-0 = <&blsp2_i2c1_default>; 3170 pinctrl-1 = <&blsp2_i2c1_sleep>; 3171 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3172 dma-names = "tx", "rx"; 3173 #address-cells = <1>; 3174 #size-cells = <0>; 3175 status = "disabled"; 3176 }; 3177 3178 blsp2_i2c2: i2c@75b6000 { 3179 compatible = "qcom,i2c-qup-v2.2.1"; 3180 reg = <0x075b6000 0x1000>; 3181 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3182 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3183 <&gcc GCC_BLSP2_AHB_CLK>; 3184 clock-names = "core", "iface"; 3185 pinctrl-names = "default", "sleep"; 3186 pinctrl-0 = <&blsp2_i2c2_default>; 3187 pinctrl-1 = <&blsp2_i2c2_sleep>; 3188 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3189 dma-names = "tx", "rx"; 3190 #address-cells = <1>; 3191 #size-cells = <0>; 3192 status = "disabled"; 3193 }; 3194 3195 blsp2_i2c3: i2c@75b7000 { 3196 compatible = "qcom,i2c-qup-v2.2.1"; 3197 reg = <0x075b7000 0x1000>; 3198 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3199 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3200 <&gcc GCC_BLSP2_AHB_CLK>; 3201 clock-names = "core", "iface"; 3202 clock-frequency = <400000>; 3203 pinctrl-names = "default", "sleep"; 3204 pinctrl-0 = <&blsp2_i2c3_default>; 3205 pinctrl-1 = <&blsp2_i2c3_sleep>; 3206 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3207 dma-names = "tx", "rx"; 3208 #address-cells = <1>; 3209 #size-cells = <0>; 3210 status = "disabled"; 3211 }; 3212 3213 blsp2_i2c5: i2c@75b9000 { 3214 compatible = "qcom,i2c-qup-v2.2.1"; 3215 reg = <0x75b9000 0x1000>; 3216 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3217 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3218 <&gcc GCC_BLSP2_AHB_CLK>; 3219 clock-names = "core", "iface"; 3220 pinctrl-names = "default"; 3221 pinctrl-0 = <&blsp2_i2c5_default>; 3222 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3223 dma-names = "tx", "rx"; 3224 #address-cells = <1>; 3225 #size-cells = <0>; 3226 status = "disabled"; 3227 }; 3228 3229 blsp2_i2c6: i2c@75ba000 { 3230 compatible = "qcom,i2c-qup-v2.2.1"; 3231 reg = <0x75ba000 0x1000>; 3232 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3233 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3234 <&gcc GCC_BLSP2_AHB_CLK>; 3235 clock-names = "core", "iface"; 3236 pinctrl-names = "default", "sleep"; 3237 pinctrl-0 = <&blsp2_i2c6_default>; 3238 pinctrl-1 = <&blsp2_i2c6_sleep>; 3239 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3240 dma-names = "tx", "rx"; 3241 #address-cells = <1>; 3242 #size-cells = <0>; 3243 status = "disabled"; 3244 }; 3245 3246 blsp2_spi6: spi@75ba000{ 3247 compatible = "qcom,spi-qup-v2.2.1"; 3248 reg = <0x075ba000 0x600>; 3249 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3250 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3251 <&gcc GCC_BLSP2_AHB_CLK>; 3252 clock-names = "core", "iface"; 3253 pinctrl-names = "default", "sleep"; 3254 pinctrl-0 = <&blsp2_spi6_default>; 3255 pinctrl-1 = <&blsp2_spi6_sleep>; 3256 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3257 dma-names = "tx", "rx"; 3258 #address-cells = <1>; 3259 #size-cells = <0>; 3260 status = "disabled"; 3261 }; 3262 3263 usb2: usb@76f8800 { 3264 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3265 reg = <0x076f8800 0x400>; 3266 #address-cells = <1>; 3267 #size-cells = <1>; 3268 ranges; 3269 3270 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3271 <&gcc GCC_USB20_MASTER_CLK>, 3272 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3273 <&gcc GCC_USB20_SLEEP_CLK>, 3274 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3275 clock-names = "cfg_noc", 3276 "core", 3277 "iface", 3278 "sleep", 3279 "mock_utmi"; 3280 3281 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3282 <&gcc GCC_USB20_MASTER_CLK>; 3283 assigned-clock-rates = <19200000>, <60000000>; 3284 3285 power-domains = <&gcc USB30_GDSC>; 3286 qcom,select-utmi-as-pipe-clk; 3287 status = "disabled"; 3288 3289 usb2_dwc3: usb@7600000 { 3290 compatible = "snps,dwc3"; 3291 reg = <0x07600000 0xcc00>; 3292 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3293 phys = <&hsusb_phy2>; 3294 phy-names = "usb2-phy"; 3295 maximum-speed = "high-speed"; 3296 snps,dis_u2_susphy_quirk; 3297 snps,dis_enblslpm_quirk; 3298 }; 3299 }; 3300 3301 slimbam: dma-controller@9184000 { 3302 compatible = "qcom,bam-v1.7.0"; 3303 qcom,controlled-remotely; 3304 reg = <0x09184000 0x32000>; 3305 num-channels = <31>; 3306 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3307 #dma-cells = <1>; 3308 qcom,ee = <1>; 3309 qcom,num-ees = <2>; 3310 }; 3311 3312 slim_msm: slim@91c0000 { 3313 compatible = "qcom,slim-ngd-v1.5.0"; 3314 reg = <0x091c0000 0x2C000>; 3315 reg-names = "ctrl"; 3316 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3317 dmas = <&slimbam 3>, <&slimbam 4>, 3318 <&slimbam 5>, <&slimbam 6>; 3319 dma-names = "rx", "tx", "tx2", "rx2"; 3320 #address-cells = <1>; 3321 #size-cells = <0>; 3322 ngd@1 { 3323 reg = <1>; 3324 #address-cells = <1>; 3325 #size-cells = <1>; 3326 3327 tasha_ifd: tas-ifd { 3328 compatible = "slim217,1a0"; 3329 reg = <0 0>; 3330 }; 3331 3332 wcd9335: codec@1{ 3333 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3334 pinctrl-names = "default"; 3335 3336 compatible = "slim217,1a0"; 3337 reg = <1 0>; 3338 3339 interrupt-parent = <&tlmm>; 3340 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3341 <53 IRQ_TYPE_LEVEL_HIGH>; 3342 interrupt-names = "intr1", "intr2"; 3343 interrupt-controller; 3344 #interrupt-cells = <1>; 3345 reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; 3346 3347 slim-ifc-dev = <&tasha_ifd>; 3348 3349 #sound-dai-cells = <1>; 3350 }; 3351 }; 3352 }; 3353 3354 adsp_pil: remoteproc@9300000 { 3355 compatible = "qcom,msm8996-adsp-pil"; 3356 reg = <0x09300000 0x80000>; 3357 3358 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3359 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3360 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3361 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3362 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3363 interrupt-names = "wdog", "fatal", "ready", 3364 "handover", "stop-ack"; 3365 3366 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 3367 clock-names = "xo"; 3368 3369 memory-region = <&adsp_mem>; 3370 3371 qcom,smem-states = <&adsp_smp2p_out 0>; 3372 qcom,smem-state-names = "stop"; 3373 3374 power-domains = <&rpmpd MSM8996_VDDCX>; 3375 power-domain-names = "cx"; 3376 3377 status = "disabled"; 3378 3379 smd-edge { 3380 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3381 3382 label = "lpass"; 3383 mboxes = <&apcs_glb 8>; 3384 qcom,smd-edge = <1>; 3385 qcom,remote-pid = <2>; 3386 #address-cells = <1>; 3387 #size-cells = <0>; 3388 apr { 3389 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3390 compatible = "qcom,apr-v2"; 3391 qcom,smd-channels = "apr_audio_svc"; 3392 qcom,domain = <APR_DOMAIN_ADSP>; 3393 #address-cells = <1>; 3394 #size-cells = <0>; 3395 3396 q6core { 3397 reg = <APR_SVC_ADSP_CORE>; 3398 compatible = "qcom,q6core"; 3399 }; 3400 3401 q6afe: q6afe { 3402 compatible = "qcom,q6afe"; 3403 reg = <APR_SVC_AFE>; 3404 q6afedai: dais { 3405 compatible = "qcom,q6afe-dais"; 3406 #address-cells = <1>; 3407 #size-cells = <0>; 3408 #sound-dai-cells = <1>; 3409 hdmi@1 { 3410 reg = <1>; 3411 }; 3412 }; 3413 }; 3414 3415 q6asm: q6asm { 3416 compatible = "qcom,q6asm"; 3417 reg = <APR_SVC_ASM>; 3418 q6asmdai: dais { 3419 compatible = "qcom,q6asm-dais"; 3420 #address-cells = <1>; 3421 #size-cells = <0>; 3422 #sound-dai-cells = <1>; 3423 iommus = <&lpass_q6_smmu 1>; 3424 }; 3425 }; 3426 3427 q6adm: q6adm { 3428 compatible = "qcom,q6adm"; 3429 reg = <APR_SVC_ADM>; 3430 q6routing: routing { 3431 compatible = "qcom,q6adm-routing"; 3432 #sound-dai-cells = <0>; 3433 }; 3434 }; 3435 }; 3436 3437 }; 3438 }; 3439 3440 apcs_glb: mailbox@9820000 { 3441 compatible = "qcom,msm8996-apcs-hmss-global"; 3442 reg = <0x09820000 0x1000>; 3443 3444 #mbox-cells = <1>; 3445 }; 3446 3447 timer@9840000 { 3448 #address-cells = <1>; 3449 #size-cells = <1>; 3450 ranges; 3451 compatible = "arm,armv7-timer-mem"; 3452 reg = <0x09840000 0x1000>; 3453 clock-frequency = <19200000>; 3454 3455 frame@9850000 { 3456 frame-number = <0>; 3457 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3459 reg = <0x09850000 0x1000>, 3460 <0x09860000 0x1000>; 3461 }; 3462 3463 frame@9870000 { 3464 frame-number = <1>; 3465 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3466 reg = <0x09870000 0x1000>; 3467 status = "disabled"; 3468 }; 3469 3470 frame@9880000 { 3471 frame-number = <2>; 3472 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3473 reg = <0x09880000 0x1000>; 3474 status = "disabled"; 3475 }; 3476 3477 frame@9890000 { 3478 frame-number = <3>; 3479 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3480 reg = <0x09890000 0x1000>; 3481 status = "disabled"; 3482 }; 3483 3484 frame@98a0000 { 3485 frame-number = <4>; 3486 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3487 reg = <0x098a0000 0x1000>; 3488 status = "disabled"; 3489 }; 3490 3491 frame@98b0000 { 3492 frame-number = <5>; 3493 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3494 reg = <0x098b0000 0x1000>; 3495 status = "disabled"; 3496 }; 3497 3498 frame@98c0000 { 3499 frame-number = <6>; 3500 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3501 reg = <0x098c0000 0x1000>; 3502 status = "disabled"; 3503 }; 3504 }; 3505 3506 saw3: syscon@9a10000 { 3507 compatible = "qcom,tcsr-msm8996", "syscon"; 3508 reg = <0x09a10000 0x1000>; 3509 }; 3510 3511 intc: interrupt-controller@9bc0000 { 3512 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3513 #interrupt-cells = <3>; 3514 interrupt-controller; 3515 #redistributor-regions = <1>; 3516 redistributor-stride = <0x0 0x40000>; 3517 reg = <0x09bc0000 0x10000>, 3518 <0x09c00000 0x100000>; 3519 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3520 }; 3521 }; 3522 3523 sound: sound { 3524 }; 3525 3526 thermal-zones { 3527 cpu0-thermal { 3528 polling-delay-passive = <250>; 3529 polling-delay = <1000>; 3530 3531 thermal-sensors = <&tsens0 3>; 3532 3533 trips { 3534 cpu0_alert0: trip-point0 { 3535 temperature = <75000>; 3536 hysteresis = <2000>; 3537 type = "passive"; 3538 }; 3539 3540 cpu0_crit: cpu_crit { 3541 temperature = <110000>; 3542 hysteresis = <2000>; 3543 type = "critical"; 3544 }; 3545 }; 3546 }; 3547 3548 cpu1-thermal { 3549 polling-delay-passive = <250>; 3550 polling-delay = <1000>; 3551 3552 thermal-sensors = <&tsens0 5>; 3553 3554 trips { 3555 cpu1_alert0: trip-point0 { 3556 temperature = <75000>; 3557 hysteresis = <2000>; 3558 type = "passive"; 3559 }; 3560 3561 cpu1_crit: cpu_crit { 3562 temperature = <110000>; 3563 hysteresis = <2000>; 3564 type = "critical"; 3565 }; 3566 }; 3567 }; 3568 3569 cpu2-thermal { 3570 polling-delay-passive = <250>; 3571 polling-delay = <1000>; 3572 3573 thermal-sensors = <&tsens0 8>; 3574 3575 trips { 3576 cpu2_alert0: trip-point0 { 3577 temperature = <75000>; 3578 hysteresis = <2000>; 3579 type = "passive"; 3580 }; 3581 3582 cpu2_crit: cpu_crit { 3583 temperature = <110000>; 3584 hysteresis = <2000>; 3585 type = "critical"; 3586 }; 3587 }; 3588 }; 3589 3590 cpu3-thermal { 3591 polling-delay-passive = <250>; 3592 polling-delay = <1000>; 3593 3594 thermal-sensors = <&tsens0 10>; 3595 3596 trips { 3597 cpu3_alert0: trip-point0 { 3598 temperature = <75000>; 3599 hysteresis = <2000>; 3600 type = "passive"; 3601 }; 3602 3603 cpu3_crit: cpu_crit { 3604 temperature = <110000>; 3605 hysteresis = <2000>; 3606 type = "critical"; 3607 }; 3608 }; 3609 }; 3610 3611 gpu-top-thermal { 3612 polling-delay-passive = <250>; 3613 polling-delay = <1000>; 3614 3615 thermal-sensors = <&tsens1 6>; 3616 3617 trips { 3618 gpu1_alert0: trip-point0 { 3619 temperature = <90000>; 3620 hysteresis = <2000>; 3621 type = "passive"; 3622 }; 3623 }; 3624 3625 cooling-maps { 3626 map0 { 3627 trip = <&gpu1_alert0>; 3628 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3629 }; 3630 }; 3631 }; 3632 3633 gpu-bottom-thermal { 3634 polling-delay-passive = <250>; 3635 polling-delay = <1000>; 3636 3637 thermal-sensors = <&tsens1 7>; 3638 3639 trips { 3640 gpu2_alert0: trip-point0 { 3641 temperature = <90000>; 3642 hysteresis = <2000>; 3643 type = "passive"; 3644 }; 3645 }; 3646 3647 cooling-maps { 3648 map0 { 3649 trip = <&gpu2_alert0>; 3650 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3651 }; 3652 }; 3653 }; 3654 3655 m4m-thermal { 3656 polling-delay-passive = <250>; 3657 polling-delay = <1000>; 3658 3659 thermal-sensors = <&tsens0 1>; 3660 3661 trips { 3662 m4m_alert0: trip-point0 { 3663 temperature = <90000>; 3664 hysteresis = <2000>; 3665 type = "hot"; 3666 }; 3667 }; 3668 }; 3669 3670 l3-or-venus-thermal { 3671 polling-delay-passive = <250>; 3672 polling-delay = <1000>; 3673 3674 thermal-sensors = <&tsens0 2>; 3675 3676 trips { 3677 l3_or_venus_alert0: trip-point0 { 3678 temperature = <90000>; 3679 hysteresis = <2000>; 3680 type = "hot"; 3681 }; 3682 }; 3683 }; 3684 3685 cluster0-l2-thermal { 3686 polling-delay-passive = <250>; 3687 polling-delay = <1000>; 3688 3689 thermal-sensors = <&tsens0 7>; 3690 3691 trips { 3692 cluster0_l2_alert0: trip-point0 { 3693 temperature = <90000>; 3694 hysteresis = <2000>; 3695 type = "hot"; 3696 }; 3697 }; 3698 }; 3699 3700 cluster1-l2-thermal { 3701 polling-delay-passive = <250>; 3702 polling-delay = <1000>; 3703 3704 thermal-sensors = <&tsens0 12>; 3705 3706 trips { 3707 cluster1_l2_alert0: trip-point0 { 3708 temperature = <90000>; 3709 hysteresis = <2000>; 3710 type = "hot"; 3711 }; 3712 }; 3713 }; 3714 3715 camera-thermal { 3716 polling-delay-passive = <250>; 3717 polling-delay = <1000>; 3718 3719 thermal-sensors = <&tsens1 1>; 3720 3721 trips { 3722 camera_alert0: trip-point0 { 3723 temperature = <90000>; 3724 hysteresis = <2000>; 3725 type = "hot"; 3726 }; 3727 }; 3728 }; 3729 3730 q6-dsp-thermal { 3731 polling-delay-passive = <250>; 3732 polling-delay = <1000>; 3733 3734 thermal-sensors = <&tsens1 2>; 3735 3736 trips { 3737 q6_dsp_alert0: trip-point0 { 3738 temperature = <90000>; 3739 hysteresis = <2000>; 3740 type = "hot"; 3741 }; 3742 }; 3743 }; 3744 3745 mem-thermal { 3746 polling-delay-passive = <250>; 3747 polling-delay = <1000>; 3748 3749 thermal-sensors = <&tsens1 3>; 3750 3751 trips { 3752 mem_alert0: trip-point0 { 3753 temperature = <90000>; 3754 hysteresis = <2000>; 3755 type = "hot"; 3756 }; 3757 }; 3758 }; 3759 3760 modemtx-thermal { 3761 polling-delay-passive = <250>; 3762 polling-delay = <1000>; 3763 3764 thermal-sensors = <&tsens1 4>; 3765 3766 trips { 3767 modemtx_alert0: trip-point0 { 3768 temperature = <90000>; 3769 hysteresis = <2000>; 3770 type = "hot"; 3771 }; 3772 }; 3773 }; 3774 }; 3775 3776 timer { 3777 compatible = "arm,armv8-timer"; 3778 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3779 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3780 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3781 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3782 }; 3783}; 3784