1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7180.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/phy/phy-qcom-qusb2.h> 12#include <dt-bindings/power/qcom-aoss-qmp.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/reset/qcom,sdm845-aoss.h> 15#include <dt-bindings/reset/qcom,sdm845-pdc.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 aliases { 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 i2c3 = &i2c3; 32 i2c4 = &i2c4; 33 i2c5 = &i2c5; 34 i2c6 = &i2c6; 35 i2c7 = &i2c7; 36 i2c8 = &i2c8; 37 i2c9 = &i2c9; 38 i2c10 = &i2c10; 39 i2c11 = &i2c11; 40 spi0 = &spi0; 41 spi1 = &spi1; 42 spi3 = &spi3; 43 spi5 = &spi5; 44 spi6 = &spi6; 45 spi8 = &spi8; 46 spi10 = &spi10; 47 spi11 = &spi11; 48 }; 49 50 clocks { 51 xo_board: xo-board { 52 compatible = "fixed-clock"; 53 clock-frequency = <38400000>; 54 #clock-cells = <0>; 55 }; 56 57 sleep_clk: sleep-clk { 58 compatible = "fixed-clock"; 59 clock-frequency = <32764>; 60 #clock-cells = <0>; 61 }; 62 }; 63 64 reserved_memory: reserved-memory { 65 #address-cells = <2>; 66 #size-cells = <2>; 67 ranges; 68 69 aop_cmd_db_mem: memory@80820000 { 70 reg = <0x0 0x80820000 0x0 0x20000>; 71 compatible = "qcom,cmd-db"; 72 }; 73 74 smem_mem: memory@80900000 { 75 reg = <0x0 0x80900000 0x0 0x200000>; 76 no-map; 77 }; 78 }; 79 80 cpus { 81 #address-cells = <2>; 82 #size-cells = <0>; 83 84 CPU0: cpu@0 { 85 device_type = "cpu"; 86 compatible = "arm,armv8"; 87 reg = <0x0 0x0>; 88 enable-method = "psci"; 89 next-level-cache = <&L2_0>; 90 #cooling-cells = <2>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 L2_0: l2-cache { 93 compatible = "cache"; 94 next-level-cache = <&L3_0>; 95 L3_0: l3-cache { 96 compatible = "cache"; 97 }; 98 }; 99 }; 100 101 CPU1: cpu@100 { 102 device_type = "cpu"; 103 compatible = "arm,armv8"; 104 reg = <0x0 0x100>; 105 enable-method = "psci"; 106 next-level-cache = <&L2_100>; 107 #cooling-cells = <2>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU2: cpu@200 { 116 device_type = "cpu"; 117 compatible = "arm,armv8"; 118 reg = <0x0 0x200>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_200>; 121 #cooling-cells = <2>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 L2_200: l2-cache { 124 compatible = "cache"; 125 next-level-cache = <&L3_0>; 126 }; 127 }; 128 129 CPU3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,armv8"; 132 reg = <0x0 0x300>; 133 enable-method = "psci"; 134 next-level-cache = <&L2_300>; 135 #cooling-cells = <2>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 L2_300: l2-cache { 138 compatible = "cache"; 139 next-level-cache = <&L3_0>; 140 }; 141 }; 142 143 CPU4: cpu@400 { 144 device_type = "cpu"; 145 compatible = "arm,armv8"; 146 reg = <0x0 0x400>; 147 enable-method = "psci"; 148 next-level-cache = <&L2_400>; 149 #cooling-cells = <2>; 150 qcom,freq-domain = <&cpufreq_hw 0>; 151 L2_400: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU5: cpu@500 { 158 device_type = "cpu"; 159 compatible = "arm,armv8"; 160 reg = <0x0 0x500>; 161 enable-method = "psci"; 162 next-level-cache = <&L2_500>; 163 #cooling-cells = <2>; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 next-level-cache = <&L3_0>; 168 }; 169 }; 170 171 CPU6: cpu@600 { 172 device_type = "cpu"; 173 compatible = "arm,armv8"; 174 reg = <0x0 0x600>; 175 enable-method = "psci"; 176 next-level-cache = <&L2_600>; 177 #cooling-cells = <2>; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 L2_600: l2-cache { 180 compatible = "cache"; 181 next-level-cache = <&L3_0>; 182 }; 183 }; 184 185 CPU7: cpu@700 { 186 device_type = "cpu"; 187 compatible = "arm,armv8"; 188 reg = <0x0 0x700>; 189 enable-method = "psci"; 190 next-level-cache = <&L2_700>; 191 #cooling-cells = <2>; 192 qcom,freq-domain = <&cpufreq_hw 1>; 193 L2_700: l2-cache { 194 compatible = "cache"; 195 next-level-cache = <&L3_0>; 196 }; 197 }; 198 }; 199 200 memory@80000000 { 201 device_type = "memory"; 202 /* We expect the bootloader to fill in the size */ 203 reg = <0 0x80000000 0 0>; 204 }; 205 206 pmu { 207 compatible = "arm,armv8-pmuv3"; 208 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 209 }; 210 211 firmware { 212 scm { 213 compatible = "qcom,scm-sc7180", "qcom,scm"; 214 }; 215 }; 216 217 tcsr_mutex: hwlock { 218 compatible = "qcom,tcsr-mutex"; 219 syscon = <&tcsr_mutex_regs 0 0x1000>; 220 #hwlock-cells = <1>; 221 }; 222 223 smem { 224 compatible = "qcom,smem"; 225 memory-region = <&smem_mem>; 226 hwlocks = <&tcsr_mutex 3>; 227 }; 228 229 smp2p-cdsp { 230 compatible = "qcom,smp2p"; 231 qcom,smem = <94>, <432>; 232 233 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 234 235 mboxes = <&apss_shared 6>; 236 237 qcom,local-pid = <0>; 238 qcom,remote-pid = <5>; 239 240 cdsp_smp2p_out: master-kernel { 241 qcom,entry-name = "master-kernel"; 242 #qcom,smem-state-cells = <1>; 243 }; 244 245 cdsp_smp2p_in: slave-kernel { 246 qcom,entry-name = "slave-kernel"; 247 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 }; 251 }; 252 253 smp2p-lpass { 254 compatible = "qcom,smp2p"; 255 qcom,smem = <443>, <429>; 256 257 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 258 259 mboxes = <&apss_shared 10>; 260 261 qcom,local-pid = <0>; 262 qcom,remote-pid = <2>; 263 264 adsp_smp2p_out: master-kernel { 265 qcom,entry-name = "master-kernel"; 266 #qcom,smem-state-cells = <1>; 267 }; 268 269 adsp_smp2p_in: slave-kernel { 270 qcom,entry-name = "slave-kernel"; 271 272 interrupt-controller; 273 #interrupt-cells = <2>; 274 }; 275 }; 276 277 smp2p-mpss { 278 compatible = "qcom,smp2p"; 279 qcom,smem = <435>, <428>; 280 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 281 mboxes = <&apss_shared 14>; 282 qcom,local-pid = <0>; 283 qcom,remote-pid = <1>; 284 285 modem_smp2p_out: master-kernel { 286 qcom,entry-name = "master-kernel"; 287 #qcom,smem-state-cells = <1>; 288 }; 289 290 modem_smp2p_in: slave-kernel { 291 qcom,entry-name = "slave-kernel"; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 }; 295 }; 296 297 psci { 298 compatible = "arm,psci-1.0"; 299 method = "smc"; 300 }; 301 302 soc: soc { 303 #address-cells = <2>; 304 #size-cells = <2>; 305 ranges = <0 0 0 0 0x10 0>; 306 dma-ranges = <0 0 0 0 0x10 0>; 307 compatible = "simple-bus"; 308 309 gcc: clock-controller@100000 { 310 compatible = "qcom,gcc-sc7180"; 311 reg = <0 0x00100000 0 0x1f0000>; 312 clocks = <&rpmhcc RPMH_CXO_CLK>, 313 <&rpmhcc RPMH_CXO_CLK_A>; 314 clock-names = "bi_tcxo", "bi_tcxo_ao"; 315 #clock-cells = <1>; 316 #reset-cells = <1>; 317 #power-domain-cells = <1>; 318 }; 319 320 qfprom@784000 { 321 compatible = "qcom,qfprom"; 322 reg = <0 0x00784000 0 0x8ff>; 323 #address-cells = <1>; 324 #size-cells = <1>; 325 326 qusb2p_hstx_trim: hstx-trim-primary@25b { 327 reg = <0x25b 0x1>; 328 bits = <1 3>; 329 }; 330 }; 331 332 qupv3_id_0: geniqup@8c0000 { 333 compatible = "qcom,geni-se-qup"; 334 reg = <0 0x008c0000 0 0x6000>; 335 clock-names = "m-ahb", "s-ahb"; 336 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 337 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 338 #address-cells = <2>; 339 #size-cells = <2>; 340 ranges; 341 status = "disabled"; 342 343 i2c0: i2c@880000 { 344 compatible = "qcom,geni-i2c"; 345 reg = <0 0x00880000 0 0x4000>; 346 clock-names = "se"; 347 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&qup_i2c0_default>; 350 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 status = "disabled"; 354 }; 355 356 spi0: spi@880000 { 357 compatible = "qcom,geni-spi"; 358 reg = <0 0x00880000 0 0x4000>; 359 clock-names = "se"; 360 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&qup_spi0_default>; 363 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 status = "disabled"; 367 }; 368 369 uart0: serial@880000 { 370 compatible = "qcom,geni-uart"; 371 reg = <0 0x00880000 0 0x4000>; 372 clock-names = "se"; 373 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&qup_uart0_default>; 376 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 377 status = "disabled"; 378 }; 379 380 i2c1: i2c@884000 { 381 compatible = "qcom,geni-i2c"; 382 reg = <0 0x00884000 0 0x4000>; 383 clock-names = "se"; 384 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&qup_i2c1_default>; 387 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 spi1: spi@884000 { 394 compatible = "qcom,geni-spi"; 395 reg = <0 0x00884000 0 0x4000>; 396 clock-names = "se"; 397 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&qup_spi1_default>; 400 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 }; 405 406 uart1: serial@884000 { 407 compatible = "qcom,geni-uart"; 408 reg = <0 0x00884000 0 0x4000>; 409 clock-names = "se"; 410 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&qup_uart1_default>; 413 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 414 status = "disabled"; 415 }; 416 417 i2c2: i2c@888000 { 418 compatible = "qcom,geni-i2c"; 419 reg = <0 0x00888000 0 0x4000>; 420 clock-names = "se"; 421 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&qup_i2c2_default>; 424 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 status = "disabled"; 428 }; 429 430 uart2: serial@888000 { 431 compatible = "qcom,geni-uart"; 432 reg = <0 0x00888000 0 0x4000>; 433 clock-names = "se"; 434 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&qup_uart2_default>; 437 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 438 status = "disabled"; 439 }; 440 441 i2c3: i2c@88c000 { 442 compatible = "qcom,geni-i2c"; 443 reg = <0 0x0088c000 0 0x4000>; 444 clock-names = "se"; 445 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&qup_i2c3_default>; 448 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 status = "disabled"; 452 }; 453 454 spi3: spi@88c000 { 455 compatible = "qcom,geni-spi"; 456 reg = <0 0x0088c000 0 0x4000>; 457 clock-names = "se"; 458 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&qup_spi3_default>; 461 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 uart3: serial@88c000 { 468 compatible = "qcom,geni-uart"; 469 reg = <0 0x0088c000 0 0x4000>; 470 clock-names = "se"; 471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&qup_uart3_default>; 474 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 475 status = "disabled"; 476 }; 477 478 i2c4: i2c@890000 { 479 compatible = "qcom,geni-i2c"; 480 reg = <0 0x00890000 0 0x4000>; 481 clock-names = "se"; 482 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&qup_i2c4_default>; 485 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 status = "disabled"; 489 }; 490 491 uart4: serial@890000 { 492 compatible = "qcom,geni-uart"; 493 reg = <0 0x00890000 0 0x4000>; 494 clock-names = "se"; 495 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&qup_uart4_default>; 498 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 499 status = "disabled"; 500 }; 501 502 i2c5: i2c@894000 { 503 compatible = "qcom,geni-i2c"; 504 reg = <0 0x00894000 0 0x4000>; 505 clock-names = "se"; 506 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&qup_i2c5_default>; 509 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 status = "disabled"; 513 }; 514 515 spi5: spi@894000 { 516 compatible = "qcom,geni-spi"; 517 reg = <0 0x00894000 0 0x4000>; 518 clock-names = "se"; 519 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&qup_spi5_default>; 522 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 }; 527 528 uart5: serial@894000 { 529 compatible = "qcom,geni-uart"; 530 reg = <0 0x00894000 0 0x4000>; 531 clock-names = "se"; 532 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&qup_uart5_default>; 535 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 536 status = "disabled"; 537 }; 538 }; 539 540 qupv3_id_1: geniqup@ac0000 { 541 compatible = "qcom,geni-se-qup"; 542 reg = <0 0x00ac0000 0 0x6000>; 543 clock-names = "m-ahb", "s-ahb"; 544 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 545 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 546 #address-cells = <2>; 547 #size-cells = <2>; 548 ranges; 549 status = "disabled"; 550 551 i2c6: i2c@a80000 { 552 compatible = "qcom,geni-i2c"; 553 reg = <0 0x00a80000 0 0x4000>; 554 clock-names = "se"; 555 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&qup_i2c6_default>; 558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 status = "disabled"; 562 }; 563 564 spi6: spi@a80000 { 565 compatible = "qcom,geni-spi"; 566 reg = <0 0x00a80000 0 0x4000>; 567 clock-names = "se"; 568 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&qup_spi6_default>; 571 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 status = "disabled"; 575 }; 576 577 uart6: serial@a80000 { 578 compatible = "qcom,geni-uart"; 579 reg = <0 0x00a80000 0 0x4000>; 580 clock-names = "se"; 581 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&qup_uart6_default>; 584 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 585 status = "disabled"; 586 }; 587 588 i2c7: i2c@a84000 { 589 compatible = "qcom,geni-i2c"; 590 reg = <0 0x00a84000 0 0x4000>; 591 clock-names = "se"; 592 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&qup_i2c7_default>; 595 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 uart7: serial@a84000 { 602 compatible = "qcom,geni-uart"; 603 reg = <0 0x00a84000 0 0x4000>; 604 clock-names = "se"; 605 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&qup_uart7_default>; 608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 609 status = "disabled"; 610 }; 611 612 i2c8: i2c@a88000 { 613 compatible = "qcom,geni-i2c"; 614 reg = <0 0x00a88000 0 0x4000>; 615 clock-names = "se"; 616 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&qup_i2c8_default>; 619 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 spi8: spi@a88000 { 626 compatible = "qcom,geni-spi"; 627 reg = <0 0x00a88000 0 0x4000>; 628 clock-names = "se"; 629 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&qup_spi8_default>; 632 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 uart8: serial@a88000 { 639 compatible = "qcom,geni-debug-uart"; 640 reg = <0 0x00a88000 0 0x4000>; 641 clock-names = "se"; 642 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&qup_uart8_default>; 645 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 646 status = "disabled"; 647 }; 648 649 i2c9: i2c@a8c000 { 650 compatible = "qcom,geni-i2c"; 651 reg = <0 0x00a8c000 0 0x4000>; 652 clock-names = "se"; 653 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&qup_i2c9_default>; 656 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 uart9: serial@a8c000 { 663 compatible = "qcom,geni-uart"; 664 reg = <0 0x00a8c000 0 0x4000>; 665 clock-names = "se"; 666 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&qup_uart9_default>; 669 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 670 status = "disabled"; 671 }; 672 673 i2c10: i2c@a90000 { 674 compatible = "qcom,geni-i2c"; 675 reg = <0 0x00a90000 0 0x4000>; 676 clock-names = "se"; 677 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&qup_i2c10_default>; 680 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 status = "disabled"; 684 }; 685 686 spi10: spi@a90000 { 687 compatible = "qcom,geni-spi"; 688 reg = <0 0x00a90000 0 0x4000>; 689 clock-names = "se"; 690 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&qup_spi10_default>; 693 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 status = "disabled"; 697 }; 698 699 uart10: serial@a90000 { 700 compatible = "qcom,geni-uart"; 701 reg = <0 0x00a90000 0 0x4000>; 702 clock-names = "se"; 703 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&qup_uart10_default>; 706 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 707 status = "disabled"; 708 }; 709 710 i2c11: i2c@a94000 { 711 compatible = "qcom,geni-i2c"; 712 reg = <0 0x00a94000 0 0x4000>; 713 clock-names = "se"; 714 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&qup_i2c11_default>; 717 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 status = "disabled"; 721 }; 722 723 spi11: spi@a94000 { 724 compatible = "qcom,geni-spi"; 725 reg = <0 0x00a94000 0 0x4000>; 726 clock-names = "se"; 727 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&qup_spi11_default>; 730 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 uart11: serial@a94000 { 737 compatible = "qcom,geni-uart"; 738 reg = <0 0x00a94000 0 0x4000>; 739 clock-names = "se"; 740 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&qup_uart11_default>; 743 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 744 status = "disabled"; 745 }; 746 }; 747 748 tcsr_mutex_regs: syscon@1f40000 { 749 compatible = "syscon"; 750 reg = <0 0x01f40000 0 0x40000>; 751 }; 752 753 tlmm: pinctrl@3500000 { 754 compatible = "qcom,sc7180-pinctrl"; 755 reg = <0 0x03500000 0 0x300000>, 756 <0 0x03900000 0 0x300000>, 757 <0 0x03d00000 0 0x300000>; 758 reg-names = "west", "north", "south"; 759 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 760 gpio-controller; 761 #gpio-cells = <2>; 762 interrupt-controller; 763 #interrupt-cells = <2>; 764 gpio-ranges = <&tlmm 0 0 120>; 765 wakeup-parent = <&pdc>; 766 767 qspi_clk: qspi-clk { 768 pinmux { 769 pins = "gpio63"; 770 function = "qspi_clk"; 771 }; 772 }; 773 774 qspi_cs0: qspi-cs0 { 775 pinmux { 776 pins = "gpio68"; 777 function = "qspi_cs"; 778 }; 779 }; 780 781 qspi_cs1: qspi-cs1 { 782 pinmux { 783 pins = "gpio72"; 784 function = "qspi_cs"; 785 }; 786 }; 787 788 qspi_data01: qspi-data01 { 789 pinmux-data { 790 pins = "gpio64", "gpio65"; 791 function = "qspi_data"; 792 }; 793 }; 794 795 qspi_data12: qspi-data12 { 796 pinmux-data { 797 pins = "gpio66", "gpio67"; 798 function = "qspi_data"; 799 }; 800 }; 801 802 qup_i2c0_default: qup-i2c0-default { 803 pinmux { 804 pins = "gpio34", "gpio35"; 805 function = "qup00"; 806 }; 807 }; 808 809 qup_i2c1_default: qup-i2c1-default { 810 pinmux { 811 pins = "gpio0", "gpio1"; 812 function = "qup01"; 813 }; 814 }; 815 816 qup_i2c2_default: qup-i2c2-default { 817 pinmux { 818 pins = "gpio15", "gpio16"; 819 function = "qup02_i2c"; 820 }; 821 }; 822 823 qup_i2c3_default: qup-i2c3-default { 824 pinmux { 825 pins = "gpio38", "gpio39"; 826 function = "qup03"; 827 }; 828 }; 829 830 qup_i2c4_default: qup-i2c4-default { 831 pinmux { 832 pins = "gpio115", "gpio116"; 833 function = "qup04_i2c"; 834 }; 835 }; 836 837 qup_i2c5_default: qup-i2c5-default { 838 pinmux { 839 pins = "gpio25", "gpio26"; 840 function = "qup05"; 841 }; 842 }; 843 844 qup_i2c6_default: qup-i2c6-default { 845 pinmux { 846 pins = "gpio59", "gpio60"; 847 function = "qup10"; 848 }; 849 }; 850 851 qup_i2c7_default: qup-i2c7-default { 852 pinmux { 853 pins = "gpio6", "gpio7"; 854 function = "qup11_i2c"; 855 }; 856 }; 857 858 qup_i2c8_default: qup-i2c8-default { 859 pinmux { 860 pins = "gpio42", "gpio43"; 861 function = "qup12"; 862 }; 863 }; 864 865 qup_i2c9_default: qup-i2c9-default { 866 pinmux { 867 pins = "gpio46", "gpio47"; 868 function = "qup13_i2c"; 869 }; 870 }; 871 872 qup_i2c10_default: qup-i2c10-default { 873 pinmux { 874 pins = "gpio86", "gpio87"; 875 function = "qup14"; 876 }; 877 }; 878 879 qup_i2c11_default: qup-i2c11-default { 880 pinmux { 881 pins = "gpio53", "gpio54"; 882 function = "qup15"; 883 }; 884 }; 885 886 qup_spi0_default: qup-spi0-default { 887 pinmux { 888 pins = "gpio34", "gpio35", 889 "gpio36", "gpio37"; 890 function = "qup00"; 891 }; 892 }; 893 894 qup_spi1_default: qup-spi1-default { 895 pinmux { 896 pins = "gpio0", "gpio1", 897 "gpio2", "gpio3"; 898 function = "qup01"; 899 }; 900 }; 901 902 qup_spi3_default: qup-spi3-default { 903 pinmux { 904 pins = "gpio38", "gpio39", 905 "gpio40", "gpio41"; 906 function = "qup03"; 907 }; 908 }; 909 910 qup_spi5_default: qup-spi5-default { 911 pinmux { 912 pins = "gpio25", "gpio26", 913 "gpio27", "gpio28"; 914 function = "qup05"; 915 }; 916 }; 917 918 qup_spi6_default: qup-spi6-default { 919 pinmux { 920 pins = "gpio59", "gpio60", 921 "gpio61", "gpio62"; 922 function = "qup10"; 923 }; 924 }; 925 926 qup_spi8_default: qup-spi8-default { 927 pinmux { 928 pins = "gpio42", "gpio43", 929 "gpio44", "gpio45"; 930 function = "qup12"; 931 }; 932 }; 933 934 qup_spi10_default: qup-spi10-default { 935 pinmux { 936 pins = "gpio86", "gpio87", 937 "gpio88", "gpio89"; 938 function = "qup14"; 939 }; 940 }; 941 942 qup_spi11_default: qup-spi11-default { 943 pinmux { 944 pins = "gpio53", "gpio54", 945 "gpio55", "gpio56"; 946 function = "qup15"; 947 }; 948 }; 949 950 qup_uart0_default: qup-uart0-default { 951 pinmux { 952 pins = "gpio34", "gpio35", 953 "gpio36", "gpio37"; 954 function = "qup00"; 955 }; 956 }; 957 958 qup_uart1_default: qup-uart1-default { 959 pinmux { 960 pins = "gpio0", "gpio1", 961 "gpio2", "gpio3"; 962 function = "qup01"; 963 }; 964 }; 965 966 qup_uart2_default: qup-uart2-default { 967 pinmux { 968 pins = "gpio15", "gpio16"; 969 function = "qup02_uart"; 970 }; 971 }; 972 973 qup_uart3_default: qup-uart3-default { 974 pinmux { 975 pins = "gpio38", "gpio39", 976 "gpio40", "gpio41"; 977 function = "qup03"; 978 }; 979 }; 980 981 qup_uart4_default: qup-uart4-default { 982 pinmux { 983 pins = "gpio115", "gpio116"; 984 function = "qup04_uart"; 985 }; 986 }; 987 988 qup_uart5_default: qup-uart5-default { 989 pinmux { 990 pins = "gpio25", "gpio26", 991 "gpio27", "gpio28"; 992 function = "qup05"; 993 }; 994 }; 995 996 qup_uart6_default: qup-uart6-default { 997 pinmux { 998 pins = "gpio59", "gpio60", 999 "gpio61", "gpio62"; 1000 function = "qup10"; 1001 }; 1002 }; 1003 1004 qup_uart7_default: qup-uart7-default { 1005 pinmux { 1006 pins = "gpio6", "gpio7"; 1007 function = "qup11_uart"; 1008 }; 1009 }; 1010 1011 qup_uart8_default: qup-uart8-default { 1012 pinmux { 1013 pins = "gpio44", "gpio45"; 1014 function = "qup12"; 1015 }; 1016 }; 1017 1018 qup_uart9_default: qup-uart9-default { 1019 pinmux { 1020 pins = "gpio46", "gpio47"; 1021 function = "qup13_uart"; 1022 }; 1023 }; 1024 1025 qup_uart10_default: qup-uart10-default { 1026 pinmux { 1027 pins = "gpio86", "gpio87", 1028 "gpio88", "gpio89"; 1029 function = "qup14"; 1030 }; 1031 }; 1032 1033 qup_uart11_default: qup-uart11-default { 1034 pinmux { 1035 pins = "gpio53", "gpio54", 1036 "gpio55", "gpio56"; 1037 function = "qup15"; 1038 }; 1039 }; 1040 }; 1041 1042 qspi: spi@88dc000 { 1043 compatible = "qcom,qspi-v1"; 1044 reg = <0 0x088dc000 0 0x600>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 1049 <&gcc GCC_QSPI_CORE_CLK>; 1050 clock-names = "iface", "core"; 1051 status = "disabled"; 1052 }; 1053 1054 usb_1_hsphy: phy@88e3000 { 1055 compatible = "qcom,sc7180-qusb2-phy"; 1056 reg = <0 0x088e3000 0 0x400>; 1057 status = "disabled"; 1058 #phy-cells = <0>; 1059 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1060 <&rpmhcc RPMH_CXO_CLK>; 1061 clock-names = "cfg_ahb", "ref"; 1062 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1063 1064 nvmem-cells = <&qusb2p_hstx_trim>; 1065 }; 1066 1067 usb_1_qmpphy: phy-wrapper@88e9000 { 1068 compatible = "qcom,sc7180-qmp-usb3-phy"; 1069 reg = <0 0x088e9000 0 0x18c>, 1070 <0 0x088e8000 0 0x38>; 1071 reg-names = "reg-base", "dp_com"; 1072 status = "disabled"; 1073 #clock-cells = <1>; 1074 #address-cells = <2>; 1075 #size-cells = <2>; 1076 ranges; 1077 1078 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1079 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1080 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1081 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1082 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1083 1084 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1085 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1086 reset-names = "phy", "common"; 1087 1088 usb_1_ssphy: phy@88e9200 { 1089 reg = <0 0x088e9200 0 0x128>, 1090 <0 0x088e9400 0 0x200>, 1091 <0 0x088e9c00 0 0x218>, 1092 <0 0x088e9600 0 0x128>, 1093 <0 0x088e9800 0 0x200>, 1094 <0 0x088e9a00 0 0x18>; 1095 #clock-cells = <0>; 1096 #phy-cells = <0>; 1097 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1098 clock-names = "pipe0"; 1099 clock-output-names = "usb3_phy_pipe_clk_src"; 1100 }; 1101 }; 1102 1103 system-cache-controller@9200000 { 1104 compatible = "qcom,sc7180-llcc"; 1105 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; 1106 reg-names = "llcc_base", "llcc_broadcast_base"; 1107 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1108 }; 1109 1110 usb_1: usb@a6f8800 { 1111 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 1112 reg = <0 0x0a6f8800 0 0x400>; 1113 status = "disabled"; 1114 #address-cells = <2>; 1115 #size-cells = <2>; 1116 ranges; 1117 dma-ranges; 1118 1119 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1120 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1121 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1122 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1123 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 1124 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 1125 "sleep"; 1126 1127 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1128 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1129 assigned-clock-rates = <19200000>, <150000000>; 1130 1131 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1135 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1136 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1137 1138 power-domains = <&gcc USB30_PRIM_GDSC>; 1139 1140 resets = <&gcc GCC_USB30_PRIM_BCR>; 1141 1142 usb_1_dwc3: dwc3@a600000 { 1143 compatible = "snps,dwc3"; 1144 reg = <0 0x0a600000 0 0xe000>; 1145 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1146 iommus = <&apps_smmu 0x540 0>; 1147 snps,dis_u2_susphy_quirk; 1148 snps,dis_enblslpm_quirk; 1149 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1150 phy-names = "usb2-phy", "usb3-phy"; 1151 }; 1152 }; 1153 1154 pdc: interrupt-controller@b220000 { 1155 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 1156 reg = <0 0x0b220000 0 0x30000>; 1157 qcom,pdc-ranges = <0 480 15>, <17 497 98>, 1158 <119 634 4>, <124 639 1>; 1159 #interrupt-cells = <2>; 1160 interrupt-parent = <&intc>; 1161 interrupt-controller; 1162 }; 1163 1164 pdc_reset: reset-controller@b2e0000 { 1165 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 1166 reg = <0 0x0b2e0000 0 0x20000>; 1167 #reset-cells = <1>; 1168 }; 1169 1170 tsens0: thermal-sensor@c263000 { 1171 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 1172 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1173 <0 0x0c222000 0 0x1ff>; /* SROT */ 1174 #qcom,sensors = <15>; 1175 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 1177 interrupt-names = "uplow","critical"; 1178 #thermal-sensor-cells = <1>; 1179 }; 1180 1181 tsens1: thermal-sensor@c265000 { 1182 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 1183 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1184 <0 0x0c223000 0 0x1ff>; /* SROT */ 1185 #qcom,sensors = <10>; 1186 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 1188 interrupt-names = "uplow","critical"; 1189 #thermal-sensor-cells = <1>; 1190 }; 1191 1192 aoss_reset: reset-controller@c2a0000 { 1193 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 1194 reg = <0 0x0c2a0000 0 0x31000>; 1195 #reset-cells = <1>; 1196 }; 1197 1198 aoss_qmp: qmp@c300000 { 1199 compatible = "qcom,sc7180-aoss-qmp"; 1200 reg = <0 0x0c300000 0 0x100000>; 1201 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 1202 mboxes = <&apss_shared 0>; 1203 1204 #clock-cells = <0>; 1205 #power-domain-cells = <1>; 1206 }; 1207 1208 spmi_bus: spmi@c440000 { 1209 compatible = "qcom,spmi-pmic-arb"; 1210 reg = <0 0x0c440000 0 0x1100>, 1211 <0 0x0c600000 0 0x2000000>, 1212 <0 0x0e600000 0 0x100000>, 1213 <0 0x0e700000 0 0xa0000>, 1214 <0 0x0c40a000 0 0x26000>; 1215 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1216 interrupt-names = "periph_irq"; 1217 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1218 qcom,ee = <0>; 1219 qcom,channel = <0>; 1220 #address-cells = <1>; 1221 #size-cells = <1>; 1222 interrupt-controller; 1223 #interrupt-cells = <4>; 1224 cell-index = <0>; 1225 }; 1226 1227 apps_smmu: iommu@15000000 { 1228 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 1229 reg = <0 0x15000000 0 0x100000>; 1230 #iommu-cells = <2>; 1231 #global-interrupts = <1>; 1232 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 1313 }; 1314 1315 intc: interrupt-controller@17a00000 { 1316 compatible = "arm,gic-v3"; 1317 #address-cells = <2>; 1318 #size-cells = <2>; 1319 ranges; 1320 #interrupt-cells = <3>; 1321 interrupt-controller; 1322 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1323 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1324 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1325 1326 msi-controller@17a40000 { 1327 compatible = "arm,gic-v3-its"; 1328 msi-controller; 1329 #msi-cells = <1>; 1330 reg = <0 0x17a40000 0 0x20000>; 1331 status = "disabled"; 1332 }; 1333 }; 1334 1335 apss_shared: mailbox@17c00000 { 1336 compatible = "qcom,sc7180-apss-shared"; 1337 reg = <0 0x17c00000 0 0x10000>; 1338 #mbox-cells = <1>; 1339 }; 1340 1341 watchdog@17c10000 { 1342 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 1343 reg = <0 0x17c10000 0 0x1000>; 1344 clocks = <&sleep_clk>; 1345 }; 1346 1347 timer@17c20000{ 1348 #address-cells = <2>; 1349 #size-cells = <2>; 1350 ranges; 1351 compatible = "arm,armv7-timer-mem"; 1352 reg = <0 0x17c20000 0 0x1000>; 1353 1354 frame@17c21000 { 1355 frame-number = <0>; 1356 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1358 reg = <0 0x17c21000 0 0x1000>, 1359 <0 0x17c22000 0 0x1000>; 1360 }; 1361 1362 frame@17c23000 { 1363 frame-number = <1>; 1364 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1365 reg = <0 0x17c23000 0 0x1000>; 1366 status = "disabled"; 1367 }; 1368 1369 frame@17c25000 { 1370 frame-number = <2>; 1371 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1372 reg = <0 0x17c25000 0 0x1000>; 1373 status = "disabled"; 1374 }; 1375 1376 frame@17c27000 { 1377 frame-number = <3>; 1378 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1379 reg = <0 0x17c27000 0 0x1000>; 1380 status = "disabled"; 1381 }; 1382 1383 frame@17c29000 { 1384 frame-number = <4>; 1385 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1386 reg = <0 0x17c29000 0 0x1000>; 1387 status = "disabled"; 1388 }; 1389 1390 frame@17c2b000 { 1391 frame-number = <5>; 1392 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1393 reg = <0 0x17c2b000 0 0x1000>; 1394 status = "disabled"; 1395 }; 1396 1397 frame@17c2d000 { 1398 frame-number = <6>; 1399 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1400 reg = <0 0x17c2d000 0 0x1000>; 1401 status = "disabled"; 1402 }; 1403 }; 1404 1405 apps_rsc: rsc@18200000 { 1406 compatible = "qcom,rpmh-rsc"; 1407 reg = <0 0x18200000 0 0x10000>, 1408 <0 0x18210000 0 0x10000>, 1409 <0 0x18220000 0 0x10000>; 1410 reg-names = "drv-0", "drv-1", "drv-2"; 1411 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1414 qcom,tcs-offset = <0xd00>; 1415 qcom,drv-id = <2>; 1416 qcom,tcs-config = <ACTIVE_TCS 2>, 1417 <SLEEP_TCS 3>, 1418 <WAKE_TCS 3>, 1419 <CONTROL_TCS 1>; 1420 1421 rpmhcc: clock-controller { 1422 compatible = "qcom,sc7180-rpmh-clk"; 1423 clocks = <&xo_board>; 1424 clock-names = "xo"; 1425 #clock-cells = <1>; 1426 }; 1427 1428 rpmhpd: power-controller { 1429 compatible = "qcom,sc7180-rpmhpd"; 1430 #power-domain-cells = <1>; 1431 operating-points-v2 = <&rpmhpd_opp_table>; 1432 1433 rpmhpd_opp_table: opp-table { 1434 compatible = "operating-points-v2"; 1435 1436 rpmhpd_opp_ret: opp1 { 1437 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1438 }; 1439 1440 rpmhpd_opp_min_svs: opp2 { 1441 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1442 }; 1443 1444 rpmhpd_opp_low_svs: opp3 { 1445 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1446 }; 1447 1448 rpmhpd_opp_svs: opp4 { 1449 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1450 }; 1451 1452 rpmhpd_opp_svs_l1: opp5 { 1453 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1454 }; 1455 1456 rpmhpd_opp_svs_l2: opp6 { 1457 opp-level = <224>; 1458 }; 1459 1460 rpmhpd_opp_nom: opp7 { 1461 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1462 }; 1463 1464 rpmhpd_opp_nom_l1: opp8 { 1465 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1466 }; 1467 1468 rpmhpd_opp_nom_l2: opp9 { 1469 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1470 }; 1471 1472 rpmhpd_opp_turbo: opp10 { 1473 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1474 }; 1475 1476 rpmhpd_opp_turbo_l1: opp11 { 1477 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1478 }; 1479 }; 1480 }; 1481 }; 1482 1483 cpufreq_hw: cpufreq@18323000 { 1484 compatible = "qcom,cpufreq-hw"; 1485 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 1486 reg-names = "freq-domain0", "freq-domain1"; 1487 1488 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1489 clock-names = "xo", "alternate"; 1490 1491 #freq-domain-cells = <1>; 1492 }; 1493 }; 1494 1495 thermal-zones { 1496 cpu0-thermal { 1497 polling-delay-passive = <250>; 1498 polling-delay = <1000>; 1499 1500 thermal-sensors = <&tsens0 1>; 1501 1502 trips { 1503 cpu0_alert0: trip-point0 { 1504 temperature = <90000>; 1505 hysteresis = <2000>; 1506 type = "passive"; 1507 }; 1508 1509 cpu0_alert1: trip-point1 { 1510 temperature = <95000>; 1511 hysteresis = <2000>; 1512 type = "passive"; 1513 }; 1514 1515 cpu0_crit: cpu_crit { 1516 temperature = <110000>; 1517 hysteresis = <1000>; 1518 type = "critical"; 1519 }; 1520 }; 1521 1522 cooling-maps { 1523 map0 { 1524 trip = <&cpu0_alert0>; 1525 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1526 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1527 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1528 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1529 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1530 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1531 }; 1532 map1 { 1533 trip = <&cpu0_alert1>; 1534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1538 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1539 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1540 }; 1541 }; 1542 }; 1543 1544 cpu1-thermal { 1545 polling-delay-passive = <250>; 1546 polling-delay = <1000>; 1547 1548 thermal-sensors = <&tsens0 2>; 1549 1550 trips { 1551 cpu1_alert0: trip-point0 { 1552 temperature = <90000>; 1553 hysteresis = <2000>; 1554 type = "passive"; 1555 }; 1556 1557 cpu1_alert1: trip-point1 { 1558 temperature = <95000>; 1559 hysteresis = <2000>; 1560 type = "passive"; 1561 }; 1562 1563 cpu1_crit: cpu_crit { 1564 temperature = <110000>; 1565 hysteresis = <1000>; 1566 type = "critical"; 1567 }; 1568 }; 1569 1570 cooling-maps { 1571 map0 { 1572 trip = <&cpu1_alert0>; 1573 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1574 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1575 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1576 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1577 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1578 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1579 }; 1580 map1 { 1581 trip = <&cpu1_alert1>; 1582 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1583 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1584 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1585 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1586 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1588 }; 1589 }; 1590 }; 1591 1592 cpu2-thermal { 1593 polling-delay-passive = <250>; 1594 polling-delay = <1000>; 1595 1596 thermal-sensors = <&tsens0 3>; 1597 1598 trips { 1599 cpu2_alert0: trip-point0 { 1600 temperature = <90000>; 1601 hysteresis = <2000>; 1602 type = "passive"; 1603 }; 1604 1605 cpu2_alert1: trip-point1 { 1606 temperature = <95000>; 1607 hysteresis = <2000>; 1608 type = "passive"; 1609 }; 1610 1611 cpu2_crit: cpu_crit { 1612 temperature = <110000>; 1613 hysteresis = <1000>; 1614 type = "critical"; 1615 }; 1616 }; 1617 1618 cooling-maps { 1619 map0 { 1620 trip = <&cpu2_alert0>; 1621 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1622 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1623 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1624 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1625 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1626 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1627 }; 1628 map1 { 1629 trip = <&cpu2_alert1>; 1630 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1631 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1632 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1633 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1634 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1635 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1636 }; 1637 }; 1638 }; 1639 1640 cpu3-thermal { 1641 polling-delay-passive = <250>; 1642 polling-delay = <1000>; 1643 1644 thermal-sensors = <&tsens0 4>; 1645 1646 trips { 1647 cpu3_alert0: trip-point0 { 1648 temperature = <90000>; 1649 hysteresis = <2000>; 1650 type = "passive"; 1651 }; 1652 1653 cpu3_alert1: trip-point1 { 1654 temperature = <95000>; 1655 hysteresis = <2000>; 1656 type = "passive"; 1657 }; 1658 1659 cpu3_crit: cpu_crit { 1660 temperature = <110000>; 1661 hysteresis = <1000>; 1662 type = "critical"; 1663 }; 1664 }; 1665 1666 cooling-maps { 1667 map0 { 1668 trip = <&cpu3_alert0>; 1669 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1670 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1671 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1672 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1673 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1675 }; 1676 map1 { 1677 trip = <&cpu3_alert1>; 1678 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1679 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1680 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1681 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1682 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1684 }; 1685 }; 1686 }; 1687 1688 cpu4-thermal { 1689 polling-delay-passive = <250>; 1690 polling-delay = <1000>; 1691 1692 thermal-sensors = <&tsens0 5>; 1693 1694 trips { 1695 cpu4_alert0: trip-point0 { 1696 temperature = <90000>; 1697 hysteresis = <2000>; 1698 type = "passive"; 1699 }; 1700 1701 cpu4_alert1: trip-point1 { 1702 temperature = <95000>; 1703 hysteresis = <2000>; 1704 type = "passive"; 1705 }; 1706 1707 cpu4_crit: cpu_crit { 1708 temperature = <110000>; 1709 hysteresis = <1000>; 1710 type = "critical"; 1711 }; 1712 }; 1713 1714 cooling-maps { 1715 map0 { 1716 trip = <&cpu4_alert0>; 1717 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1718 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1719 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1720 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1721 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1722 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1723 }; 1724 map1 { 1725 trip = <&cpu4_alert1>; 1726 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1727 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1728 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1729 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1730 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1731 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1732 }; 1733 }; 1734 }; 1735 1736 cpu5-thermal { 1737 polling-delay-passive = <250>; 1738 polling-delay = <1000>; 1739 1740 thermal-sensors = <&tsens0 6>; 1741 1742 trips { 1743 cpu5_alert0: trip-point0 { 1744 temperature = <90000>; 1745 hysteresis = <2000>; 1746 type = "passive"; 1747 }; 1748 1749 cpu5_alert1: trip-point1 { 1750 temperature = <95000>; 1751 hysteresis = <2000>; 1752 type = "passive"; 1753 }; 1754 1755 cpu5_crit: cpu_crit { 1756 temperature = <110000>; 1757 hysteresis = <1000>; 1758 type = "critical"; 1759 }; 1760 }; 1761 1762 cooling-maps { 1763 map0 { 1764 trip = <&cpu5_alert0>; 1765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1769 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1771 }; 1772 map1 { 1773 trip = <&cpu5_alert1>; 1774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1775 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1776 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1777 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1778 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1779 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1780 }; 1781 }; 1782 }; 1783 1784 cpu6-thermal { 1785 polling-delay-passive = <250>; 1786 polling-delay = <1000>; 1787 1788 thermal-sensors = <&tsens0 9>; 1789 1790 trips { 1791 cpu6_alert0: trip-point0 { 1792 temperature = <90000>; 1793 hysteresis = <2000>; 1794 type = "passive"; 1795 }; 1796 1797 cpu6_alert1: trip-point1 { 1798 temperature = <95000>; 1799 hysteresis = <2000>; 1800 type = "passive"; 1801 }; 1802 1803 cpu6_crit: cpu_crit { 1804 temperature = <110000>; 1805 hysteresis = <1000>; 1806 type = "critical"; 1807 }; 1808 }; 1809 1810 cooling-maps { 1811 map0 { 1812 trip = <&cpu6_alert0>; 1813 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1815 }; 1816 map1 { 1817 trip = <&cpu6_alert1>; 1818 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1820 }; 1821 }; 1822 }; 1823 1824 cpu7-thermal { 1825 polling-delay-passive = <250>; 1826 polling-delay = <1000>; 1827 1828 thermal-sensors = <&tsens0 10>; 1829 1830 trips { 1831 cpu7_alert0: trip-point0 { 1832 temperature = <90000>; 1833 hysteresis = <2000>; 1834 type = "passive"; 1835 }; 1836 1837 cpu7_alert1: trip-point1 { 1838 temperature = <95000>; 1839 hysteresis = <2000>; 1840 type = "passive"; 1841 }; 1842 1843 cpu7_crit: cpu_crit { 1844 temperature = <110000>; 1845 hysteresis = <1000>; 1846 type = "critical"; 1847 }; 1848 }; 1849 1850 cooling-maps { 1851 map0 { 1852 trip = <&cpu7_alert0>; 1853 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1855 }; 1856 map1 { 1857 trip = <&cpu7_alert1>; 1858 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1860 }; 1861 }; 1862 }; 1863 1864 cpu8-thermal { 1865 polling-delay-passive = <250>; 1866 polling-delay = <1000>; 1867 1868 thermal-sensors = <&tsens0 11>; 1869 1870 trips { 1871 cpu8_alert0: trip-point0 { 1872 temperature = <90000>; 1873 hysteresis = <2000>; 1874 type = "passive"; 1875 }; 1876 1877 cpu8_alert1: trip-point1 { 1878 temperature = <95000>; 1879 hysteresis = <2000>; 1880 type = "passive"; 1881 }; 1882 1883 cpu8_crit: cpu_crit { 1884 temperature = <110000>; 1885 hysteresis = <1000>; 1886 type = "critical"; 1887 }; 1888 }; 1889 1890 cooling-maps { 1891 map0 { 1892 trip = <&cpu8_alert0>; 1893 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1894 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1895 }; 1896 map1 { 1897 trip = <&cpu8_alert1>; 1898 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1900 }; 1901 }; 1902 }; 1903 1904 cpu9-thermal { 1905 polling-delay-passive = <250>; 1906 polling-delay = <1000>; 1907 1908 thermal-sensors = <&tsens0 12>; 1909 1910 trips { 1911 cpu9_alert0: trip-point0 { 1912 temperature = <90000>; 1913 hysteresis = <2000>; 1914 type = "passive"; 1915 }; 1916 1917 cpu9_alert1: trip-point1 { 1918 temperature = <95000>; 1919 hysteresis = <2000>; 1920 type = "passive"; 1921 }; 1922 1923 cpu9_crit: cpu_crit { 1924 temperature = <110000>; 1925 hysteresis = <1000>; 1926 type = "critical"; 1927 }; 1928 }; 1929 1930 cooling-maps { 1931 map0 { 1932 trip = <&cpu9_alert0>; 1933 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1934 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1935 }; 1936 map1 { 1937 trip = <&cpu9_alert1>; 1938 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1940 }; 1941 }; 1942 }; 1943 1944 aoss0-thermal { 1945 polling-delay-passive = <250>; 1946 polling-delay = <1000>; 1947 1948 thermal-sensors = <&tsens0 0>; 1949 1950 trips { 1951 aoss0_alert0: trip-point0 { 1952 temperature = <90000>; 1953 hysteresis = <2000>; 1954 type = "hot"; 1955 }; 1956 }; 1957 }; 1958 1959 cpuss0-thermal { 1960 polling-delay-passive = <250>; 1961 polling-delay = <1000>; 1962 1963 thermal-sensors = <&tsens0 7>; 1964 1965 trips { 1966 cpuss0_alert0: trip-point0 { 1967 temperature = <90000>; 1968 hysteresis = <2000>; 1969 type = "hot"; 1970 }; 1971 cpuss0_crit: cluster0_crit { 1972 temperature = <110000>; 1973 hysteresis = <2000>; 1974 type = "critical"; 1975 }; 1976 }; 1977 }; 1978 1979 cpuss1-thermal { 1980 polling-delay-passive = <250>; 1981 polling-delay = <1000>; 1982 1983 thermal-sensors = <&tsens0 8>; 1984 1985 trips { 1986 cpuss1_alert0: trip-point0 { 1987 temperature = <90000>; 1988 hysteresis = <2000>; 1989 type = "hot"; 1990 }; 1991 cpuss1_crit: cluster0_crit { 1992 temperature = <110000>; 1993 hysteresis = <2000>; 1994 type = "critical"; 1995 }; 1996 }; 1997 }; 1998 1999 gpuss0-thermal { 2000 polling-delay-passive = <250>; 2001 polling-delay = <1000>; 2002 2003 thermal-sensors = <&tsens0 13>; 2004 2005 trips { 2006 gpuss0_alert0: trip-point0 { 2007 temperature = <90000>; 2008 hysteresis = <2000>; 2009 type = "hot"; 2010 }; 2011 }; 2012 }; 2013 2014 gpuss1-thermal { 2015 polling-delay-passive = <250>; 2016 polling-delay = <1000>; 2017 2018 thermal-sensors = <&tsens0 14>; 2019 2020 trips { 2021 gpuss1_alert0: trip-point0 { 2022 temperature = <90000>; 2023 hysteresis = <2000>; 2024 type = "hot"; 2025 }; 2026 }; 2027 }; 2028 2029 aoss1-thermal { 2030 polling-delay-passive = <250>; 2031 polling-delay = <1000>; 2032 2033 thermal-sensors = <&tsens1 0>; 2034 2035 trips { 2036 aoss1_alert0: trip-point0 { 2037 temperature = <90000>; 2038 hysteresis = <2000>; 2039 type = "hot"; 2040 }; 2041 }; 2042 }; 2043 2044 cwlan-thermal { 2045 polling-delay-passive = <250>; 2046 polling-delay = <1000>; 2047 2048 thermal-sensors = <&tsens1 1>; 2049 2050 trips { 2051 cwlan_alert0: trip-point0 { 2052 temperature = <90000>; 2053 hysteresis = <2000>; 2054 type = "hot"; 2055 }; 2056 }; 2057 }; 2058 2059 audio-thermal { 2060 polling-delay-passive = <250>; 2061 polling-delay = <1000>; 2062 2063 thermal-sensors = <&tsens1 2>; 2064 2065 trips { 2066 audio_alert0: trip-point0 { 2067 temperature = <90000>; 2068 hysteresis = <2000>; 2069 type = "hot"; 2070 }; 2071 }; 2072 }; 2073 2074 ddr-thermal { 2075 polling-delay-passive = <250>; 2076 polling-delay = <1000>; 2077 2078 thermal-sensors = <&tsens1 3>; 2079 2080 trips { 2081 ddr_alert0: trip-point0 { 2082 temperature = <90000>; 2083 hysteresis = <2000>; 2084 type = "hot"; 2085 }; 2086 }; 2087 }; 2088 2089 q6-hvx-thermal { 2090 polling-delay-passive = <250>; 2091 polling-delay = <1000>; 2092 2093 thermal-sensors = <&tsens1 4>; 2094 2095 trips { 2096 q6_hvx_alert0: trip-point0 { 2097 temperature = <90000>; 2098 hysteresis = <2000>; 2099 type = "hot"; 2100 }; 2101 }; 2102 }; 2103 2104 camera-thermal { 2105 polling-delay-passive = <250>; 2106 polling-delay = <1000>; 2107 2108 thermal-sensors = <&tsens1 5>; 2109 2110 trips { 2111 camera_alert0: trip-point0 { 2112 temperature = <90000>; 2113 hysteresis = <2000>; 2114 type = "hot"; 2115 }; 2116 }; 2117 }; 2118 2119 mdm-core-thermal { 2120 polling-delay-passive = <250>; 2121 polling-delay = <1000>; 2122 2123 thermal-sensors = <&tsens1 6>; 2124 2125 trips { 2126 mdm_alert0: trip-point0 { 2127 temperature = <90000>; 2128 hysteresis = <2000>; 2129 type = "hot"; 2130 }; 2131 }; 2132 }; 2133 2134 mdm-dsp-thermal { 2135 polling-delay-passive = <250>; 2136 polling-delay = <1000>; 2137 2138 thermal-sensors = <&tsens1 7>; 2139 2140 trips { 2141 mdm_dsp_alert0: trip-point0 { 2142 temperature = <90000>; 2143 hysteresis = <2000>; 2144 type = "hot"; 2145 }; 2146 }; 2147 }; 2148 2149 npu-thermal { 2150 polling-delay-passive = <250>; 2151 polling-delay = <1000>; 2152 2153 thermal-sensors = <&tsens1 8>; 2154 2155 trips { 2156 npu_alert0: trip-point0 { 2157 temperature = <90000>; 2158 hysteresis = <2000>; 2159 type = "hot"; 2160 }; 2161 }; 2162 }; 2163 2164 video-thermal { 2165 polling-delay-passive = <250>; 2166 polling-delay = <1000>; 2167 2168 thermal-sensors = <&tsens1 9>; 2169 2170 trips { 2171 video_alert0: trip-point0 { 2172 temperature = <90000>; 2173 hysteresis = <2000>; 2174 type = "hot"; 2175 }; 2176 }; 2177 }; 2178 }; 2179 2180 timer { 2181 compatible = "arm,armv8-timer"; 2182 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2183 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2184 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2185 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2186 }; 2187}; 2188