1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sc7280 fragment for devices with Chrome bootloader
4 *
5 * This file mainly tries to abstract out the memory protections put into
6 * place by the Chrome bootloader which are different than what's put into
7 * place by Qualcomm's typical bootloader. It also has a smattering of other
8 * things that will hold true for any conceivable Chrome design
9 *
10 * Copyright 2022 Google LLC.
11 */
12
13/*
14 * Reserved memory changes
15 *
16 * Delete all unused memory nodes and define the peripheral memory regions
17 * required by the setup for Chrome boards.
18 */
19
20/delete-node/ &cdsp_mem;
21/delete-node/ &gpu_zap_mem;
22/delete-node/ &gpu_zap_shader;
23/delete-node/ &hyp_mem;
24/delete-node/ &xbl_mem;
25/delete-node/ &reserved_xbl_uefi_log;
26/delete-node/ &sec_apps_mem;
27
28/ {
29	reserved-memory {
30		camera_mem: memory@8ad00000 {
31			reg = <0x0 0x8ad00000 0x0 0x500000>;
32			no-map;
33		};
34
35		venus_mem: memory@8b200000 {
36			reg = <0x0 0x8b200000 0x0 0x500000>;
37			no-map;
38		};
39	};
40};
41
42&lpass_aon {
43	status = "okay";
44};
45
46&lpass_core {
47	status = "okay";
48};
49
50&lpass_hm {
51	status = "okay";
52};
53
54&lpasscc {
55	status = "okay";
56};
57
58&pdc_reset {
59	status = "okay";
60};
61
62/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
63&pmk8350_pon {
64	status = "disabled";
65};
66
67/*
68 * Chrome designs always boot from SPI flash hooked up to the qspi.
69 *
70 * It's expected that all boards will support "dual SPI" at 37.5 MHz.
71 * If some boards need a different speed or have a package that allows
72 * Quad SPI together with WP then those boards can easily override.
73 */
74&qspi {
75	status = "okay";
76	pinctrl-names = "default", "sleep";
77	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
78	pinctrl-1 = <&qspi_sleep>;
79
80	spi_flash: flash@0 {
81		compatible = "jedec,spi-nor";
82		reg = <0>;
83
84		spi-max-frequency = <37500000>;
85		spi-tx-bus-width = <2>;
86		spi-rx-bus-width = <2>;
87	};
88};
89
90/* Currently not used */
91&remoteproc_cdsp {
92	/delete-property/ memory-region;
93};
94
95&remoteproc_wpss {
96	compatible = "qcom,sc7280-wpss-pil";
97	clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
98		 <&gcc GCC_WPSS_AHB_CLK>,
99		 <&gcc GCC_WPSS_RSCP_CLK>,
100		 <&rpmhcc RPMH_CXO_CLK>;
101	clock-names = "ahb_bdg",
102		      "ahb",
103		      "rscp",
104		      "xo";
105
106	resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
107		 <&pdc_reset PDC_WPSS_SYNC_RESET>;
108	reset-names = "restart", "pdc_sync";
109
110	qcom,halt-regs = <&tcsr_1 0x17000>;
111
112	firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
113
114	status = "okay";
115};
116
117&scm {
118	/* TF-A firmware maps memory cached so mark dma-coherent to match. */
119	dma-coherent;
120};
121
122&watchdog {
123	status = "okay";
124};
125
126&wifi {
127	status = "okay";
128
129	wifi-firmware {
130		iommus = <&apps_smmu 0x1c02 0x1>;
131	};
132};
133
134/* PINCTRL - chrome-common pinctrl */
135
136&tlmm {
137	qspi_sleep: qspi-sleep-state {
138		pins = "gpio12", "gpio13", "gpio14", "gpio15";
139
140		/*
141		 * When we're not actively transferring we want pins as GPIOs
142		 * with output disabled so that the quad SPI IP block stops
143		 * driving them. We rely on the normal pulls configured in
144		 * the active state and don't redefine them here. Also note
145		 * that we don't need the reverse (output-enable) in the
146		 * normal mode since the "output-enable" only matters for
147		 * GPIO function.
148		 */
149		function = "gpio";
150		output-disable;
151	};
152};
153