1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 756 wlan_smp2p_out: wlan-ap-to-wpss { 757 qcom,entry-name = "wlan"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 wlan_smp2p_in: wlan-wpss-to-ap { 762 qcom,entry-name = "wlan"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 }; 767 768 pmu { 769 compatible = "arm,armv8-pmuv3"; 770 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 771 }; 772 773 psci { 774 compatible = "arm,psci-1.0"; 775 method = "smc"; 776 }; 777 778 qspi_opp_table: opp-table-qspi { 779 compatible = "operating-points-v2"; 780 781 opp-75000000 { 782 opp-hz = /bits/ 64 <75000000>; 783 required-opps = <&rpmhpd_opp_low_svs>; 784 }; 785 786 opp-150000000 { 787 opp-hz = /bits/ 64 <150000000>; 788 required-opps = <&rpmhpd_opp_svs>; 789 }; 790 791 opp-200000000 { 792 opp-hz = /bits/ 64 <200000000>; 793 required-opps = <&rpmhpd_opp_svs_l1>; 794 }; 795 796 opp-300000000 { 797 opp-hz = /bits/ 64 <300000000>; 798 required-opps = <&rpmhpd_opp_nom>; 799 }; 800 }; 801 802 qup_opp_table: opp-table-qup { 803 compatible = "operating-points-v2"; 804 805 opp-75000000 { 806 opp-hz = /bits/ 64 <75000000>; 807 required-opps = <&rpmhpd_opp_low_svs>; 808 }; 809 810 opp-100000000 { 811 opp-hz = /bits/ 64 <100000000>; 812 required-opps = <&rpmhpd_opp_svs>; 813 }; 814 815 opp-128000000 { 816 opp-hz = /bits/ 64 <128000000>; 817 required-opps = <&rpmhpd_opp_nom>; 818 }; 819 }; 820 821 soc: soc@0 { 822 #address-cells = <2>; 823 #size-cells = <2>; 824 ranges = <0 0 0 0 0x10 0>; 825 dma-ranges = <0 0 0 0 0x10 0>; 826 compatible = "simple-bus"; 827 828 gcc: clock-controller@100000 { 829 compatible = "qcom,gcc-sc7280"; 830 reg = <0 0x00100000 0 0x1f0000>; 831 clocks = <&rpmhcc RPMH_CXO_CLK>, 832 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 833 <0>, <&pcie1_lane>, 834 <0>, <0>, <0>, <0>; 835 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 836 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 837 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 838 "ufs_phy_tx_symbol_0_clk", 839 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 840 #clock-cells = <1>; 841 #reset-cells = <1>; 842 #power-domain-cells = <1>; 843 power-domains = <&rpmhpd SC7280_CX>; 844 }; 845 846 ipcc: mailbox@408000 { 847 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 848 reg = <0 0x00408000 0 0x1000>; 849 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-controller; 851 #interrupt-cells = <3>; 852 #mbox-cells = <2>; 853 }; 854 855 qfprom: efuse@784000 { 856 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 857 reg = <0 0x00784000 0 0xa20>, 858 <0 0x00780000 0 0xa20>, 859 <0 0x00782000 0 0x120>, 860 <0 0x00786000 0 0x1fff>; 861 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 862 clock-names = "core"; 863 power-domains = <&rpmhpd SC7280_MX>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 867 gpu_speed_bin: gpu_speed_bin@1e9 { 868 reg = <0x1e9 0x2>; 869 bits = <5 8>; 870 }; 871 }; 872 873 sdhc_1: mmc@7c4000 { 874 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 875 pinctrl-names = "default", "sleep"; 876 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 877 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 878 status = "disabled"; 879 880 reg = <0 0x007c4000 0 0x1000>, 881 <0 0x007c5000 0 0x1000>; 882 reg-names = "hc", "cqhci"; 883 884 iommus = <&apps_smmu 0xc0 0x0>; 885 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "hc_irq", "pwr_irq"; 888 889 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 890 <&gcc GCC_SDCC1_APPS_CLK>, 891 <&rpmhcc RPMH_CXO_CLK>; 892 clock-names = "iface", "core", "xo"; 893 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 895 interconnect-names = "sdhc-ddr","cpu-sdhc"; 896 power-domains = <&rpmhpd SC7280_CX>; 897 operating-points-v2 = <&sdhc1_opp_table>; 898 899 bus-width = <8>; 900 supports-cqe; 901 902 qcom,dll-config = <0x0007642c>; 903 qcom,ddr-config = <0x80040868>; 904 905 mmc-ddr-1_8v; 906 mmc-hs200-1_8v; 907 mmc-hs400-1_8v; 908 mmc-hs400-enhanced-strobe; 909 910 resets = <&gcc GCC_SDCC1_BCR>; 911 912 sdhc1_opp_table: opp-table { 913 compatible = "operating-points-v2"; 914 915 opp-100000000 { 916 opp-hz = /bits/ 64 <100000000>; 917 required-opps = <&rpmhpd_opp_low_svs>; 918 opp-peak-kBps = <1800000 400000>; 919 opp-avg-kBps = <100000 0>; 920 }; 921 922 opp-384000000 { 923 opp-hz = /bits/ 64 <384000000>; 924 required-opps = <&rpmhpd_opp_nom>; 925 opp-peak-kBps = <5400000 1600000>; 926 opp-avg-kBps = <390000 0>; 927 }; 928 }; 929 930 }; 931 932 gpi_dma0: dma-controller@900000 { 933 #dma-cells = <3>; 934 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 935 reg = <0 0x00900000 0 0x60000>; 936 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 948 dma-channels = <12>; 949 dma-channel-mask = <0x7f>; 950 iommus = <&apps_smmu 0x0136 0x0>; 951 status = "disabled"; 952 }; 953 954 qupv3_id_0: geniqup@9c0000 { 955 compatible = "qcom,geni-se-qup"; 956 reg = <0 0x009c0000 0 0x2000>; 957 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 958 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 959 clock-names = "m-ahb", "s-ahb"; 960 #address-cells = <2>; 961 #size-cells = <2>; 962 ranges; 963 iommus = <&apps_smmu 0x123 0x0>; 964 status = "disabled"; 965 966 i2c0: i2c@980000 { 967 compatible = "qcom,geni-i2c"; 968 reg = <0 0x00980000 0 0x4000>; 969 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 970 clock-names = "se"; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_i2c0_data_clk>; 973 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 978 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 979 interconnect-names = "qup-core", "qup-config", 980 "qup-memory"; 981 power-domains = <&rpmhpd SC7280_CX>; 982 required-opps = <&rpmhpd_opp_low_svs>; 983 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 984 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 spi0: spi@980000 { 990 compatible = "qcom,geni-spi"; 991 reg = <0 0x00980000 0 0x4000>; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 clock-names = "se"; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 power-domains = <&rpmhpd SC7280_CX>; 1000 operating-points-v2 = <&qup_opp_table>; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1002 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1003 interconnect-names = "qup-core", "qup-config"; 1004 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1005 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1006 dma-names = "tx", "rx"; 1007 status = "disabled"; 1008 }; 1009 1010 uart0: serial@980000 { 1011 compatible = "qcom,geni-uart"; 1012 reg = <0 0x00980000 0 0x4000>; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1014 clock-names = "se"; 1015 pinctrl-names = "default"; 1016 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1017 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1018 power-domains = <&rpmhpd SC7280_CX>; 1019 operating-points-v2 = <&qup_opp_table>; 1020 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1021 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1022 interconnect-names = "qup-core", "qup-config"; 1023 status = "disabled"; 1024 }; 1025 1026 i2c1: i2c@984000 { 1027 compatible = "qcom,geni-i2c"; 1028 reg = <0 0x00984000 0 0x4000>; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 clock-names = "se"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&qup_i2c1_data_clk>; 1033 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1038 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1039 interconnect-names = "qup-core", "qup-config", 1040 "qup-memory"; 1041 power-domains = <&rpmhpd SC7280_CX>; 1042 required-opps = <&rpmhpd_opp_low_svs>; 1043 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1044 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 status = "disabled"; 1047 }; 1048 1049 spi1: spi@984000 { 1050 compatible = "qcom,geni-spi"; 1051 reg = <0 0x00984000 0 0x4000>; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1053 clock-names = "se"; 1054 pinctrl-names = "default"; 1055 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1056 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 power-domains = <&rpmhpd SC7280_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1062 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1065 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 status = "disabled"; 1068 }; 1069 1070 uart1: serial@984000 { 1071 compatible = "qcom,geni-uart"; 1072 reg = <0 0x00984000 0 0x4000>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1074 clock-names = "se"; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1077 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1078 power-domains = <&rpmhpd SC7280_CX>; 1079 operating-points-v2 = <&qup_opp_table>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1081 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1082 interconnect-names = "qup-core", "qup-config"; 1083 status = "disabled"; 1084 }; 1085 1086 i2c2: i2c@988000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0 0x00988000 0 0x4000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1090 clock-names = "se"; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&qup_i2c2_data_clk>; 1093 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1097 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1098 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1099 interconnect-names = "qup-core", "qup-config", 1100 "qup-memory"; 1101 power-domains = <&rpmhpd SC7280_CX>; 1102 required-opps = <&rpmhpd_opp_low_svs>; 1103 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 status = "disabled"; 1107 }; 1108 1109 spi2: spi@988000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x00988000 0 0x4000>; 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1113 clock-names = "se"; 1114 pinctrl-names = "default"; 1115 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1116 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 power-domains = <&rpmhpd SC7280_CX>; 1120 operating-points-v2 = <&qup_opp_table>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1123 interconnect-names = "qup-core", "qup-config"; 1124 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1125 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1126 dma-names = "tx", "rx"; 1127 status = "disabled"; 1128 }; 1129 1130 uart2: serial@988000 { 1131 compatible = "qcom,geni-uart"; 1132 reg = <0 0x00988000 0 0x4000>; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1134 clock-names = "se"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1137 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd SC7280_CX>; 1139 operating-points-v2 = <&qup_opp_table>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 status = "disabled"; 1144 }; 1145 1146 i2c3: i2c@98c000 { 1147 compatible = "qcom,geni-i2c"; 1148 reg = <0 0x0098c000 0 0x4000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1150 clock-names = "se"; 1151 pinctrl-names = "default"; 1152 pinctrl-0 = <&qup_i2c3_data_clk>; 1153 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1158 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1159 interconnect-names = "qup-core", "qup-config", 1160 "qup-memory"; 1161 power-domains = <&rpmhpd SC7280_CX>; 1162 required-opps = <&rpmhpd_opp_low_svs>; 1163 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 status = "disabled"; 1167 }; 1168 1169 spi3: spi@98c000 { 1170 compatible = "qcom,geni-spi"; 1171 reg = <0 0x0098c000 0 0x4000>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1173 clock-names = "se"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1176 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 power-domains = <&rpmhpd SC7280_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1183 interconnect-names = "qup-core", "qup-config"; 1184 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1185 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1186 dma-names = "tx", "rx"; 1187 status = "disabled"; 1188 }; 1189 1190 uart3: serial@98c000 { 1191 compatible = "qcom,geni-uart"; 1192 reg = <0 0x0098c000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1194 clock-names = "se"; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1197 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1198 power-domains = <&rpmhpd SC7280_CX>; 1199 operating-points-v2 = <&qup_opp_table>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 status = "disabled"; 1204 }; 1205 1206 i2c4: i2c@990000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x00990000 0 0x4000>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1210 clock-names = "se"; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c4_data_clk>; 1213 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1217 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1218 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1219 interconnect-names = "qup-core", "qup-config", 1220 "qup-memory"; 1221 power-domains = <&rpmhpd SC7280_CX>; 1222 required-opps = <&rpmhpd_opp_low_svs>; 1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1224 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1225 dma-names = "tx", "rx"; 1226 status = "disabled"; 1227 }; 1228 1229 spi4: spi@990000 { 1230 compatible = "qcom,geni-spi"; 1231 reg = <0 0x00990000 0 0x4000>; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1233 clock-names = "se"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1236 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 power-domains = <&rpmhpd SC7280_CX>; 1240 operating-points-v2 = <&qup_opp_table>; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1242 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1243 interconnect-names = "qup-core", "qup-config"; 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1245 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1246 dma-names = "tx", "rx"; 1247 status = "disabled"; 1248 }; 1249 1250 uart4: serial@990000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00990000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1254 clock-names = "se"; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1257 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1258 power-domains = <&rpmhpd SC7280_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1262 interconnect-names = "qup-core", "qup-config"; 1263 status = "disabled"; 1264 }; 1265 1266 i2c5: i2c@994000 { 1267 compatible = "qcom,geni-i2c"; 1268 reg = <0 0x00994000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_i2c5_data_clk>; 1273 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", 1280 "qup-memory"; 1281 power-domains = <&rpmhpd SC7280_CX>; 1282 required-opps = <&rpmhpd_opp_low_svs>; 1283 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1284 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1285 dma-names = "tx", "rx"; 1286 status = "disabled"; 1287 }; 1288 1289 spi5: spi@994000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00994000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1293 clock-names = "se"; 1294 pinctrl-names = "default"; 1295 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1296 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 power-domains = <&rpmhpd SC7280_CX>; 1300 operating-points-v2 = <&qup_opp_table>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1302 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1303 interconnect-names = "qup-core", "qup-config"; 1304 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1305 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1306 dma-names = "tx", "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 uart5: serial@994000 { 1311 compatible = "qcom,geni-uart"; 1312 reg = <0 0x00994000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1314 clock-names = "se"; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1317 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1318 power-domains = <&rpmhpd SC7280_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1322 interconnect-names = "qup-core", "qup-config"; 1323 status = "disabled"; 1324 }; 1325 1326 i2c6: i2c@998000 { 1327 compatible = "qcom,geni-i2c"; 1328 reg = <0 0x00998000 0 0x4000>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1330 clock-names = "se"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&qup_i2c6_data_clk>; 1333 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", 1340 "qup-memory"; 1341 power-domains = <&rpmhpd SC7280_CX>; 1342 required-opps = <&rpmhpd_opp_low_svs>; 1343 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1344 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 status = "disabled"; 1347 }; 1348 1349 spi6: spi@998000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00998000 0 0x4000>; 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1353 clock-names = "se"; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1356 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 power-domains = <&rpmhpd SC7280_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1365 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1366 dma-names = "tx", "rx"; 1367 status = "disabled"; 1368 }; 1369 1370 uart6: serial@998000 { 1371 compatible = "qcom,geni-uart"; 1372 reg = <0 0x00998000 0 0x4000>; 1373 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1374 clock-names = "se"; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd SC7280_CX>; 1379 operating-points-v2 = <&qup_opp_table>; 1380 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1381 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1382 interconnect-names = "qup-core", "qup-config"; 1383 status = "disabled"; 1384 }; 1385 1386 i2c7: i2c@99c000 { 1387 compatible = "qcom,geni-i2c"; 1388 reg = <0 0x0099c000 0 0x4000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1390 clock-names = "se"; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_i2c7_data_clk>; 1393 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1398 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", 1400 "qup-memory"; 1401 power-domains = <&rpmhpd SC7280_CX>; 1402 required-opps = <&rpmhpd_opp_low_svs>; 1403 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1404 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1405 dma-names = "tx", "rx"; 1406 status = "disabled"; 1407 }; 1408 1409 spi7: spi@99c000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0 0x0099c000 0 0x4000>; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1413 clock-names = "se"; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1416 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 power-domains = <&rpmhpd SC7280_CX>; 1420 operating-points-v2 = <&qup_opp_table>; 1421 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1422 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1423 interconnect-names = "qup-core", "qup-config"; 1424 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1426 dma-names = "tx", "rx"; 1427 status = "disabled"; 1428 }; 1429 1430 uart7: serial@99c000 { 1431 compatible = "qcom,geni-uart"; 1432 reg = <0 0x0099c000 0 0x4000>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1434 clock-names = "se"; 1435 pinctrl-names = "default"; 1436 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1438 power-domains = <&rpmhpd SC7280_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 status = "disabled"; 1444 }; 1445 }; 1446 1447 gpi_dma1: dma-controller@a00000 { 1448 #dma-cells = <3>; 1449 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1450 reg = <0 0x00a00000 0 0x60000>; 1451 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1463 dma-channels = <12>; 1464 dma-channel-mask = <0x1e>; 1465 iommus = <&apps_smmu 0x56 0x0>; 1466 status = "disabled"; 1467 }; 1468 1469 qupv3_id_1: geniqup@ac0000 { 1470 compatible = "qcom,geni-se-qup"; 1471 reg = <0 0x00ac0000 0 0x2000>; 1472 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1473 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1474 clock-names = "m-ahb", "s-ahb"; 1475 #address-cells = <2>; 1476 #size-cells = <2>; 1477 ranges; 1478 iommus = <&apps_smmu 0x43 0x0>; 1479 status = "disabled"; 1480 1481 i2c8: i2c@a80000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00a80000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_i2c8_data_clk>; 1488 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1492 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1493 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", 1495 "qup-memory"; 1496 power-domains = <&rpmhpd SC7280_CX>; 1497 required-opps = <&rpmhpd_opp_low_svs>; 1498 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1499 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1500 dma-names = "tx", "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 spi8: spi@a80000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x00a80000 0 0x4000>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1508 clock-names = "se"; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1511 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 power-domains = <&rpmhpd SC7280_CX>; 1515 operating-points-v2 = <&qup_opp_table>; 1516 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1517 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1518 interconnect-names = "qup-core", "qup-config"; 1519 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1520 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1521 dma-names = "tx", "rx"; 1522 status = "disabled"; 1523 }; 1524 1525 uart8: serial@a80000 { 1526 compatible = "qcom,geni-uart"; 1527 reg = <0 0x00a80000 0 0x4000>; 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1529 clock-names = "se"; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1532 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 operating-points-v2 = <&qup_opp_table>; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1536 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1537 interconnect-names = "qup-core", "qup-config"; 1538 status = "disabled"; 1539 }; 1540 1541 i2c9: i2c@a84000 { 1542 compatible = "qcom,geni-i2c"; 1543 reg = <0 0x00a84000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_i2c9_data_clk>; 1548 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1552 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1553 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1554 interconnect-names = "qup-core", "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SC7280_CX>; 1557 required-opps = <&rpmhpd_opp_low_svs>; 1558 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1559 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1560 dma-names = "tx", "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 spi9: spi@a84000 { 1565 compatible = "qcom,geni-spi"; 1566 reg = <0 0x00a84000 0 0x4000>; 1567 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1568 clock-names = "se"; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1571 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 power-domains = <&rpmhpd SC7280_CX>; 1575 operating-points-v2 = <&qup_opp_table>; 1576 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1577 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1578 interconnect-names = "qup-core", "qup-config"; 1579 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1580 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 status = "disabled"; 1583 }; 1584 1585 uart9: serial@a84000 { 1586 compatible = "qcom,geni-uart"; 1587 reg = <0 0x00a84000 0 0x4000>; 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1589 clock-names = "se"; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1592 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1593 power-domains = <&rpmhpd SC7280_CX>; 1594 operating-points-v2 = <&qup_opp_table>; 1595 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1596 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1597 interconnect-names = "qup-core", "qup-config"; 1598 status = "disabled"; 1599 }; 1600 1601 i2c10: i2c@a88000 { 1602 compatible = "qcom,geni-i2c"; 1603 reg = <0 0x00a88000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1605 clock-names = "se"; 1606 pinctrl-names = "default"; 1607 pinctrl-0 = <&qup_i2c10_data_clk>; 1608 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1613 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1614 interconnect-names = "qup-core", "qup-config", 1615 "qup-memory"; 1616 power-domains = <&rpmhpd SC7280_CX>; 1617 required-opps = <&rpmhpd_opp_low_svs>; 1618 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1619 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1620 dma-names = "tx", "rx"; 1621 status = "disabled"; 1622 }; 1623 1624 spi10: spi@a88000 { 1625 compatible = "qcom,geni-spi"; 1626 reg = <0 0x00a88000 0 0x4000>; 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1628 clock-names = "se"; 1629 pinctrl-names = "default"; 1630 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1631 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 power-domains = <&rpmhpd SC7280_CX>; 1635 operating-points-v2 = <&qup_opp_table>; 1636 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1638 interconnect-names = "qup-core", "qup-config"; 1639 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1640 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1641 dma-names = "tx", "rx"; 1642 status = "disabled"; 1643 }; 1644 1645 uart10: serial@a88000 { 1646 compatible = "qcom,geni-uart"; 1647 reg = <0 0x00a88000 0 0x4000>; 1648 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1649 clock-names = "se"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1652 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1653 power-domains = <&rpmhpd SC7280_CX>; 1654 operating-points-v2 = <&qup_opp_table>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1657 interconnect-names = "qup-core", "qup-config"; 1658 status = "disabled"; 1659 }; 1660 1661 i2c11: i2c@a8c000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0 0x00a8c000 0 0x4000>; 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1665 clock-names = "se"; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_i2c11_data_clk>; 1668 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", 1675 "qup-memory"; 1676 power-domains = <&rpmhpd SC7280_CX>; 1677 required-opps = <&rpmhpd_opp_low_svs>; 1678 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1679 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1680 dma-names = "tx", "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 spi11: spi@a8c000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0 0x00a8c000 0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1688 clock-names = "se"; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1691 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 power-domains = <&rpmhpd SC7280_CX>; 1695 operating-points-v2 = <&qup_opp_table>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1698 interconnect-names = "qup-core", "qup-config"; 1699 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1700 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1701 dma-names = "tx", "rx"; 1702 status = "disabled"; 1703 }; 1704 1705 uart11: serial@a8c000 { 1706 compatible = "qcom,geni-uart"; 1707 reg = <0 0x00a8c000 0 0x4000>; 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1709 clock-names = "se"; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1713 power-domains = <&rpmhpd SC7280_CX>; 1714 operating-points-v2 = <&qup_opp_table>; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1716 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1717 interconnect-names = "qup-core", "qup-config"; 1718 status = "disabled"; 1719 }; 1720 1721 i2c12: i2c@a90000 { 1722 compatible = "qcom,geni-i2c"; 1723 reg = <0 0x00a90000 0 0x4000>; 1724 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1725 clock-names = "se"; 1726 pinctrl-names = "default"; 1727 pinctrl-0 = <&qup_i2c12_data_clk>; 1728 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1733 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1734 interconnect-names = "qup-core", "qup-config", 1735 "qup-memory"; 1736 power-domains = <&rpmhpd SC7280_CX>; 1737 required-opps = <&rpmhpd_opp_low_svs>; 1738 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1739 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1740 dma-names = "tx", "rx"; 1741 status = "disabled"; 1742 }; 1743 1744 spi12: spi@a90000 { 1745 compatible = "qcom,geni-spi"; 1746 reg = <0 0x00a90000 0 0x4000>; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1748 clock-names = "se"; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1751 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 power-domains = <&rpmhpd SC7280_CX>; 1755 operating-points-v2 = <&qup_opp_table>; 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1757 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1758 interconnect-names = "qup-core", "qup-config"; 1759 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1760 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 uart12: serial@a90000 { 1766 compatible = "qcom,geni-uart"; 1767 reg = <0 0x00a90000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1773 power-domains = <&rpmhpd SC7280_CX>; 1774 operating-points-v2 = <&qup_opp_table>; 1775 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1776 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1777 interconnect-names = "qup-core", "qup-config"; 1778 status = "disabled"; 1779 }; 1780 1781 i2c13: i2c@a94000 { 1782 compatible = "qcom,geni-i2c"; 1783 reg = <0 0x00a94000 0 0x4000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1785 clock-names = "se"; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_i2c13_data_clk>; 1788 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1794 interconnect-names = "qup-core", "qup-config", 1795 "qup-memory"; 1796 power-domains = <&rpmhpd SC7280_CX>; 1797 required-opps = <&rpmhpd_opp_low_svs>; 1798 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1800 dma-names = "tx", "rx"; 1801 status = "disabled"; 1802 }; 1803 1804 spi13: spi@a94000 { 1805 compatible = "qcom,geni-spi"; 1806 reg = <0 0x00a94000 0 0x4000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1808 clock-names = "se"; 1809 pinctrl-names = "default"; 1810 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1811 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 power-domains = <&rpmhpd SC7280_CX>; 1815 operating-points-v2 = <&qup_opp_table>; 1816 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1817 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1818 interconnect-names = "qup-core", "qup-config"; 1819 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1820 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1821 dma-names = "tx", "rx"; 1822 status = "disabled"; 1823 }; 1824 1825 uart13: serial@a94000 { 1826 compatible = "qcom,geni-uart"; 1827 reg = <0 0x00a94000 0 0x4000>; 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1829 clock-names = "se"; 1830 pinctrl-names = "default"; 1831 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1832 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 status = "disabled"; 1839 }; 1840 1841 i2c14: i2c@a98000 { 1842 compatible = "qcom,geni-i2c"; 1843 reg = <0 0x00a98000 0 0x4000>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1845 clock-names = "se"; 1846 pinctrl-names = "default"; 1847 pinctrl-0 = <&qup_i2c14_data_clk>; 1848 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1853 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1854 interconnect-names = "qup-core", "qup-config", 1855 "qup-memory"; 1856 power-domains = <&rpmhpd SC7280_CX>; 1857 required-opps = <&rpmhpd_opp_low_svs>; 1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1859 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1860 dma-names = "tx", "rx"; 1861 status = "disabled"; 1862 }; 1863 1864 spi14: spi@a98000 { 1865 compatible = "qcom,geni-spi"; 1866 reg = <0 0x00a98000 0 0x4000>; 1867 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1868 clock-names = "se"; 1869 pinctrl-names = "default"; 1870 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1871 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 power-domains = <&rpmhpd SC7280_CX>; 1875 operating-points-v2 = <&qup_opp_table>; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1877 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1878 interconnect-names = "qup-core", "qup-config"; 1879 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1880 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1881 dma-names = "tx", "rx"; 1882 status = "disabled"; 1883 }; 1884 1885 uart14: serial@a98000 { 1886 compatible = "qcom,geni-uart"; 1887 reg = <0 0x00a98000 0 0x4000>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1889 clock-names = "se"; 1890 pinctrl-names = "default"; 1891 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1892 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1893 power-domains = <&rpmhpd SC7280_CX>; 1894 operating-points-v2 = <&qup_opp_table>; 1895 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1896 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1897 interconnect-names = "qup-core", "qup-config"; 1898 status = "disabled"; 1899 }; 1900 1901 i2c15: i2c@a9c000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0 0x00a9c000 0 0x4000>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1905 clock-names = "se"; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_i2c15_data_clk>; 1908 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1912 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1913 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1914 interconnect-names = "qup-core", "qup-config", 1915 "qup-memory"; 1916 power-domains = <&rpmhpd SC7280_CX>; 1917 required-opps = <&rpmhpd_opp_low_svs>; 1918 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1919 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1920 dma-names = "tx", "rx"; 1921 status = "disabled"; 1922 }; 1923 1924 spi15: spi@a9c000 { 1925 compatible = "qcom,geni-spi"; 1926 reg = <0 0x00a9c000 0 0x4000>; 1927 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1928 clock-names = "se"; 1929 pinctrl-names = "default"; 1930 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1931 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 power-domains = <&rpmhpd SC7280_CX>; 1935 operating-points-v2 = <&qup_opp_table>; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1938 interconnect-names = "qup-core", "qup-config"; 1939 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1940 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1941 dma-names = "tx", "rx"; 1942 status = "disabled"; 1943 }; 1944 1945 uart15: serial@a9c000 { 1946 compatible = "qcom,geni-uart"; 1947 reg = <0 0x00a9c000 0 0x4000>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1949 clock-names = "se"; 1950 pinctrl-names = "default"; 1951 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1952 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1953 power-domains = <&rpmhpd SC7280_CX>; 1954 operating-points-v2 = <&qup_opp_table>; 1955 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1956 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1957 interconnect-names = "qup-core", "qup-config"; 1958 status = "disabled"; 1959 }; 1960 }; 1961 1962 cnoc2: interconnect@1500000 { 1963 reg = <0 0x01500000 0 0x1000>; 1964 compatible = "qcom,sc7280-cnoc2"; 1965 #interconnect-cells = <2>; 1966 qcom,bcm-voters = <&apps_bcm_voter>; 1967 }; 1968 1969 cnoc3: interconnect@1502000 { 1970 reg = <0 0x01502000 0 0x1000>; 1971 compatible = "qcom,sc7280-cnoc3"; 1972 #interconnect-cells = <2>; 1973 qcom,bcm-voters = <&apps_bcm_voter>; 1974 }; 1975 1976 mc_virt: interconnect@1580000 { 1977 reg = <0 0x01580000 0 0x4>; 1978 compatible = "qcom,sc7280-mc-virt"; 1979 #interconnect-cells = <2>; 1980 qcom,bcm-voters = <&apps_bcm_voter>; 1981 }; 1982 1983 system_noc: interconnect@1680000 { 1984 reg = <0 0x01680000 0 0x15480>; 1985 compatible = "qcom,sc7280-system-noc"; 1986 #interconnect-cells = <2>; 1987 qcom,bcm-voters = <&apps_bcm_voter>; 1988 }; 1989 1990 aggre1_noc: interconnect@16e0000 { 1991 compatible = "qcom,sc7280-aggre1-noc"; 1992 reg = <0 0x016e0000 0 0x1c080>; 1993 #interconnect-cells = <2>; 1994 qcom,bcm-voters = <&apps_bcm_voter>; 1995 }; 1996 1997 aggre2_noc: interconnect@1700000 { 1998 reg = <0 0x01700000 0 0x2b080>; 1999 compatible = "qcom,sc7280-aggre2-noc"; 2000 #interconnect-cells = <2>; 2001 qcom,bcm-voters = <&apps_bcm_voter>; 2002 }; 2003 2004 mmss_noc: interconnect@1740000 { 2005 reg = <0 0x01740000 0 0x1e080>; 2006 compatible = "qcom,sc7280-mmss-noc"; 2007 #interconnect-cells = <2>; 2008 qcom,bcm-voters = <&apps_bcm_voter>; 2009 }; 2010 2011 wifi: wifi@17a10040 { 2012 compatible = "qcom,wcn6750-wifi"; 2013 reg = <0 0x17a10040 0 0x0>; 2014 iommus = <&apps_smmu 0x1c00 0x1>; 2015 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2016 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2017 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2018 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2019 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2020 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2021 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2022 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2023 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2024 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2025 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2026 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2027 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2028 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2029 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2030 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2031 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2032 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2033 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2034 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2035 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2036 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2037 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2038 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2039 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2040 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2041 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2042 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2043 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2044 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2045 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2046 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2047 qcom,rproc = <&remoteproc_wpss>; 2048 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2049 status = "disabled"; 2050 qcom,smem-states = <&wlan_smp2p_out 0>; 2051 qcom,smem-state-names = "wlan-smp2p-out"; 2052 }; 2053 2054 pcie1: pci@1c08000 { 2055 compatible = "qcom,pcie-sc7280"; 2056 reg = <0 0x01c08000 0 0x3000>, 2057 <0 0x40000000 0 0xf1d>, 2058 <0 0x40000f20 0 0xa8>, 2059 <0 0x40001000 0 0x1000>, 2060 <0 0x40100000 0 0x100000>; 2061 2062 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2063 device_type = "pci"; 2064 linux,pci-domain = <1>; 2065 bus-range = <0x00 0xff>; 2066 num-lanes = <2>; 2067 2068 #address-cells = <3>; 2069 #size-cells = <2>; 2070 2071 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2072 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2073 2074 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "msi"; 2076 #interrupt-cells = <1>; 2077 interrupt-map-mask = <0 0 0 0x7>; 2078 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2079 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2080 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2081 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2082 2083 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2084 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2085 <&pcie1_lane>, 2086 <&rpmhcc RPMH_CXO_CLK>, 2087 <&gcc GCC_PCIE_1_AUX_CLK>, 2088 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2089 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2090 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2091 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2092 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2093 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2094 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2095 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2096 2097 clock-names = "pipe", 2098 "pipe_mux", 2099 "phy_pipe", 2100 "ref", 2101 "aux", 2102 "cfg", 2103 "bus_master", 2104 "bus_slave", 2105 "slave_q2a", 2106 "tbu", 2107 "ddrss_sf_tbu", 2108 "aggre0", 2109 "aggre1"; 2110 2111 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2112 assigned-clock-rates = <19200000>; 2113 2114 resets = <&gcc GCC_PCIE_1_BCR>; 2115 reset-names = "pci"; 2116 2117 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2118 2119 phys = <&pcie1_lane>; 2120 phy-names = "pciephy"; 2121 2122 pinctrl-names = "default"; 2123 pinctrl-0 = <&pcie1_clkreq_n>; 2124 2125 iommus = <&apps_smmu 0x1c80 0x1>; 2126 2127 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2128 <0x100 &apps_smmu 0x1c81 0x1>; 2129 2130 status = "disabled"; 2131 }; 2132 2133 pcie1_phy: phy@1c0e000 { 2134 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2135 reg = <0 0x01c0e000 0 0x1c0>; 2136 #address-cells = <2>; 2137 #size-cells = <2>; 2138 ranges; 2139 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2140 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2141 <&gcc GCC_PCIE_CLKREF_EN>, 2142 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2143 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2144 2145 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2146 reset-names = "phy"; 2147 2148 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2149 assigned-clock-rates = <100000000>; 2150 2151 status = "disabled"; 2152 2153 pcie1_lane: phy@1c0e200 { 2154 reg = <0 0x01c0e200 0 0x170>, 2155 <0 0x01c0e400 0 0x200>, 2156 <0 0x01c0ea00 0 0x1f0>, 2157 <0 0x01c0e600 0 0x170>, 2158 <0 0x01c0e800 0 0x200>, 2159 <0 0x01c0ee00 0 0xf4>; 2160 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2161 clock-names = "pipe0"; 2162 2163 #phy-cells = <0>; 2164 #clock-cells = <0>; 2165 clock-output-names = "pcie_1_pipe_clk"; 2166 }; 2167 }; 2168 2169 ipa: ipa@1e40000 { 2170 compatible = "qcom,sc7280-ipa"; 2171 2172 iommus = <&apps_smmu 0x480 0x0>, 2173 <&apps_smmu 0x482 0x0>; 2174 reg = <0 0x1e40000 0 0x8000>, 2175 <0 0x1e50000 0 0x4ad0>, 2176 <0 0x1e04000 0 0x23000>; 2177 reg-names = "ipa-reg", 2178 "ipa-shared", 2179 "gsi"; 2180 2181 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2182 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2183 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2184 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2185 interrupt-names = "ipa", 2186 "gsi", 2187 "ipa-clock-query", 2188 "ipa-setup-ready"; 2189 2190 clocks = <&rpmhcc RPMH_IPA_CLK>; 2191 clock-names = "core"; 2192 2193 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2195 interconnect-names = "memory", 2196 "config"; 2197 2198 qcom,qmp = <&aoss_qmp>; 2199 2200 qcom,smem-states = <&ipa_smp2p_out 0>, 2201 <&ipa_smp2p_out 1>; 2202 qcom,smem-state-names = "ipa-clock-enabled-valid", 2203 "ipa-clock-enabled"; 2204 2205 status = "disabled"; 2206 }; 2207 2208 tcsr_mutex: hwlock@1f40000 { 2209 compatible = "qcom,tcsr-mutex"; 2210 reg = <0 0x01f40000 0 0x20000>; 2211 #hwlock-cells = <1>; 2212 }; 2213 2214 tcsr_1: syscon@1f60000 { 2215 compatible = "qcom,sc7280-tcsr", "syscon"; 2216 reg = <0 0x01f60000 0 0x20000>; 2217 }; 2218 2219 tcsr_2: syscon@1fc0000 { 2220 compatible = "qcom,sc7280-tcsr", "syscon"; 2221 reg = <0 0x01fc0000 0 0x30000>; 2222 }; 2223 2224 lpasscc: lpasscc@3000000 { 2225 compatible = "qcom,sc7280-lpasscc"; 2226 reg = <0 0x03000000 0 0x40>, 2227 <0 0x03c04000 0 0x4>; 2228 reg-names = "qdsp6ss", "top_cc"; 2229 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2230 clock-names = "iface"; 2231 #clock-cells = <1>; 2232 }; 2233 2234 lpass_rx_macro: codec@3200000 { 2235 compatible = "qcom,sc7280-lpass-rx-macro"; 2236 reg = <0 0x03200000 0 0x1000>; 2237 2238 pinctrl-names = "default"; 2239 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2240 2241 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2242 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2243 <&lpass_va_macro>; 2244 clock-names = "mclk", "npl", "fsgen"; 2245 2246 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2247 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2248 power-domain-names = "macro", "dcodec"; 2249 2250 #clock-cells = <0>; 2251 #sound-dai-cells = <1>; 2252 2253 status = "disabled"; 2254 }; 2255 2256 swr0: soundwire@3210000 { 2257 compatible = "qcom,soundwire-v1.6.0"; 2258 reg = <0 0x03210000 0 0x2000>; 2259 2260 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2261 clocks = <&lpass_rx_macro>; 2262 clock-names = "iface"; 2263 2264 qcom,din-ports = <0>; 2265 qcom,dout-ports = <5>; 2266 2267 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2268 reset-names = "swr_audio_cgcr"; 2269 2270 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2271 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2272 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2273 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2274 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2275 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2276 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2277 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2278 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2279 2280 #sound-dai-cells = <1>; 2281 #address-cells = <2>; 2282 #size-cells = <0>; 2283 2284 status = "disabled"; 2285 }; 2286 2287 lpass_tx_macro: codec@3220000 { 2288 compatible = "qcom,sc7280-lpass-tx-macro"; 2289 reg = <0 0x03220000 0 0x1000>; 2290 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2293 2294 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2295 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2296 <&lpass_va_macro>; 2297 clock-names = "mclk", "npl", "fsgen"; 2298 2299 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2300 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2301 power-domain-names = "macro", "dcodec"; 2302 2303 #clock-cells = <0>; 2304 #sound-dai-cells = <1>; 2305 2306 status = "disabled"; 2307 }; 2308 2309 swr1: soundwire@3230000 { 2310 compatible = "qcom,soundwire-v1.6.0"; 2311 reg = <0 0x03230000 0 0x2000>; 2312 2313 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2314 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2315 clocks = <&lpass_tx_macro>; 2316 clock-names = "iface"; 2317 2318 qcom,din-ports = <3>; 2319 qcom,dout-ports = <0>; 2320 2321 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2322 reset-names = "swr_audio_cgcr"; 2323 2324 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2325 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2326 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2327 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2328 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2329 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2330 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2331 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2332 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2333 2334 #sound-dai-cells = <1>; 2335 #address-cells = <2>; 2336 #size-cells = <0>; 2337 2338 status = "disabled"; 2339 }; 2340 2341 lpass_audiocc: clock-controller@3300000 { 2342 compatible = "qcom,sc7280-lpassaudiocc"; 2343 reg = <0 0x03300000 0 0x30000>, 2344 <0 0x032a9000 0 0x1000>; 2345 clocks = <&rpmhcc RPMH_CXO_CLK>, 2346 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2347 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2348 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2349 #clock-cells = <1>; 2350 #power-domain-cells = <1>; 2351 #reset-cells = <1>; 2352 }; 2353 2354 lpass_va_macro: codec@3370000 { 2355 compatible = "qcom,sc7280-lpass-va-macro"; 2356 reg = <0 0x03370000 0 0x1000>; 2357 2358 pinctrl-names = "default"; 2359 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2360 2361 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2362 clock-names = "mclk"; 2363 2364 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2365 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2366 power-domain-names = "macro", "dcodec"; 2367 2368 #clock-cells = <0>; 2369 #sound-dai-cells = <1>; 2370 2371 status = "disabled"; 2372 }; 2373 2374 lpass_aon: clock-controller@3380000 { 2375 compatible = "qcom,sc7280-lpassaoncc"; 2376 reg = <0 0x03380000 0 0x30000>; 2377 clocks = <&rpmhcc RPMH_CXO_CLK>, 2378 <&rpmhcc RPMH_CXO_CLK_A>, 2379 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2380 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2381 #clock-cells = <1>; 2382 #power-domain-cells = <1>; 2383 }; 2384 2385 lpass_core: clock-controller@3900000 { 2386 compatible = "qcom,sc7280-lpasscorecc"; 2387 reg = <0 0x03900000 0 0x50000>; 2388 clocks = <&rpmhcc RPMH_CXO_CLK>; 2389 clock-names = "bi_tcxo"; 2390 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2391 #clock-cells = <1>; 2392 #power-domain-cells = <1>; 2393 }; 2394 2395 lpass_cpu: audio@3987000 { 2396 compatible = "qcom,sc7280-lpass-cpu"; 2397 2398 reg = <0 0x03987000 0 0x68000>, 2399 <0 0x03b00000 0 0x29000>, 2400 <0 0x03260000 0 0xc000>, 2401 <0 0x03280000 0 0x29000>, 2402 <0 0x03340000 0 0x29000>, 2403 <0 0x0336c000 0 0x3000>; 2404 reg-names = "lpass-hdmiif", 2405 "lpass-lpaif", 2406 "lpass-rxtx-cdc-dma-lpm", 2407 "lpass-rxtx-lpaif", 2408 "lpass-va-lpaif", 2409 "lpass-va-cdc-dma-lpm"; 2410 2411 iommus = <&apps_smmu 0x1820 0>, 2412 <&apps_smmu 0x1821 0>, 2413 <&apps_smmu 0x1832 0>; 2414 2415 power-domains = <&rpmhpd SC7280_LCX>; 2416 power-domain-names = "lcx"; 2417 required-opps = <&rpmhpd_opp_nom>; 2418 2419 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2420 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2421 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2422 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2423 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2424 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2425 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2426 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2427 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2428 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2429 clock-names = "aon_cc_audio_hm_h", 2430 "audio_cc_ext_mclk0", 2431 "core_cc_sysnoc_mport_core", 2432 "core_cc_ext_if0_ibit", 2433 "core_cc_ext_if1_ibit", 2434 "audio_cc_codec_mem", 2435 "audio_cc_codec_mem0", 2436 "audio_cc_codec_mem1", 2437 "audio_cc_codec_mem2", 2438 "aon_cc_va_mem0"; 2439 2440 #sound-dai-cells = <1>; 2441 #address-cells = <1>; 2442 #size-cells = <0>; 2443 2444 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2448 interrupt-names = "lpass-irq-lpaif", 2449 "lpass-irq-hdmi", 2450 "lpass-irq-vaif", 2451 "lpass-irq-rxtxif"; 2452 2453 status = "disabled"; 2454 }; 2455 2456 lpass_hm: clock-controller@3c00000 { 2457 compatible = "qcom,sc7280-lpasshm"; 2458 reg = <0 0x3c00000 0 0x28>; 2459 clocks = <&rpmhcc RPMH_CXO_CLK>; 2460 clock-names = "bi_tcxo"; 2461 #clock-cells = <1>; 2462 #power-domain-cells = <1>; 2463 }; 2464 2465 lpass_ag_noc: interconnect@3c40000 { 2466 reg = <0 0x03c40000 0 0xf080>; 2467 compatible = "qcom,sc7280-lpass-ag-noc"; 2468 #interconnect-cells = <2>; 2469 qcom,bcm-voters = <&apps_bcm_voter>; 2470 }; 2471 2472 lpass_tlmm: pinctrl@33c0000 { 2473 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2474 reg = <0 0x033c0000 0x0 0x20000>, 2475 <0 0x03550000 0x0 0x10000>; 2476 qcom,adsp-bypass-mode; 2477 gpio-controller; 2478 #gpio-cells = <2>; 2479 gpio-ranges = <&lpass_tlmm 0 0 15>; 2480 2481 lpass_dmic01_clk: dmic01-clk-state { 2482 pins = "gpio6"; 2483 function = "dmic1_clk"; 2484 }; 2485 2486 lpass_dmic01_data: dmic01-data-state { 2487 pins = "gpio7"; 2488 function = "dmic1_data"; 2489 }; 2490 2491 lpass_dmic23_clk: dmic23-clk-state { 2492 pins = "gpio8"; 2493 function = "dmic2_clk"; 2494 }; 2495 2496 lpass_dmic23_data: dmic23-data-state { 2497 pins = "gpio9"; 2498 function = "dmic2_data"; 2499 }; 2500 2501 lpass_rx_swr_clk: rx-swr-clk-state { 2502 pins = "gpio3"; 2503 function = "swr_rx_clk"; 2504 }; 2505 2506 lpass_rx_swr_data: rx-swr-data-state { 2507 pins = "gpio4", "gpio5"; 2508 function = "swr_rx_data"; 2509 }; 2510 2511 lpass_tx_swr_clk: tx-swr-clk-state { 2512 pins = "gpio0"; 2513 function = "swr_tx_clk"; 2514 }; 2515 2516 lpass_tx_swr_data: tx-swr-data-state { 2517 pins = "gpio1", "gpio2", "gpio14"; 2518 function = "swr_tx_data"; 2519 }; 2520 }; 2521 2522 gpu: gpu@3d00000 { 2523 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2524 reg = <0 0x03d00000 0 0x40000>, 2525 <0 0x03d9e000 0 0x1000>, 2526 <0 0x03d61000 0 0x800>; 2527 reg-names = "kgsl_3d0_reg_memory", 2528 "cx_mem", 2529 "cx_dbgc"; 2530 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2531 iommus = <&adreno_smmu 0 0x401>; 2532 operating-points-v2 = <&gpu_opp_table>; 2533 qcom,gmu = <&gmu>; 2534 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2535 interconnect-names = "gfx-mem"; 2536 #cooling-cells = <2>; 2537 2538 nvmem-cells = <&gpu_speed_bin>; 2539 nvmem-cell-names = "speed_bin"; 2540 2541 gpu_opp_table: opp-table { 2542 compatible = "operating-points-v2"; 2543 2544 opp-315000000 { 2545 opp-hz = /bits/ 64 <315000000>; 2546 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2547 opp-peak-kBps = <1804000>; 2548 opp-supported-hw = <0x03>; 2549 }; 2550 2551 opp-450000000 { 2552 opp-hz = /bits/ 64 <450000000>; 2553 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2554 opp-peak-kBps = <4068000>; 2555 opp-supported-hw = <0x03>; 2556 }; 2557 2558 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2559 opp-550000000-0 { 2560 opp-hz = /bits/ 64 <550000000>; 2561 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2562 opp-peak-kBps = <8368000>; 2563 opp-supported-hw = <0x01>; 2564 }; 2565 2566 opp-550000000-1 { 2567 opp-hz = /bits/ 64 <550000000>; 2568 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2569 opp-peak-kBps = <6832000>; 2570 opp-supported-hw = <0x02>; 2571 }; 2572 2573 opp-608000000 { 2574 opp-hz = /bits/ 64 <608000000>; 2575 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2576 opp-peak-kBps = <8368000>; 2577 opp-supported-hw = <0x02>; 2578 }; 2579 2580 opp-700000000 { 2581 opp-hz = /bits/ 64 <700000000>; 2582 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2583 opp-peak-kBps = <8532000>; 2584 opp-supported-hw = <0x02>; 2585 }; 2586 2587 opp-812000000 { 2588 opp-hz = /bits/ 64 <812000000>; 2589 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2590 opp-peak-kBps = <8532000>; 2591 opp-supported-hw = <0x02>; 2592 }; 2593 2594 opp-840000000 { 2595 opp-hz = /bits/ 64 <840000000>; 2596 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2597 opp-peak-kBps = <8532000>; 2598 opp-supported-hw = <0x02>; 2599 }; 2600 2601 opp-900000000 { 2602 opp-hz = /bits/ 64 <900000000>; 2603 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2604 opp-peak-kBps = <8532000>; 2605 opp-supported-hw = <0x02>; 2606 }; 2607 }; 2608 }; 2609 2610 gmu: gmu@3d6a000 { 2611 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2612 reg = <0 0x03d6a000 0 0x34000>, 2613 <0 0x3de0000 0 0x10000>, 2614 <0 0x0b290000 0 0x10000>; 2615 reg-names = "gmu", "rscc", "gmu_pdc"; 2616 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2618 interrupt-names = "hfi", "gmu"; 2619 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2620 <&gpucc GPU_CC_CXO_CLK>, 2621 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2622 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2623 <&gpucc GPU_CC_AHB_CLK>, 2624 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2625 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2626 clock-names = "gmu", 2627 "cxo", 2628 "axi", 2629 "memnoc", 2630 "ahb", 2631 "hub", 2632 "smmu_vote"; 2633 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2634 <&gpucc GPU_CC_GX_GDSC>; 2635 power-domain-names = "cx", 2636 "gx"; 2637 iommus = <&adreno_smmu 5 0x400>; 2638 operating-points-v2 = <&gmu_opp_table>; 2639 2640 gmu_opp_table: opp-table { 2641 compatible = "operating-points-v2"; 2642 2643 opp-200000000 { 2644 opp-hz = /bits/ 64 <200000000>; 2645 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2646 }; 2647 }; 2648 }; 2649 2650 gpucc: clock-controller@3d90000 { 2651 compatible = "qcom,sc7280-gpucc"; 2652 reg = <0 0x03d90000 0 0x9000>; 2653 clocks = <&rpmhcc RPMH_CXO_CLK>, 2654 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2655 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2656 clock-names = "bi_tcxo", 2657 "gcc_gpu_gpll0_clk_src", 2658 "gcc_gpu_gpll0_div_clk_src"; 2659 #clock-cells = <1>; 2660 #reset-cells = <1>; 2661 #power-domain-cells = <1>; 2662 }; 2663 2664 adreno_smmu: iommu@3da0000 { 2665 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2666 reg = <0 0x03da0000 0 0x20000>; 2667 #iommu-cells = <2>; 2668 #global-interrupts = <2>; 2669 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2678 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2679 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2681 2682 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2683 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2684 <&gpucc GPU_CC_AHB_CLK>, 2685 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2686 <&gpucc GPU_CC_CX_GMU_CLK>, 2687 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2688 <&gpucc GPU_CC_HUB_AON_CLK>; 2689 clock-names = "gcc_gpu_memnoc_gfx_clk", 2690 "gcc_gpu_snoc_dvm_gfx_clk", 2691 "gpu_cc_ahb_clk", 2692 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2693 "gpu_cc_cx_gmu_clk", 2694 "gpu_cc_hub_cx_int_clk", 2695 "gpu_cc_hub_aon_clk"; 2696 2697 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2698 }; 2699 2700 remoteproc_mpss: remoteproc@4080000 { 2701 compatible = "qcom,sc7280-mpss-pas"; 2702 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2703 reg-names = "qdsp6", "rmb"; 2704 2705 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2706 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2707 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2708 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2709 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2710 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2711 interrupt-names = "wdog", "fatal", "ready", "handover", 2712 "stop-ack", "shutdown-ack"; 2713 2714 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2715 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2716 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2717 <&rpmhcc RPMH_PKA_CLK>, 2718 <&rpmhcc RPMH_CXO_CLK>; 2719 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2720 2721 power-domains = <&rpmhpd SC7280_CX>, 2722 <&rpmhpd SC7280_MSS>; 2723 power-domain-names = "cx", "mss"; 2724 2725 memory-region = <&mpss_mem>; 2726 2727 qcom,qmp = <&aoss_qmp>; 2728 2729 qcom,smem-states = <&modem_smp2p_out 0>; 2730 qcom,smem-state-names = "stop"; 2731 2732 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2733 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2734 reset-names = "mss_restart", "pdc_reset"; 2735 2736 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2737 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2738 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2739 2740 status = "disabled"; 2741 2742 glink-edge { 2743 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2744 IPCC_MPROC_SIGNAL_GLINK_QMP 2745 IRQ_TYPE_EDGE_RISING>; 2746 mboxes = <&ipcc IPCC_CLIENT_MPSS 2747 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2748 label = "modem"; 2749 qcom,remote-pid = <1>; 2750 }; 2751 }; 2752 2753 stm@6002000 { 2754 compatible = "arm,coresight-stm", "arm,primecell"; 2755 reg = <0 0x06002000 0 0x1000>, 2756 <0 0x16280000 0 0x180000>; 2757 reg-names = "stm-base", "stm-stimulus-base"; 2758 2759 clocks = <&aoss_qmp>; 2760 clock-names = "apb_pclk"; 2761 2762 out-ports { 2763 port { 2764 stm_out: endpoint { 2765 remote-endpoint = <&funnel0_in7>; 2766 }; 2767 }; 2768 }; 2769 }; 2770 2771 funnel@6041000 { 2772 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2773 reg = <0 0x06041000 0 0x1000>; 2774 2775 clocks = <&aoss_qmp>; 2776 clock-names = "apb_pclk"; 2777 2778 out-ports { 2779 port { 2780 funnel0_out: endpoint { 2781 remote-endpoint = <&merge_funnel_in0>; 2782 }; 2783 }; 2784 }; 2785 2786 in-ports { 2787 #address-cells = <1>; 2788 #size-cells = <0>; 2789 2790 port@7 { 2791 reg = <7>; 2792 funnel0_in7: endpoint { 2793 remote-endpoint = <&stm_out>; 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 funnel@6042000 { 2800 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2801 reg = <0 0x06042000 0 0x1000>; 2802 2803 clocks = <&aoss_qmp>; 2804 clock-names = "apb_pclk"; 2805 2806 out-ports { 2807 port { 2808 funnel1_out: endpoint { 2809 remote-endpoint = <&merge_funnel_in1>; 2810 }; 2811 }; 2812 }; 2813 2814 in-ports { 2815 #address-cells = <1>; 2816 #size-cells = <0>; 2817 2818 port@4 { 2819 reg = <4>; 2820 funnel1_in4: endpoint { 2821 remote-endpoint = <&apss_merge_funnel_out>; 2822 }; 2823 }; 2824 }; 2825 }; 2826 2827 funnel@6045000 { 2828 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2829 reg = <0 0x06045000 0 0x1000>; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 out-ports { 2835 port { 2836 merge_funnel_out: endpoint { 2837 remote-endpoint = <&swao_funnel_in>; 2838 }; 2839 }; 2840 }; 2841 2842 in-ports { 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 2846 port@0 { 2847 reg = <0>; 2848 merge_funnel_in0: endpoint { 2849 remote-endpoint = <&funnel0_out>; 2850 }; 2851 }; 2852 2853 port@1 { 2854 reg = <1>; 2855 merge_funnel_in1: endpoint { 2856 remote-endpoint = <&funnel1_out>; 2857 }; 2858 }; 2859 }; 2860 }; 2861 2862 replicator@6046000 { 2863 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2864 reg = <0 0x06046000 0 0x1000>; 2865 2866 clocks = <&aoss_qmp>; 2867 clock-names = "apb_pclk"; 2868 2869 out-ports { 2870 port { 2871 replicator_out: endpoint { 2872 remote-endpoint = <&etr_in>; 2873 }; 2874 }; 2875 }; 2876 2877 in-ports { 2878 port { 2879 replicator_in: endpoint { 2880 remote-endpoint = <&swao_replicator_out>; 2881 }; 2882 }; 2883 }; 2884 }; 2885 2886 etr@6048000 { 2887 compatible = "arm,coresight-tmc", "arm,primecell"; 2888 reg = <0 0x06048000 0 0x1000>; 2889 iommus = <&apps_smmu 0x04c0 0>; 2890 2891 clocks = <&aoss_qmp>; 2892 clock-names = "apb_pclk"; 2893 arm,scatter-gather; 2894 2895 in-ports { 2896 port { 2897 etr_in: endpoint { 2898 remote-endpoint = <&replicator_out>; 2899 }; 2900 }; 2901 }; 2902 }; 2903 2904 funnel@6b04000 { 2905 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2906 reg = <0 0x06b04000 0 0x1000>; 2907 2908 clocks = <&aoss_qmp>; 2909 clock-names = "apb_pclk"; 2910 2911 out-ports { 2912 port { 2913 swao_funnel_out: endpoint { 2914 remote-endpoint = <&etf_in>; 2915 }; 2916 }; 2917 }; 2918 2919 in-ports { 2920 #address-cells = <1>; 2921 #size-cells = <0>; 2922 2923 port@7 { 2924 reg = <7>; 2925 swao_funnel_in: endpoint { 2926 remote-endpoint = <&merge_funnel_out>; 2927 }; 2928 }; 2929 }; 2930 }; 2931 2932 etf@6b05000 { 2933 compatible = "arm,coresight-tmc", "arm,primecell"; 2934 reg = <0 0x06b05000 0 0x1000>; 2935 2936 clocks = <&aoss_qmp>; 2937 clock-names = "apb_pclk"; 2938 2939 out-ports { 2940 port { 2941 etf_out: endpoint { 2942 remote-endpoint = <&swao_replicator_in>; 2943 }; 2944 }; 2945 }; 2946 2947 in-ports { 2948 port { 2949 etf_in: endpoint { 2950 remote-endpoint = <&swao_funnel_out>; 2951 }; 2952 }; 2953 }; 2954 }; 2955 2956 replicator@6b06000 { 2957 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2958 reg = <0 0x06b06000 0 0x1000>; 2959 2960 clocks = <&aoss_qmp>; 2961 clock-names = "apb_pclk"; 2962 qcom,replicator-loses-context; 2963 2964 out-ports { 2965 port { 2966 swao_replicator_out: endpoint { 2967 remote-endpoint = <&replicator_in>; 2968 }; 2969 }; 2970 }; 2971 2972 in-ports { 2973 port { 2974 swao_replicator_in: endpoint { 2975 remote-endpoint = <&etf_out>; 2976 }; 2977 }; 2978 }; 2979 }; 2980 2981 etm@7040000 { 2982 compatible = "arm,coresight-etm4x", "arm,primecell"; 2983 reg = <0 0x07040000 0 0x1000>; 2984 2985 cpu = <&CPU0>; 2986 2987 clocks = <&aoss_qmp>; 2988 clock-names = "apb_pclk"; 2989 arm,coresight-loses-context-with-cpu; 2990 qcom,skip-power-up; 2991 2992 out-ports { 2993 port { 2994 etm0_out: endpoint { 2995 remote-endpoint = <&apss_funnel_in0>; 2996 }; 2997 }; 2998 }; 2999 }; 3000 3001 etm@7140000 { 3002 compatible = "arm,coresight-etm4x", "arm,primecell"; 3003 reg = <0 0x07140000 0 0x1000>; 3004 3005 cpu = <&CPU1>; 3006 3007 clocks = <&aoss_qmp>; 3008 clock-names = "apb_pclk"; 3009 arm,coresight-loses-context-with-cpu; 3010 qcom,skip-power-up; 3011 3012 out-ports { 3013 port { 3014 etm1_out: endpoint { 3015 remote-endpoint = <&apss_funnel_in1>; 3016 }; 3017 }; 3018 }; 3019 }; 3020 3021 etm@7240000 { 3022 compatible = "arm,coresight-etm4x", "arm,primecell"; 3023 reg = <0 0x07240000 0 0x1000>; 3024 3025 cpu = <&CPU2>; 3026 3027 clocks = <&aoss_qmp>; 3028 clock-names = "apb_pclk"; 3029 arm,coresight-loses-context-with-cpu; 3030 qcom,skip-power-up; 3031 3032 out-ports { 3033 port { 3034 etm2_out: endpoint { 3035 remote-endpoint = <&apss_funnel_in2>; 3036 }; 3037 }; 3038 }; 3039 }; 3040 3041 etm@7340000 { 3042 compatible = "arm,coresight-etm4x", "arm,primecell"; 3043 reg = <0 0x07340000 0 0x1000>; 3044 3045 cpu = <&CPU3>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 arm,coresight-loses-context-with-cpu; 3050 qcom,skip-power-up; 3051 3052 out-ports { 3053 port { 3054 etm3_out: endpoint { 3055 remote-endpoint = <&apss_funnel_in3>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 etm@7440000 { 3062 compatible = "arm,coresight-etm4x", "arm,primecell"; 3063 reg = <0 0x07440000 0 0x1000>; 3064 3065 cpu = <&CPU4>; 3066 3067 clocks = <&aoss_qmp>; 3068 clock-names = "apb_pclk"; 3069 arm,coresight-loses-context-with-cpu; 3070 qcom,skip-power-up; 3071 3072 out-ports { 3073 port { 3074 etm4_out: endpoint { 3075 remote-endpoint = <&apss_funnel_in4>; 3076 }; 3077 }; 3078 }; 3079 }; 3080 3081 etm@7540000 { 3082 compatible = "arm,coresight-etm4x", "arm,primecell"; 3083 reg = <0 0x07540000 0 0x1000>; 3084 3085 cpu = <&CPU5>; 3086 3087 clocks = <&aoss_qmp>; 3088 clock-names = "apb_pclk"; 3089 arm,coresight-loses-context-with-cpu; 3090 qcom,skip-power-up; 3091 3092 out-ports { 3093 port { 3094 etm5_out: endpoint { 3095 remote-endpoint = <&apss_funnel_in5>; 3096 }; 3097 }; 3098 }; 3099 }; 3100 3101 etm@7640000 { 3102 compatible = "arm,coresight-etm4x", "arm,primecell"; 3103 reg = <0 0x07640000 0 0x1000>; 3104 3105 cpu = <&CPU6>; 3106 3107 clocks = <&aoss_qmp>; 3108 clock-names = "apb_pclk"; 3109 arm,coresight-loses-context-with-cpu; 3110 qcom,skip-power-up; 3111 3112 out-ports { 3113 port { 3114 etm6_out: endpoint { 3115 remote-endpoint = <&apss_funnel_in6>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 etm@7740000 { 3122 compatible = "arm,coresight-etm4x", "arm,primecell"; 3123 reg = <0 0x07740000 0 0x1000>; 3124 3125 cpu = <&CPU7>; 3126 3127 clocks = <&aoss_qmp>; 3128 clock-names = "apb_pclk"; 3129 arm,coresight-loses-context-with-cpu; 3130 qcom,skip-power-up; 3131 3132 out-ports { 3133 port { 3134 etm7_out: endpoint { 3135 remote-endpoint = <&apss_funnel_in7>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 funnel@7800000 { /* APSS Funnel */ 3142 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3143 reg = <0 0x07800000 0 0x1000>; 3144 3145 clocks = <&aoss_qmp>; 3146 clock-names = "apb_pclk"; 3147 3148 out-ports { 3149 port { 3150 apss_funnel_out: endpoint { 3151 remote-endpoint = <&apss_merge_funnel_in>; 3152 }; 3153 }; 3154 }; 3155 3156 in-ports { 3157 #address-cells = <1>; 3158 #size-cells = <0>; 3159 3160 port@0 { 3161 reg = <0>; 3162 apss_funnel_in0: endpoint { 3163 remote-endpoint = <&etm0_out>; 3164 }; 3165 }; 3166 3167 port@1 { 3168 reg = <1>; 3169 apss_funnel_in1: endpoint { 3170 remote-endpoint = <&etm1_out>; 3171 }; 3172 }; 3173 3174 port@2 { 3175 reg = <2>; 3176 apss_funnel_in2: endpoint { 3177 remote-endpoint = <&etm2_out>; 3178 }; 3179 }; 3180 3181 port@3 { 3182 reg = <3>; 3183 apss_funnel_in3: endpoint { 3184 remote-endpoint = <&etm3_out>; 3185 }; 3186 }; 3187 3188 port@4 { 3189 reg = <4>; 3190 apss_funnel_in4: endpoint { 3191 remote-endpoint = <&etm4_out>; 3192 }; 3193 }; 3194 3195 port@5 { 3196 reg = <5>; 3197 apss_funnel_in5: endpoint { 3198 remote-endpoint = <&etm5_out>; 3199 }; 3200 }; 3201 3202 port@6 { 3203 reg = <6>; 3204 apss_funnel_in6: endpoint { 3205 remote-endpoint = <&etm6_out>; 3206 }; 3207 }; 3208 3209 port@7 { 3210 reg = <7>; 3211 apss_funnel_in7: endpoint { 3212 remote-endpoint = <&etm7_out>; 3213 }; 3214 }; 3215 }; 3216 }; 3217 3218 funnel@7810000 { 3219 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3220 reg = <0 0x07810000 0 0x1000>; 3221 3222 clocks = <&aoss_qmp>; 3223 clock-names = "apb_pclk"; 3224 3225 out-ports { 3226 port { 3227 apss_merge_funnel_out: endpoint { 3228 remote-endpoint = <&funnel1_in4>; 3229 }; 3230 }; 3231 }; 3232 3233 in-ports { 3234 port { 3235 apss_merge_funnel_in: endpoint { 3236 remote-endpoint = <&apss_funnel_out>; 3237 }; 3238 }; 3239 }; 3240 }; 3241 3242 sdhc_2: mmc@8804000 { 3243 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3244 pinctrl-names = "default", "sleep"; 3245 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3246 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3247 status = "disabled"; 3248 3249 reg = <0 0x08804000 0 0x1000>; 3250 3251 iommus = <&apps_smmu 0x100 0x0>; 3252 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3254 interrupt-names = "hc_irq", "pwr_irq"; 3255 3256 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3257 <&gcc GCC_SDCC2_APPS_CLK>, 3258 <&rpmhcc RPMH_CXO_CLK>; 3259 clock-names = "iface", "core", "xo"; 3260 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3262 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3263 power-domains = <&rpmhpd SC7280_CX>; 3264 operating-points-v2 = <&sdhc2_opp_table>; 3265 3266 bus-width = <4>; 3267 3268 qcom,dll-config = <0x0007642c>; 3269 3270 resets = <&gcc GCC_SDCC2_BCR>; 3271 3272 sdhc2_opp_table: opp-table { 3273 compatible = "operating-points-v2"; 3274 3275 opp-100000000 { 3276 opp-hz = /bits/ 64 <100000000>; 3277 required-opps = <&rpmhpd_opp_low_svs>; 3278 opp-peak-kBps = <1800000 400000>; 3279 opp-avg-kBps = <100000 0>; 3280 }; 3281 3282 opp-202000000 { 3283 opp-hz = /bits/ 64 <202000000>; 3284 required-opps = <&rpmhpd_opp_nom>; 3285 opp-peak-kBps = <5400000 1600000>; 3286 opp-avg-kBps = <200000 0>; 3287 }; 3288 }; 3289 3290 }; 3291 3292 usb_1_hsphy: phy@88e3000 { 3293 compatible = "qcom,sc7280-usb-hs-phy", 3294 "qcom,usb-snps-hs-7nm-phy"; 3295 reg = <0 0x088e3000 0 0x400>; 3296 status = "disabled"; 3297 #phy-cells = <0>; 3298 3299 clocks = <&rpmhcc RPMH_CXO_CLK>; 3300 clock-names = "ref"; 3301 3302 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3303 }; 3304 3305 usb_2_hsphy: phy@88e4000 { 3306 compatible = "qcom,sc7280-usb-hs-phy", 3307 "qcom,usb-snps-hs-7nm-phy"; 3308 reg = <0 0x088e4000 0 0x400>; 3309 status = "disabled"; 3310 #phy-cells = <0>; 3311 3312 clocks = <&rpmhcc RPMH_CXO_CLK>; 3313 clock-names = "ref"; 3314 3315 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3316 }; 3317 3318 usb_1_qmpphy: phy-wrapper@88e9000 { 3319 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3320 "qcom,sm8250-qmp-usb3-dp-phy"; 3321 reg = <0 0x088e9000 0 0x200>, 3322 <0 0x088e8000 0 0x40>, 3323 <0 0x088ea000 0 0x200>; 3324 status = "disabled"; 3325 #address-cells = <2>; 3326 #size-cells = <2>; 3327 ranges; 3328 3329 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3330 <&rpmhcc RPMH_CXO_CLK>, 3331 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3332 clock-names = "aux", "ref_clk_src", "com_aux"; 3333 3334 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3335 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3336 reset-names = "phy", "common"; 3337 3338 usb_1_ssphy: usb3-phy@88e9200 { 3339 reg = <0 0x088e9200 0 0x200>, 3340 <0 0x088e9400 0 0x200>, 3341 <0 0x088e9c00 0 0x400>, 3342 <0 0x088e9600 0 0x200>, 3343 <0 0x088e9800 0 0x200>, 3344 <0 0x088e9a00 0 0x100>; 3345 #clock-cells = <0>; 3346 #phy-cells = <0>; 3347 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3348 clock-names = "pipe0"; 3349 clock-output-names = "usb3_phy_pipe_clk_src"; 3350 }; 3351 3352 dp_phy: dp-phy@88ea200 { 3353 reg = <0 0x088ea200 0 0x200>, 3354 <0 0x088ea400 0 0x200>, 3355 <0 0x088eaa00 0 0x200>, 3356 <0 0x088ea600 0 0x200>, 3357 <0 0x088ea800 0 0x200>; 3358 #phy-cells = <0>; 3359 #clock-cells = <1>; 3360 }; 3361 }; 3362 3363 usb_2: usb@8cf8800 { 3364 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3365 reg = <0 0x08cf8800 0 0x400>; 3366 status = "disabled"; 3367 #address-cells = <2>; 3368 #size-cells = <2>; 3369 ranges; 3370 dma-ranges; 3371 3372 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3373 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3374 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3375 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3376 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3377 clock-names = "cfg_noc", 3378 "core", 3379 "iface", 3380 "sleep", 3381 "mock_utmi"; 3382 3383 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3384 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3385 assigned-clock-rates = <19200000>, <200000000>; 3386 3387 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3388 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3389 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3390 interrupt-names = "hs_phy_irq", 3391 "dp_hs_phy_irq", 3392 "dm_hs_phy_irq"; 3393 3394 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3395 required-opps = <&rpmhpd_opp_nom>; 3396 3397 resets = <&gcc GCC_USB30_SEC_BCR>; 3398 3399 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3400 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3401 interconnect-names = "usb-ddr", "apps-usb"; 3402 3403 usb_2_dwc3: usb@8c00000 { 3404 compatible = "snps,dwc3"; 3405 reg = <0 0x08c00000 0 0xe000>; 3406 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3407 iommus = <&apps_smmu 0xa0 0x0>; 3408 snps,dis_u2_susphy_quirk; 3409 snps,dis_enblslpm_quirk; 3410 phys = <&usb_2_hsphy>; 3411 phy-names = "usb2-phy"; 3412 maximum-speed = "high-speed"; 3413 usb-role-switch; 3414 port { 3415 usb2_role_switch: endpoint { 3416 remote-endpoint = <&eud_ep>; 3417 }; 3418 }; 3419 }; 3420 }; 3421 3422 qspi: spi@88dc000 { 3423 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3424 reg = <0 0x088dc000 0 0x1000>; 3425 #address-cells = <1>; 3426 #size-cells = <0>; 3427 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3428 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3429 <&gcc GCC_QSPI_CORE_CLK>; 3430 clock-names = "iface", "core"; 3431 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3432 &cnoc2 SLAVE_QSPI_0 0>; 3433 interconnect-names = "qspi-config"; 3434 power-domains = <&rpmhpd SC7280_CX>; 3435 operating-points-v2 = <&qspi_opp_table>; 3436 status = "disabled"; 3437 }; 3438 3439 remoteproc_wpss: remoteproc@8a00000 { 3440 compatible = "qcom,sc7280-wpss-pil"; 3441 reg = <0 0x08a00000 0 0x10000>; 3442 3443 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3444 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3445 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3446 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3447 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3448 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3449 interrupt-names = "wdog", "fatal", "ready", "handover", 3450 "stop-ack", "shutdown-ack"; 3451 3452 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3453 <&gcc GCC_WPSS_AHB_CLK>, 3454 <&gcc GCC_WPSS_RSCP_CLK>, 3455 <&rpmhcc RPMH_CXO_CLK>; 3456 clock-names = "ahb_bdg", "ahb", 3457 "rscp", "xo"; 3458 3459 power-domains = <&rpmhpd SC7280_CX>, 3460 <&rpmhpd SC7280_MX>; 3461 power-domain-names = "cx", "mx"; 3462 3463 memory-region = <&wpss_mem>; 3464 3465 qcom,qmp = <&aoss_qmp>; 3466 3467 qcom,smem-states = <&wpss_smp2p_out 0>; 3468 qcom,smem-state-names = "stop"; 3469 3470 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3471 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3472 reset-names = "restart", "pdc_sync"; 3473 3474 qcom,halt-regs = <&tcsr_1 0x17000>; 3475 3476 status = "disabled"; 3477 3478 glink-edge { 3479 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3480 IPCC_MPROC_SIGNAL_GLINK_QMP 3481 IRQ_TYPE_EDGE_RISING>; 3482 mboxes = <&ipcc IPCC_CLIENT_WPSS 3483 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3484 3485 label = "wpss"; 3486 qcom,remote-pid = <13>; 3487 }; 3488 }; 3489 3490 pmu@9091000 { 3491 compatible = "qcom,sc7280-llcc-bwmon"; 3492 reg = <0 0x9091000 0 0x1000>; 3493 3494 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3495 3496 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3497 3498 operating-points-v2 = <&llcc_bwmon_opp_table>; 3499 3500 llcc_bwmon_opp_table: opp-table { 3501 compatible = "operating-points-v2"; 3502 3503 opp-0 { 3504 opp-peak-kBps = <800000>; 3505 }; 3506 opp-1 { 3507 opp-peak-kBps = <1804000>; 3508 }; 3509 opp-2 { 3510 opp-peak-kBps = <2188000>; 3511 }; 3512 opp-3 { 3513 opp-peak-kBps = <3072000>; 3514 }; 3515 opp-4 { 3516 opp-peak-kBps = <4068000>; 3517 }; 3518 opp-5 { 3519 opp-peak-kBps = <6220000>; 3520 }; 3521 opp-6 { 3522 opp-peak-kBps = <6832000>; 3523 }; 3524 opp-7 { 3525 opp-peak-kBps = <8532000>; 3526 }; 3527 }; 3528 }; 3529 3530 pmu@90b6400 { 3531 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3532 reg = <0 0x090b6400 0 0x600>; 3533 3534 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3535 3536 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3537 operating-points-v2 = <&cpu_bwmon_opp_table>; 3538 3539 cpu_bwmon_opp_table: opp-table { 3540 compatible = "operating-points-v2"; 3541 3542 opp-0 { 3543 opp-peak-kBps = <2400000>; 3544 }; 3545 opp-1 { 3546 opp-peak-kBps = <4800000>; 3547 }; 3548 opp-2 { 3549 opp-peak-kBps = <7456000>; 3550 }; 3551 opp-3 { 3552 opp-peak-kBps = <9600000>; 3553 }; 3554 opp-4 { 3555 opp-peak-kBps = <12896000>; 3556 }; 3557 opp-5 { 3558 opp-peak-kBps = <14928000>; 3559 }; 3560 opp-6 { 3561 opp-peak-kBps = <17056000>; 3562 }; 3563 }; 3564 }; 3565 3566 dc_noc: interconnect@90e0000 { 3567 reg = <0 0x090e0000 0 0x5080>; 3568 compatible = "qcom,sc7280-dc-noc"; 3569 #interconnect-cells = <2>; 3570 qcom,bcm-voters = <&apps_bcm_voter>; 3571 }; 3572 3573 gem_noc: interconnect@9100000 { 3574 reg = <0 0x9100000 0 0xe2200>; 3575 compatible = "qcom,sc7280-gem-noc"; 3576 #interconnect-cells = <2>; 3577 qcom,bcm-voters = <&apps_bcm_voter>; 3578 }; 3579 3580 system-cache-controller@9200000 { 3581 compatible = "qcom,sc7280-llcc"; 3582 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3583 reg-names = "llcc_base", "llcc_broadcast_base"; 3584 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3585 }; 3586 3587 eud: eud@88e0000 { 3588 compatible = "qcom,sc7280-eud","qcom,eud"; 3589 reg = <0 0x88e0000 0 0x2000>, 3590 <0 0x88e2000 0 0x1000>; 3591 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3592 ports { 3593 port@0 { 3594 eud_ep: endpoint { 3595 remote-endpoint = <&usb2_role_switch>; 3596 }; 3597 }; 3598 port@1 { 3599 eud_con: endpoint { 3600 remote-endpoint = <&con_eud>; 3601 }; 3602 }; 3603 }; 3604 }; 3605 3606 eud_typec: connector { 3607 compatible = "usb-c-connector"; 3608 ports { 3609 port@0 { 3610 con_eud: endpoint { 3611 remote-endpoint = <&eud_con>; 3612 }; 3613 }; 3614 }; 3615 }; 3616 3617 nsp_noc: interconnect@a0c0000 { 3618 reg = <0 0x0a0c0000 0 0x10000>; 3619 compatible = "qcom,sc7280-nsp-noc"; 3620 #interconnect-cells = <2>; 3621 qcom,bcm-voters = <&apps_bcm_voter>; 3622 }; 3623 3624 usb_1: usb@a6f8800 { 3625 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3626 reg = <0 0x0a6f8800 0 0x400>; 3627 status = "disabled"; 3628 #address-cells = <2>; 3629 #size-cells = <2>; 3630 ranges; 3631 dma-ranges; 3632 3633 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3634 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3635 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3636 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3637 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3638 clock-names = "cfg_noc", 3639 "core", 3640 "iface", 3641 "sleep", 3642 "mock_utmi"; 3643 3644 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3645 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3646 assigned-clock-rates = <19200000>, <200000000>; 3647 3648 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3649 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3650 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3651 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3652 interrupt-names = "hs_phy_irq", 3653 "dp_hs_phy_irq", 3654 "dm_hs_phy_irq", 3655 "ss_phy_irq"; 3656 3657 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3658 required-opps = <&rpmhpd_opp_nom>; 3659 3660 resets = <&gcc GCC_USB30_PRIM_BCR>; 3661 3662 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3663 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3664 interconnect-names = "usb-ddr", "apps-usb"; 3665 3666 wakeup-source; 3667 3668 usb_1_dwc3: usb@a600000 { 3669 compatible = "snps,dwc3"; 3670 reg = <0 0x0a600000 0 0xe000>; 3671 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3672 iommus = <&apps_smmu 0xe0 0x0>; 3673 snps,dis_u2_susphy_quirk; 3674 snps,dis_enblslpm_quirk; 3675 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3676 phy-names = "usb2-phy", "usb3-phy"; 3677 maximum-speed = "super-speed"; 3678 }; 3679 }; 3680 3681 venus: video-codec@aa00000 { 3682 compatible = "qcom,sc7280-venus"; 3683 reg = <0 0x0aa00000 0 0xd0600>; 3684 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3685 3686 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3687 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3688 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3689 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3690 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3691 clock-names = "core", "bus", "iface", 3692 "vcodec_core", "vcodec_bus"; 3693 3694 power-domains = <&videocc MVSC_GDSC>, 3695 <&videocc MVS0_GDSC>, 3696 <&rpmhpd SC7280_CX>; 3697 power-domain-names = "venus", "vcodec0", "cx"; 3698 operating-points-v2 = <&venus_opp_table>; 3699 3700 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3701 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3702 interconnect-names = "cpu-cfg", "video-mem"; 3703 3704 iommus = <&apps_smmu 0x2180 0x20>, 3705 <&apps_smmu 0x2184 0x20>; 3706 memory-region = <&video_mem>; 3707 3708 video-decoder { 3709 compatible = "venus-decoder"; 3710 }; 3711 3712 video-encoder { 3713 compatible = "venus-encoder"; 3714 }; 3715 3716 video-firmware { 3717 iommus = <&apps_smmu 0x21a2 0x0>; 3718 }; 3719 3720 venus_opp_table: opp-table { 3721 compatible = "operating-points-v2"; 3722 3723 opp-133330000 { 3724 opp-hz = /bits/ 64 <133330000>; 3725 required-opps = <&rpmhpd_opp_low_svs>; 3726 }; 3727 3728 opp-240000000 { 3729 opp-hz = /bits/ 64 <240000000>; 3730 required-opps = <&rpmhpd_opp_svs>; 3731 }; 3732 3733 opp-335000000 { 3734 opp-hz = /bits/ 64 <335000000>; 3735 required-opps = <&rpmhpd_opp_svs_l1>; 3736 }; 3737 3738 opp-424000000 { 3739 opp-hz = /bits/ 64 <424000000>; 3740 required-opps = <&rpmhpd_opp_nom>; 3741 }; 3742 3743 opp-460000048 { 3744 opp-hz = /bits/ 64 <460000048>; 3745 required-opps = <&rpmhpd_opp_turbo>; 3746 }; 3747 }; 3748 3749 }; 3750 3751 videocc: clock-controller@aaf0000 { 3752 compatible = "qcom,sc7280-videocc"; 3753 reg = <0 0xaaf0000 0 0x10000>; 3754 clocks = <&rpmhcc RPMH_CXO_CLK>, 3755 <&rpmhcc RPMH_CXO_CLK_A>; 3756 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3757 #clock-cells = <1>; 3758 #reset-cells = <1>; 3759 #power-domain-cells = <1>; 3760 }; 3761 3762 camcc: clock-controller@ad00000 { 3763 compatible = "qcom,sc7280-camcc"; 3764 reg = <0 0x0ad00000 0 0x10000>; 3765 clocks = <&rpmhcc RPMH_CXO_CLK>, 3766 <&rpmhcc RPMH_CXO_CLK_A>, 3767 <&sleep_clk>; 3768 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3769 #clock-cells = <1>; 3770 #reset-cells = <1>; 3771 #power-domain-cells = <1>; 3772 }; 3773 3774 dispcc: clock-controller@af00000 { 3775 compatible = "qcom,sc7280-dispcc"; 3776 reg = <0 0xaf00000 0 0x20000>; 3777 clocks = <&rpmhcc RPMH_CXO_CLK>, 3778 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3779 <&mdss_dsi_phy 0>, 3780 <&mdss_dsi_phy 1>, 3781 <&dp_phy 0>, 3782 <&dp_phy 1>, 3783 <&mdss_edp_phy 0>, 3784 <&mdss_edp_phy 1>; 3785 clock-names = "bi_tcxo", 3786 "gcc_disp_gpll0_clk", 3787 "dsi0_phy_pll_out_byteclk", 3788 "dsi0_phy_pll_out_dsiclk", 3789 "dp_phy_pll_link_clk", 3790 "dp_phy_pll_vco_div_clk", 3791 "edp_phy_pll_link_clk", 3792 "edp_phy_pll_vco_div_clk"; 3793 #clock-cells = <1>; 3794 #reset-cells = <1>; 3795 #power-domain-cells = <1>; 3796 }; 3797 3798 mdss: display-subsystem@ae00000 { 3799 compatible = "qcom,sc7280-mdss"; 3800 reg = <0 0x0ae00000 0 0x1000>; 3801 reg-names = "mdss"; 3802 3803 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3804 3805 clocks = <&gcc GCC_DISP_AHB_CLK>, 3806 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3807 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3808 clock-names = "iface", 3809 "ahb", 3810 "core"; 3811 3812 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3813 interrupt-controller; 3814 #interrupt-cells = <1>; 3815 3816 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3817 interconnect-names = "mdp0-mem"; 3818 3819 iommus = <&apps_smmu 0x900 0x402>; 3820 3821 #address-cells = <2>; 3822 #size-cells = <2>; 3823 ranges; 3824 3825 status = "disabled"; 3826 3827 mdss_mdp: display-controller@ae01000 { 3828 compatible = "qcom,sc7280-dpu"; 3829 reg = <0 0x0ae01000 0 0x8f030>, 3830 <0 0x0aeb0000 0 0x2008>; 3831 reg-names = "mdp", "vbif"; 3832 3833 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3834 <&gcc GCC_DISP_SF_AXI_CLK>, 3835 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3836 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3837 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3838 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3839 clock-names = "bus", 3840 "nrt_bus", 3841 "iface", 3842 "lut", 3843 "core", 3844 "vsync"; 3845 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3846 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3847 assigned-clock-rates = <19200000>, 3848 <19200000>; 3849 operating-points-v2 = <&mdp_opp_table>; 3850 power-domains = <&rpmhpd SC7280_CX>; 3851 3852 interrupt-parent = <&mdss>; 3853 interrupts = <0>; 3854 3855 status = "disabled"; 3856 3857 ports { 3858 #address-cells = <1>; 3859 #size-cells = <0>; 3860 3861 port@0 { 3862 reg = <0>; 3863 dpu_intf1_out: endpoint { 3864 remote-endpoint = <&dsi0_in>; 3865 }; 3866 }; 3867 3868 port@1 { 3869 reg = <1>; 3870 dpu_intf5_out: endpoint { 3871 remote-endpoint = <&edp_in>; 3872 }; 3873 }; 3874 3875 port@2 { 3876 reg = <2>; 3877 dpu_intf0_out: endpoint { 3878 remote-endpoint = <&dp_in>; 3879 }; 3880 }; 3881 }; 3882 3883 mdp_opp_table: opp-table { 3884 compatible = "operating-points-v2"; 3885 3886 opp-200000000 { 3887 opp-hz = /bits/ 64 <200000000>; 3888 required-opps = <&rpmhpd_opp_low_svs>; 3889 }; 3890 3891 opp-300000000 { 3892 opp-hz = /bits/ 64 <300000000>; 3893 required-opps = <&rpmhpd_opp_svs>; 3894 }; 3895 3896 opp-380000000 { 3897 opp-hz = /bits/ 64 <380000000>; 3898 required-opps = <&rpmhpd_opp_svs_l1>; 3899 }; 3900 3901 opp-506666667 { 3902 opp-hz = /bits/ 64 <506666667>; 3903 required-opps = <&rpmhpd_opp_nom>; 3904 }; 3905 }; 3906 }; 3907 3908 mdss_dsi: dsi@ae94000 { 3909 compatible = "qcom,mdss-dsi-ctrl"; 3910 reg = <0 0x0ae94000 0 0x400>; 3911 reg-names = "dsi_ctrl"; 3912 3913 interrupt-parent = <&mdss>; 3914 interrupts = <4>; 3915 3916 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3917 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3918 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3919 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3920 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3921 <&gcc GCC_DISP_HF_AXI_CLK>; 3922 clock-names = "byte", 3923 "byte_intf", 3924 "pixel", 3925 "core", 3926 "iface", 3927 "bus"; 3928 3929 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3930 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3931 3932 operating-points-v2 = <&dsi_opp_table>; 3933 power-domains = <&rpmhpd SC7280_CX>; 3934 3935 phys = <&mdss_dsi_phy>; 3936 3937 #address-cells = <1>; 3938 #size-cells = <0>; 3939 3940 status = "disabled"; 3941 3942 ports { 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 port@0 { 3947 reg = <0>; 3948 dsi0_in: endpoint { 3949 remote-endpoint = <&dpu_intf1_out>; 3950 }; 3951 }; 3952 3953 port@1 { 3954 reg = <1>; 3955 dsi0_out: endpoint { 3956 }; 3957 }; 3958 }; 3959 3960 dsi_opp_table: opp-table { 3961 compatible = "operating-points-v2"; 3962 3963 opp-187500000 { 3964 opp-hz = /bits/ 64 <187500000>; 3965 required-opps = <&rpmhpd_opp_low_svs>; 3966 }; 3967 3968 opp-300000000 { 3969 opp-hz = /bits/ 64 <300000000>; 3970 required-opps = <&rpmhpd_opp_svs>; 3971 }; 3972 3973 opp-358000000 { 3974 opp-hz = /bits/ 64 <358000000>; 3975 required-opps = <&rpmhpd_opp_svs_l1>; 3976 }; 3977 }; 3978 }; 3979 3980 mdss_dsi_phy: phy@ae94400 { 3981 compatible = "qcom,sc7280-dsi-phy-7nm"; 3982 reg = <0 0x0ae94400 0 0x200>, 3983 <0 0x0ae94600 0 0x280>, 3984 <0 0x0ae94900 0 0x280>; 3985 reg-names = "dsi_phy", 3986 "dsi_phy_lane", 3987 "dsi_pll"; 3988 3989 #clock-cells = <1>; 3990 #phy-cells = <0>; 3991 3992 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3993 <&rpmhcc RPMH_CXO_CLK>; 3994 clock-names = "iface", "ref"; 3995 3996 status = "disabled"; 3997 }; 3998 3999 mdss_edp: edp@aea0000 { 4000 compatible = "qcom,sc7280-edp"; 4001 pinctrl-names = "default"; 4002 pinctrl-0 = <&edp_hot_plug_det>; 4003 4004 reg = <0 0xaea0000 0 0x200>, 4005 <0 0xaea0200 0 0x200>, 4006 <0 0xaea0400 0 0xc00>, 4007 <0 0xaea1000 0 0x400>; 4008 4009 interrupt-parent = <&mdss>; 4010 interrupts = <14>; 4011 4012 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4013 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4014 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4015 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4016 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4017 clock-names = "core_iface", 4018 "core_aux", 4019 "ctrl_link", 4020 "ctrl_link_iface", 4021 "stream_pixel"; 4022 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4023 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4024 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4025 4026 phys = <&mdss_edp_phy>; 4027 phy-names = "dp"; 4028 4029 operating-points-v2 = <&edp_opp_table>; 4030 power-domains = <&rpmhpd SC7280_CX>; 4031 4032 status = "disabled"; 4033 4034 ports { 4035 #address-cells = <1>; 4036 #size-cells = <0>; 4037 4038 port@0 { 4039 reg = <0>; 4040 edp_in: endpoint { 4041 remote-endpoint = <&dpu_intf5_out>; 4042 }; 4043 }; 4044 4045 port@1 { 4046 reg = <1>; 4047 mdss_edp_out: endpoint { }; 4048 }; 4049 }; 4050 4051 edp_opp_table: opp-table { 4052 compatible = "operating-points-v2"; 4053 4054 opp-160000000 { 4055 opp-hz = /bits/ 64 <160000000>; 4056 required-opps = <&rpmhpd_opp_low_svs>; 4057 }; 4058 4059 opp-270000000 { 4060 opp-hz = /bits/ 64 <270000000>; 4061 required-opps = <&rpmhpd_opp_svs>; 4062 }; 4063 4064 opp-540000000 { 4065 opp-hz = /bits/ 64 <540000000>; 4066 required-opps = <&rpmhpd_opp_nom>; 4067 }; 4068 4069 opp-810000000 { 4070 opp-hz = /bits/ 64 <810000000>; 4071 required-opps = <&rpmhpd_opp_nom>; 4072 }; 4073 }; 4074 }; 4075 4076 mdss_edp_phy: phy@aec2a00 { 4077 compatible = "qcom,sc7280-edp-phy"; 4078 4079 reg = <0 0xaec2a00 0 0x19c>, 4080 <0 0xaec2200 0 0xa0>, 4081 <0 0xaec2600 0 0xa0>, 4082 <0 0xaec2000 0 0x1c0>; 4083 4084 clocks = <&rpmhcc RPMH_CXO_CLK>, 4085 <&gcc GCC_EDP_CLKREF_EN>; 4086 clock-names = "aux", 4087 "cfg_ahb"; 4088 4089 #clock-cells = <1>; 4090 #phy-cells = <0>; 4091 4092 status = "disabled"; 4093 }; 4094 4095 mdss_dp: displayport-controller@ae90000 { 4096 compatible = "qcom,sc7280-dp"; 4097 4098 reg = <0 0xae90000 0 0x200>, 4099 <0 0xae90200 0 0x200>, 4100 <0 0xae90400 0 0xc00>, 4101 <0 0xae91000 0 0x400>, 4102 <0 0xae91400 0 0x400>; 4103 4104 interrupt-parent = <&mdss>; 4105 interrupts = <12>; 4106 4107 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4108 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4109 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4110 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4111 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4112 clock-names = "core_iface", 4113 "core_aux", 4114 "ctrl_link", 4115 "ctrl_link_iface", 4116 "stream_pixel"; 4117 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4118 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4119 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4120 phys = <&dp_phy>; 4121 phy-names = "dp"; 4122 4123 operating-points-v2 = <&dp_opp_table>; 4124 power-domains = <&rpmhpd SC7280_CX>; 4125 4126 #sound-dai-cells = <0>; 4127 4128 status = "disabled"; 4129 4130 ports { 4131 #address-cells = <1>; 4132 #size-cells = <0>; 4133 4134 port@0 { 4135 reg = <0>; 4136 dp_in: endpoint { 4137 remote-endpoint = <&dpu_intf0_out>; 4138 }; 4139 }; 4140 4141 port@1 { 4142 reg = <1>; 4143 dp_out: endpoint { }; 4144 }; 4145 }; 4146 4147 dp_opp_table: opp-table { 4148 compatible = "operating-points-v2"; 4149 4150 opp-160000000 { 4151 opp-hz = /bits/ 64 <160000000>; 4152 required-opps = <&rpmhpd_opp_low_svs>; 4153 }; 4154 4155 opp-270000000 { 4156 opp-hz = /bits/ 64 <270000000>; 4157 required-opps = <&rpmhpd_opp_svs>; 4158 }; 4159 4160 opp-540000000 { 4161 opp-hz = /bits/ 64 <540000000>; 4162 required-opps = <&rpmhpd_opp_svs_l1>; 4163 }; 4164 4165 opp-810000000 { 4166 opp-hz = /bits/ 64 <810000000>; 4167 required-opps = <&rpmhpd_opp_nom>; 4168 }; 4169 }; 4170 }; 4171 }; 4172 4173 pdc: interrupt-controller@b220000 { 4174 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4175 reg = <0 0x0b220000 0 0x30000>; 4176 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4177 <55 306 4>, <59 312 3>, <62 374 2>, 4178 <64 434 2>, <66 438 3>, <69 86 1>, 4179 <70 520 54>, <124 609 31>, <155 63 1>, 4180 <156 716 12>; 4181 #interrupt-cells = <2>; 4182 interrupt-parent = <&intc>; 4183 interrupt-controller; 4184 }; 4185 4186 pdc_reset: reset-controller@b5e0000 { 4187 compatible = "qcom,sc7280-pdc-global"; 4188 reg = <0 0x0b5e0000 0 0x20000>; 4189 #reset-cells = <1>; 4190 }; 4191 4192 tsens0: thermal-sensor@c263000 { 4193 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4194 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4195 <0 0x0c222000 0 0x1ff>; /* SROT */ 4196 #qcom,sensors = <15>; 4197 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4199 interrupt-names = "uplow","critical"; 4200 #thermal-sensor-cells = <1>; 4201 }; 4202 4203 tsens1: thermal-sensor@c265000 { 4204 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4205 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4206 <0 0x0c223000 0 0x1ff>; /* SROT */ 4207 #qcom,sensors = <12>; 4208 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4210 interrupt-names = "uplow","critical"; 4211 #thermal-sensor-cells = <1>; 4212 }; 4213 4214 aoss_reset: reset-controller@c2a0000 { 4215 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4216 reg = <0 0x0c2a0000 0 0x31000>; 4217 #reset-cells = <1>; 4218 }; 4219 4220 aoss_qmp: power-controller@c300000 { 4221 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4222 reg = <0 0x0c300000 0 0x400>; 4223 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4224 IPCC_MPROC_SIGNAL_GLINK_QMP 4225 IRQ_TYPE_EDGE_RISING>; 4226 mboxes = <&ipcc IPCC_CLIENT_AOP 4227 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4228 4229 #clock-cells = <0>; 4230 }; 4231 4232 sram@c3f0000 { 4233 compatible = "qcom,rpmh-stats"; 4234 reg = <0 0x0c3f0000 0 0x400>; 4235 }; 4236 4237 spmi_bus: spmi@c440000 { 4238 compatible = "qcom,spmi-pmic-arb"; 4239 reg = <0 0x0c440000 0 0x1100>, 4240 <0 0x0c600000 0 0x2000000>, 4241 <0 0x0e600000 0 0x100000>, 4242 <0 0x0e700000 0 0xa0000>, 4243 <0 0x0c40a000 0 0x26000>; 4244 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4245 interrupt-names = "periph_irq"; 4246 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4247 qcom,ee = <0>; 4248 qcom,channel = <0>; 4249 #address-cells = <1>; 4250 #size-cells = <1>; 4251 interrupt-controller; 4252 #interrupt-cells = <4>; 4253 }; 4254 4255 tlmm: pinctrl@f100000 { 4256 compatible = "qcom,sc7280-pinctrl"; 4257 reg = <0 0x0f100000 0 0x300000>; 4258 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4259 gpio-controller; 4260 #gpio-cells = <2>; 4261 interrupt-controller; 4262 #interrupt-cells = <2>; 4263 gpio-ranges = <&tlmm 0 0 175>; 4264 wakeup-parent = <&pdc>; 4265 4266 dp_hot_plug_det: dp-hot-plug-det-state { 4267 pins = "gpio47"; 4268 function = "dp_hot"; 4269 }; 4270 4271 edp_hot_plug_det: edp-hot-plug-det-state { 4272 pins = "gpio60"; 4273 function = "edp_hot"; 4274 }; 4275 4276 mi2s0_data0: mi2s0-data0-state { 4277 pins = "gpio98"; 4278 function = "mi2s0_data0"; 4279 }; 4280 4281 mi2s0_data1: mi2s0-data1-state { 4282 pins = "gpio99"; 4283 function = "mi2s0_data1"; 4284 }; 4285 4286 mi2s0_mclk: mi2s0-mclk-state { 4287 pins = "gpio96"; 4288 function = "pri_mi2s"; 4289 }; 4290 4291 mi2s0_sclk: mi2s0-sclk-state { 4292 pins = "gpio97"; 4293 function = "mi2s0_sck"; 4294 }; 4295 4296 mi2s0_ws: mi2s0-ws-state { 4297 pins = "gpio100"; 4298 function = "mi2s0_ws"; 4299 }; 4300 4301 mi2s1_data0: mi2s1-data0-state { 4302 pins = "gpio107"; 4303 function = "mi2s1_data0"; 4304 }; 4305 4306 mi2s1_sclk: mi2s1-sclk-state { 4307 pins = "gpio106"; 4308 function = "mi2s1_sck"; 4309 }; 4310 4311 mi2s1_ws: mi2s1-ws-state { 4312 pins = "gpio108"; 4313 function = "mi2s1_ws"; 4314 }; 4315 4316 pcie1_clkreq_n: pcie1-clkreq-n-state { 4317 pins = "gpio79"; 4318 function = "pcie1_clkreqn"; 4319 }; 4320 4321 qspi_clk: qspi-clk-state { 4322 pins = "gpio14"; 4323 function = "qspi_clk"; 4324 }; 4325 4326 qspi_cs0: qspi-cs0-state { 4327 pins = "gpio15"; 4328 function = "qspi_cs"; 4329 }; 4330 4331 qspi_cs1: qspi-cs1-state { 4332 pins = "gpio19"; 4333 function = "qspi_cs"; 4334 }; 4335 4336 qspi_data01: qspi-data01-state { 4337 pins = "gpio12", "gpio13"; 4338 function = "qspi_data"; 4339 }; 4340 4341 qspi_data12: qspi-data12-state { 4342 pins = "gpio16", "gpio17"; 4343 function = "qspi_data"; 4344 }; 4345 4346 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4347 pins = "gpio0", "gpio1"; 4348 function = "qup00"; 4349 }; 4350 4351 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4352 pins = "gpio4", "gpio5"; 4353 function = "qup01"; 4354 }; 4355 4356 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4357 pins = "gpio8", "gpio9"; 4358 function = "qup02"; 4359 }; 4360 4361 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4362 pins = "gpio12", "gpio13"; 4363 function = "qup03"; 4364 }; 4365 4366 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4367 pins = "gpio16", "gpio17"; 4368 function = "qup04"; 4369 }; 4370 4371 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4372 pins = "gpio20", "gpio21"; 4373 function = "qup05"; 4374 }; 4375 4376 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4377 pins = "gpio24", "gpio25"; 4378 function = "qup06"; 4379 }; 4380 4381 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4382 pins = "gpio28", "gpio29"; 4383 function = "qup07"; 4384 }; 4385 4386 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4387 pins = "gpio32", "gpio33"; 4388 function = "qup10"; 4389 }; 4390 4391 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4392 pins = "gpio36", "gpio37"; 4393 function = "qup11"; 4394 }; 4395 4396 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4397 pins = "gpio40", "gpio41"; 4398 function = "qup12"; 4399 }; 4400 4401 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4402 pins = "gpio44", "gpio45"; 4403 function = "qup13"; 4404 }; 4405 4406 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4407 pins = "gpio48", "gpio49"; 4408 function = "qup14"; 4409 }; 4410 4411 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4412 pins = "gpio52", "gpio53"; 4413 function = "qup15"; 4414 }; 4415 4416 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4417 pins = "gpio56", "gpio57"; 4418 function = "qup16"; 4419 }; 4420 4421 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4422 pins = "gpio60", "gpio61"; 4423 function = "qup17"; 4424 }; 4425 4426 qup_spi0_data_clk: qup-spi0-data-clk-state { 4427 pins = "gpio0", "gpio1", "gpio2"; 4428 function = "qup00"; 4429 }; 4430 4431 qup_spi0_cs: qup-spi0-cs-state { 4432 pins = "gpio3"; 4433 function = "qup00"; 4434 }; 4435 4436 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4437 pins = "gpio3"; 4438 function = "gpio"; 4439 }; 4440 4441 qup_spi1_data_clk: qup-spi1-data-clk-state { 4442 pins = "gpio4", "gpio5", "gpio6"; 4443 function = "qup01"; 4444 }; 4445 4446 qup_spi1_cs: qup-spi1-cs-state { 4447 pins = "gpio7"; 4448 function = "qup01"; 4449 }; 4450 4451 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4452 pins = "gpio7"; 4453 function = "gpio"; 4454 }; 4455 4456 qup_spi2_data_clk: qup-spi2-data-clk-state { 4457 pins = "gpio8", "gpio9", "gpio10"; 4458 function = "qup02"; 4459 }; 4460 4461 qup_spi2_cs: qup-spi2-cs-state { 4462 pins = "gpio11"; 4463 function = "qup02"; 4464 }; 4465 4466 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4467 pins = "gpio11"; 4468 function = "gpio"; 4469 }; 4470 4471 qup_spi3_data_clk: qup-spi3-data-clk-state { 4472 pins = "gpio12", "gpio13", "gpio14"; 4473 function = "qup03"; 4474 }; 4475 4476 qup_spi3_cs: qup-spi3-cs-state { 4477 pins = "gpio15"; 4478 function = "qup03"; 4479 }; 4480 4481 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4482 pins = "gpio15"; 4483 function = "gpio"; 4484 }; 4485 4486 qup_spi4_data_clk: qup-spi4-data-clk-state { 4487 pins = "gpio16", "gpio17", "gpio18"; 4488 function = "qup04"; 4489 }; 4490 4491 qup_spi4_cs: qup-spi4-cs-state { 4492 pins = "gpio19"; 4493 function = "qup04"; 4494 }; 4495 4496 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4497 pins = "gpio19"; 4498 function = "gpio"; 4499 }; 4500 4501 qup_spi5_data_clk: qup-spi5-data-clk-state { 4502 pins = "gpio20", "gpio21", "gpio22"; 4503 function = "qup05"; 4504 }; 4505 4506 qup_spi5_cs: qup-spi5-cs-state { 4507 pins = "gpio23"; 4508 function = "qup05"; 4509 }; 4510 4511 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4512 pins = "gpio23"; 4513 function = "gpio"; 4514 }; 4515 4516 qup_spi6_data_clk: qup-spi6-data-clk-state { 4517 pins = "gpio24", "gpio25", "gpio26"; 4518 function = "qup06"; 4519 }; 4520 4521 qup_spi6_cs: qup-spi6-cs-state { 4522 pins = "gpio27"; 4523 function = "qup06"; 4524 }; 4525 4526 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4527 pins = "gpio27"; 4528 function = "gpio"; 4529 }; 4530 4531 qup_spi7_data_clk: qup-spi7-data-clk-state { 4532 pins = "gpio28", "gpio29", "gpio30"; 4533 function = "qup07"; 4534 }; 4535 4536 qup_spi7_cs: qup-spi7-cs-state { 4537 pins = "gpio31"; 4538 function = "qup07"; 4539 }; 4540 4541 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4542 pins = "gpio31"; 4543 function = "gpio"; 4544 }; 4545 4546 qup_spi8_data_clk: qup-spi8-data-clk-state { 4547 pins = "gpio32", "gpio33", "gpio34"; 4548 function = "qup10"; 4549 }; 4550 4551 qup_spi8_cs: qup-spi8-cs-state { 4552 pins = "gpio35"; 4553 function = "qup10"; 4554 }; 4555 4556 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4557 pins = "gpio35"; 4558 function = "gpio"; 4559 }; 4560 4561 qup_spi9_data_clk: qup-spi9-data-clk-state { 4562 pins = "gpio36", "gpio37", "gpio38"; 4563 function = "qup11"; 4564 }; 4565 4566 qup_spi9_cs: qup-spi9-cs-state { 4567 pins = "gpio39"; 4568 function = "qup11"; 4569 }; 4570 4571 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4572 pins = "gpio39"; 4573 function = "gpio"; 4574 }; 4575 4576 qup_spi10_data_clk: qup-spi10-data-clk-state { 4577 pins = "gpio40", "gpio41", "gpio42"; 4578 function = "qup12"; 4579 }; 4580 4581 qup_spi10_cs: qup-spi10-cs-state { 4582 pins = "gpio43"; 4583 function = "qup12"; 4584 }; 4585 4586 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4587 pins = "gpio43"; 4588 function = "gpio"; 4589 }; 4590 4591 qup_spi11_data_clk: qup-spi11-data-clk-state { 4592 pins = "gpio44", "gpio45", "gpio46"; 4593 function = "qup13"; 4594 }; 4595 4596 qup_spi11_cs: qup-spi11-cs-state { 4597 pins = "gpio47"; 4598 function = "qup13"; 4599 }; 4600 4601 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4602 pins = "gpio47"; 4603 function = "gpio"; 4604 }; 4605 4606 qup_spi12_data_clk: qup-spi12-data-clk-state { 4607 pins = "gpio48", "gpio49", "gpio50"; 4608 function = "qup14"; 4609 }; 4610 4611 qup_spi12_cs: qup-spi12-cs-state { 4612 pins = "gpio51"; 4613 function = "qup14"; 4614 }; 4615 4616 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4617 pins = "gpio51"; 4618 function = "gpio"; 4619 }; 4620 4621 qup_spi13_data_clk: qup-spi13-data-clk-state { 4622 pins = "gpio52", "gpio53", "gpio54"; 4623 function = "qup15"; 4624 }; 4625 4626 qup_spi13_cs: qup-spi13-cs-state { 4627 pins = "gpio55"; 4628 function = "qup15"; 4629 }; 4630 4631 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4632 pins = "gpio55"; 4633 function = "gpio"; 4634 }; 4635 4636 qup_spi14_data_clk: qup-spi14-data-clk-state { 4637 pins = "gpio56", "gpio57", "gpio58"; 4638 function = "qup16"; 4639 }; 4640 4641 qup_spi14_cs: qup-spi14-cs-state { 4642 pins = "gpio59"; 4643 function = "qup16"; 4644 }; 4645 4646 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4647 pins = "gpio59"; 4648 function = "gpio"; 4649 }; 4650 4651 qup_spi15_data_clk: qup-spi15-data-clk-state { 4652 pins = "gpio60", "gpio61", "gpio62"; 4653 function = "qup17"; 4654 }; 4655 4656 qup_spi15_cs: qup-spi15-cs-state { 4657 pins = "gpio63"; 4658 function = "qup17"; 4659 }; 4660 4661 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4662 pins = "gpio63"; 4663 function = "gpio"; 4664 }; 4665 4666 qup_uart0_cts: qup-uart0-cts-state { 4667 pins = "gpio0"; 4668 function = "qup00"; 4669 }; 4670 4671 qup_uart0_rts: qup-uart0-rts-state { 4672 pins = "gpio1"; 4673 function = "qup00"; 4674 }; 4675 4676 qup_uart0_tx: qup-uart0-tx-state { 4677 pins = "gpio2"; 4678 function = "qup00"; 4679 }; 4680 4681 qup_uart0_rx: qup-uart0-rx-state { 4682 pins = "gpio3"; 4683 function = "qup00"; 4684 }; 4685 4686 qup_uart1_cts: qup-uart1-cts-state { 4687 pins = "gpio4"; 4688 function = "qup01"; 4689 }; 4690 4691 qup_uart1_rts: qup-uart1-rts-state { 4692 pins = "gpio5"; 4693 function = "qup01"; 4694 }; 4695 4696 qup_uart1_tx: qup-uart1-tx-state { 4697 pins = "gpio6"; 4698 function = "qup01"; 4699 }; 4700 4701 qup_uart1_rx: qup-uart1-rx-state { 4702 pins = "gpio7"; 4703 function = "qup01"; 4704 }; 4705 4706 qup_uart2_cts: qup-uart2-cts-state { 4707 pins = "gpio8"; 4708 function = "qup02"; 4709 }; 4710 4711 qup_uart2_rts: qup-uart2-rts-state { 4712 pins = "gpio9"; 4713 function = "qup02"; 4714 }; 4715 4716 qup_uart2_tx: qup-uart2-tx-state { 4717 pins = "gpio10"; 4718 function = "qup02"; 4719 }; 4720 4721 qup_uart2_rx: qup-uart2-rx-state { 4722 pins = "gpio11"; 4723 function = "qup02"; 4724 }; 4725 4726 qup_uart3_cts: qup-uart3-cts-state { 4727 pins = "gpio12"; 4728 function = "qup03"; 4729 }; 4730 4731 qup_uart3_rts: qup-uart3-rts-state { 4732 pins = "gpio13"; 4733 function = "qup03"; 4734 }; 4735 4736 qup_uart3_tx: qup-uart3-tx-state { 4737 pins = "gpio14"; 4738 function = "qup03"; 4739 }; 4740 4741 qup_uart3_rx: qup-uart3-rx-state { 4742 pins = "gpio15"; 4743 function = "qup03"; 4744 }; 4745 4746 qup_uart4_cts: qup-uart4-cts-state { 4747 pins = "gpio16"; 4748 function = "qup04"; 4749 }; 4750 4751 qup_uart4_rts: qup-uart4-rts-state { 4752 pins = "gpio17"; 4753 function = "qup04"; 4754 }; 4755 4756 qup_uart4_tx: qup-uart4-tx-state { 4757 pins = "gpio18"; 4758 function = "qup04"; 4759 }; 4760 4761 qup_uart4_rx: qup-uart4-rx-state { 4762 pins = "gpio19"; 4763 function = "qup04"; 4764 }; 4765 4766 qup_uart5_cts: qup-uart5-cts-state { 4767 pins = "gpio20"; 4768 function = "qup05"; 4769 }; 4770 4771 qup_uart5_rts: qup-uart5-rts-state { 4772 pins = "gpio21"; 4773 function = "qup05"; 4774 }; 4775 4776 qup_uart5_tx: qup-uart5-tx-state { 4777 pins = "gpio22"; 4778 function = "qup05"; 4779 }; 4780 4781 qup_uart5_rx: qup-uart5-rx-state { 4782 pins = "gpio23"; 4783 function = "qup05"; 4784 }; 4785 4786 qup_uart6_cts: qup-uart6-cts-state { 4787 pins = "gpio24"; 4788 function = "qup06"; 4789 }; 4790 4791 qup_uart6_rts: qup-uart6-rts-state { 4792 pins = "gpio25"; 4793 function = "qup06"; 4794 }; 4795 4796 qup_uart6_tx: qup-uart6-tx-state { 4797 pins = "gpio26"; 4798 function = "qup06"; 4799 }; 4800 4801 qup_uart6_rx: qup-uart6-rx-state { 4802 pins = "gpio27"; 4803 function = "qup06"; 4804 }; 4805 4806 qup_uart7_cts: qup-uart7-cts-state { 4807 pins = "gpio28"; 4808 function = "qup07"; 4809 }; 4810 4811 qup_uart7_rts: qup-uart7-rts-state { 4812 pins = "gpio29"; 4813 function = "qup07"; 4814 }; 4815 4816 qup_uart7_tx: qup-uart7-tx-state { 4817 pins = "gpio30"; 4818 function = "qup07"; 4819 }; 4820 4821 qup_uart7_rx: qup-uart7-rx-state { 4822 pins = "gpio31"; 4823 function = "qup07"; 4824 }; 4825 4826 qup_uart8_cts: qup-uart8-cts-state { 4827 pins = "gpio32"; 4828 function = "qup10"; 4829 }; 4830 4831 qup_uart8_rts: qup-uart8-rts-state { 4832 pins = "gpio33"; 4833 function = "qup10"; 4834 }; 4835 4836 qup_uart8_tx: qup-uart8-tx-state { 4837 pins = "gpio34"; 4838 function = "qup10"; 4839 }; 4840 4841 qup_uart8_rx: qup-uart8-rx-state { 4842 pins = "gpio35"; 4843 function = "qup10"; 4844 }; 4845 4846 qup_uart9_cts: qup-uart9-cts-state { 4847 pins = "gpio36"; 4848 function = "qup11"; 4849 }; 4850 4851 qup_uart9_rts: qup-uart9-rts-state { 4852 pins = "gpio37"; 4853 function = "qup11"; 4854 }; 4855 4856 qup_uart9_tx: qup-uart9-tx-state { 4857 pins = "gpio38"; 4858 function = "qup11"; 4859 }; 4860 4861 qup_uart9_rx: qup-uart9-rx-state { 4862 pins = "gpio39"; 4863 function = "qup11"; 4864 }; 4865 4866 qup_uart10_cts: qup-uart10-cts-state { 4867 pins = "gpio40"; 4868 function = "qup12"; 4869 }; 4870 4871 qup_uart10_rts: qup-uart10-rts-state { 4872 pins = "gpio41"; 4873 function = "qup12"; 4874 }; 4875 4876 qup_uart10_tx: qup-uart10-tx-state { 4877 pins = "gpio42"; 4878 function = "qup12"; 4879 }; 4880 4881 qup_uart10_rx: qup-uart10-rx-state { 4882 pins = "gpio43"; 4883 function = "qup12"; 4884 }; 4885 4886 qup_uart11_cts: qup-uart11-cts-state { 4887 pins = "gpio44"; 4888 function = "qup13"; 4889 }; 4890 4891 qup_uart11_rts: qup-uart11-rts-state { 4892 pins = "gpio45"; 4893 function = "qup13"; 4894 }; 4895 4896 qup_uart11_tx: qup-uart11-tx-state { 4897 pins = "gpio46"; 4898 function = "qup13"; 4899 }; 4900 4901 qup_uart11_rx: qup-uart11-rx-state { 4902 pins = "gpio47"; 4903 function = "qup13"; 4904 }; 4905 4906 qup_uart12_cts: qup-uart12-cts-state { 4907 pins = "gpio48"; 4908 function = "qup14"; 4909 }; 4910 4911 qup_uart12_rts: qup-uart12-rts-state { 4912 pins = "gpio49"; 4913 function = "qup14"; 4914 }; 4915 4916 qup_uart12_tx: qup-uart12-tx-state { 4917 pins = "gpio50"; 4918 function = "qup14"; 4919 }; 4920 4921 qup_uart12_rx: qup-uart12-rx-state { 4922 pins = "gpio51"; 4923 function = "qup14"; 4924 }; 4925 4926 qup_uart13_cts: qup-uart13-cts-state { 4927 pins = "gpio52"; 4928 function = "qup15"; 4929 }; 4930 4931 qup_uart13_rts: qup-uart13-rts-state { 4932 pins = "gpio53"; 4933 function = "qup15"; 4934 }; 4935 4936 qup_uart13_tx: qup-uart13-tx-state { 4937 pins = "gpio54"; 4938 function = "qup15"; 4939 }; 4940 4941 qup_uart13_rx: qup-uart13-rx-state { 4942 pins = "gpio55"; 4943 function = "qup15"; 4944 }; 4945 4946 qup_uart14_cts: qup-uart14-cts-state { 4947 pins = "gpio56"; 4948 function = "qup16"; 4949 }; 4950 4951 qup_uart14_rts: qup-uart14-rts-state { 4952 pins = "gpio57"; 4953 function = "qup16"; 4954 }; 4955 4956 qup_uart14_tx: qup-uart14-tx-state { 4957 pins = "gpio58"; 4958 function = "qup16"; 4959 }; 4960 4961 qup_uart14_rx: qup-uart14-rx-state { 4962 pins = "gpio59"; 4963 function = "qup16"; 4964 }; 4965 4966 qup_uart15_cts: qup-uart15-cts-state { 4967 pins = "gpio60"; 4968 function = "qup17"; 4969 }; 4970 4971 qup_uart15_rts: qup-uart15-rts-state { 4972 pins = "gpio61"; 4973 function = "qup17"; 4974 }; 4975 4976 qup_uart15_tx: qup-uart15-tx-state { 4977 pins = "gpio62"; 4978 function = "qup17"; 4979 }; 4980 4981 qup_uart15_rx: qup-uart15-rx-state { 4982 pins = "gpio63"; 4983 function = "qup17"; 4984 }; 4985 4986 sdc1_clk: sdc1-clk-state { 4987 pins = "sdc1_clk"; 4988 }; 4989 4990 sdc1_cmd: sdc1-cmd-state { 4991 pins = "sdc1_cmd"; 4992 }; 4993 4994 sdc1_data: sdc1-data-state { 4995 pins = "sdc1_data"; 4996 }; 4997 4998 sdc1_rclk: sdc1-rclk-state { 4999 pins = "sdc1_rclk"; 5000 }; 5001 5002 sdc1_clk_sleep: sdc1-clk-sleep-state { 5003 pins = "sdc1_clk"; 5004 drive-strength = <2>; 5005 bias-bus-hold; 5006 }; 5007 5008 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5009 pins = "sdc1_cmd"; 5010 drive-strength = <2>; 5011 bias-bus-hold; 5012 }; 5013 5014 sdc1_data_sleep: sdc1-data-sleep-state { 5015 pins = "sdc1_data"; 5016 drive-strength = <2>; 5017 bias-bus-hold; 5018 }; 5019 5020 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5021 pins = "sdc1_rclk"; 5022 drive-strength = <2>; 5023 bias-bus-hold; 5024 }; 5025 5026 sdc2_clk: sdc2-clk-state { 5027 pins = "sdc2_clk"; 5028 }; 5029 5030 sdc2_cmd: sdc2-cmd-state { 5031 pins = "sdc2_cmd"; 5032 }; 5033 5034 sdc2_data: sdc2-data-state { 5035 pins = "sdc2_data"; 5036 }; 5037 5038 sdc2_clk_sleep: sdc2-clk-sleep-state { 5039 pins = "sdc2_clk"; 5040 drive-strength = <2>; 5041 bias-bus-hold; 5042 }; 5043 5044 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5045 pins = "sdc2_cmd"; 5046 drive-strength = <2>; 5047 bias-bus-hold; 5048 }; 5049 5050 sdc2_data_sleep: sdc2-data-sleep-state { 5051 pins = "sdc2_data"; 5052 drive-strength = <2>; 5053 bias-bus-hold; 5054 }; 5055 }; 5056 5057 sram@146a5000 { 5058 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5059 reg = <0 0x146a5000 0 0x6000>; 5060 5061 #address-cells = <1>; 5062 #size-cells = <1>; 5063 5064 ranges = <0 0 0x146a5000 0x6000>; 5065 5066 pil-reloc@594c { 5067 compatible = "qcom,pil-reloc-info"; 5068 reg = <0x594c 0xc8>; 5069 }; 5070 }; 5071 5072 apps_smmu: iommu@15000000 { 5073 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5074 reg = <0 0x15000000 0 0x100000>; 5075 #iommu-cells = <2>; 5076 #global-interrupts = <1>; 5077 dma-coherent; 5078 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5159 }; 5160 5161 intc: interrupt-controller@17a00000 { 5162 compatible = "arm,gic-v3"; 5163 #address-cells = <2>; 5164 #size-cells = <2>; 5165 ranges; 5166 #interrupt-cells = <3>; 5167 interrupt-controller; 5168 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5169 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5170 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5171 5172 gic-its@17a40000 { 5173 compatible = "arm,gic-v3-its"; 5174 msi-controller; 5175 #msi-cells = <1>; 5176 reg = <0 0x17a40000 0 0x20000>; 5177 status = "disabled"; 5178 }; 5179 }; 5180 5181 watchdog@17c10000 { 5182 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5183 reg = <0 0x17c10000 0 0x1000>; 5184 clocks = <&sleep_clk>; 5185 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5186 }; 5187 5188 timer@17c20000 { 5189 #address-cells = <1>; 5190 #size-cells = <1>; 5191 ranges = <0 0 0 0x20000000>; 5192 compatible = "arm,armv7-timer-mem"; 5193 reg = <0 0x17c20000 0 0x1000>; 5194 5195 frame@17c21000 { 5196 frame-number = <0>; 5197 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5199 reg = <0x17c21000 0x1000>, 5200 <0x17c22000 0x1000>; 5201 }; 5202 5203 frame@17c23000 { 5204 frame-number = <1>; 5205 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5206 reg = <0x17c23000 0x1000>; 5207 status = "disabled"; 5208 }; 5209 5210 frame@17c25000 { 5211 frame-number = <2>; 5212 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5213 reg = <0x17c25000 0x1000>; 5214 status = "disabled"; 5215 }; 5216 5217 frame@17c27000 { 5218 frame-number = <3>; 5219 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5220 reg = <0x17c27000 0x1000>; 5221 status = "disabled"; 5222 }; 5223 5224 frame@17c29000 { 5225 frame-number = <4>; 5226 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5227 reg = <0x17c29000 0x1000>; 5228 status = "disabled"; 5229 }; 5230 5231 frame@17c2b000 { 5232 frame-number = <5>; 5233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5234 reg = <0x17c2b000 0x1000>; 5235 status = "disabled"; 5236 }; 5237 5238 frame@17c2d000 { 5239 frame-number = <6>; 5240 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5241 reg = <0x17c2d000 0x1000>; 5242 status = "disabled"; 5243 }; 5244 }; 5245 5246 apps_rsc: rsc@18200000 { 5247 compatible = "qcom,rpmh-rsc"; 5248 reg = <0 0x18200000 0 0x10000>, 5249 <0 0x18210000 0 0x10000>, 5250 <0 0x18220000 0 0x10000>; 5251 reg-names = "drv-0", "drv-1", "drv-2"; 5252 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5253 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5254 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5255 qcom,tcs-offset = <0xd00>; 5256 qcom,drv-id = <2>; 5257 qcom,tcs-config = <ACTIVE_TCS 2>, 5258 <SLEEP_TCS 3>, 5259 <WAKE_TCS 3>, 5260 <CONTROL_TCS 1>; 5261 5262 apps_bcm_voter: bcm-voter { 5263 compatible = "qcom,bcm-voter"; 5264 }; 5265 5266 rpmhpd: power-controller { 5267 compatible = "qcom,sc7280-rpmhpd"; 5268 #power-domain-cells = <1>; 5269 operating-points-v2 = <&rpmhpd_opp_table>; 5270 5271 rpmhpd_opp_table: opp-table { 5272 compatible = "operating-points-v2"; 5273 5274 rpmhpd_opp_ret: opp1 { 5275 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5276 }; 5277 5278 rpmhpd_opp_low_svs: opp2 { 5279 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5280 }; 5281 5282 rpmhpd_opp_svs: opp3 { 5283 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5284 }; 5285 5286 rpmhpd_opp_svs_l1: opp4 { 5287 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5288 }; 5289 5290 rpmhpd_opp_svs_l2: opp5 { 5291 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5292 }; 5293 5294 rpmhpd_opp_nom: opp6 { 5295 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5296 }; 5297 5298 rpmhpd_opp_nom_l1: opp7 { 5299 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5300 }; 5301 5302 rpmhpd_opp_turbo: opp8 { 5303 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5304 }; 5305 5306 rpmhpd_opp_turbo_l1: opp9 { 5307 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5308 }; 5309 }; 5310 }; 5311 5312 rpmhcc: clock-controller { 5313 compatible = "qcom,sc7280-rpmh-clk"; 5314 clocks = <&xo_board>; 5315 clock-names = "xo"; 5316 #clock-cells = <1>; 5317 }; 5318 }; 5319 5320 epss_l3: interconnect@18590000 { 5321 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5322 reg = <0 0x18590000 0 0x1000>; 5323 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5324 clock-names = "xo", "alternate"; 5325 #interconnect-cells = <1>; 5326 }; 5327 5328 cpufreq_hw: cpufreq@18591000 { 5329 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5330 reg = <0 0x18591000 0 0x1000>, 5331 <0 0x18592000 0 0x1000>, 5332 <0 0x18593000 0 0x1000>; 5333 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5334 clock-names = "xo", "alternate"; 5335 #freq-domain-cells = <1>; 5336 }; 5337 }; 5338 5339 thermal_zones: thermal-zones { 5340 cpu0-thermal { 5341 polling-delay-passive = <250>; 5342 polling-delay = <0>; 5343 5344 thermal-sensors = <&tsens0 1>; 5345 5346 trips { 5347 cpu0_alert0: trip-point0 { 5348 temperature = <90000>; 5349 hysteresis = <2000>; 5350 type = "passive"; 5351 }; 5352 5353 cpu0_alert1: trip-point1 { 5354 temperature = <95000>; 5355 hysteresis = <2000>; 5356 type = "passive"; 5357 }; 5358 5359 cpu0_crit: cpu-crit { 5360 temperature = <110000>; 5361 hysteresis = <0>; 5362 type = "critical"; 5363 }; 5364 }; 5365 5366 cooling-maps { 5367 map0 { 5368 trip = <&cpu0_alert0>; 5369 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5370 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5371 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5372 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5373 }; 5374 map1 { 5375 trip = <&cpu0_alert1>; 5376 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5377 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5378 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5379 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5380 }; 5381 }; 5382 }; 5383 5384 cpu1-thermal { 5385 polling-delay-passive = <250>; 5386 polling-delay = <0>; 5387 5388 thermal-sensors = <&tsens0 2>; 5389 5390 trips { 5391 cpu1_alert0: trip-point0 { 5392 temperature = <90000>; 5393 hysteresis = <2000>; 5394 type = "passive"; 5395 }; 5396 5397 cpu1_alert1: trip-point1 { 5398 temperature = <95000>; 5399 hysteresis = <2000>; 5400 type = "passive"; 5401 }; 5402 5403 cpu1_crit: cpu-crit { 5404 temperature = <110000>; 5405 hysteresis = <0>; 5406 type = "critical"; 5407 }; 5408 }; 5409 5410 cooling-maps { 5411 map0 { 5412 trip = <&cpu1_alert0>; 5413 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5414 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5415 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5416 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5417 }; 5418 map1 { 5419 trip = <&cpu1_alert1>; 5420 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5421 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5422 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5423 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5424 }; 5425 }; 5426 }; 5427 5428 cpu2-thermal { 5429 polling-delay-passive = <250>; 5430 polling-delay = <0>; 5431 5432 thermal-sensors = <&tsens0 3>; 5433 5434 trips { 5435 cpu2_alert0: trip-point0 { 5436 temperature = <90000>; 5437 hysteresis = <2000>; 5438 type = "passive"; 5439 }; 5440 5441 cpu2_alert1: trip-point1 { 5442 temperature = <95000>; 5443 hysteresis = <2000>; 5444 type = "passive"; 5445 }; 5446 5447 cpu2_crit: cpu-crit { 5448 temperature = <110000>; 5449 hysteresis = <0>; 5450 type = "critical"; 5451 }; 5452 }; 5453 5454 cooling-maps { 5455 map0 { 5456 trip = <&cpu2_alert0>; 5457 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5458 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5459 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5460 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5461 }; 5462 map1 { 5463 trip = <&cpu2_alert1>; 5464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5468 }; 5469 }; 5470 }; 5471 5472 cpu3-thermal { 5473 polling-delay-passive = <250>; 5474 polling-delay = <0>; 5475 5476 thermal-sensors = <&tsens0 4>; 5477 5478 trips { 5479 cpu3_alert0: trip-point0 { 5480 temperature = <90000>; 5481 hysteresis = <2000>; 5482 type = "passive"; 5483 }; 5484 5485 cpu3_alert1: trip-point1 { 5486 temperature = <95000>; 5487 hysteresis = <2000>; 5488 type = "passive"; 5489 }; 5490 5491 cpu3_crit: cpu-crit { 5492 temperature = <110000>; 5493 hysteresis = <0>; 5494 type = "critical"; 5495 }; 5496 }; 5497 5498 cooling-maps { 5499 map0 { 5500 trip = <&cpu3_alert0>; 5501 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5502 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5503 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5504 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5505 }; 5506 map1 { 5507 trip = <&cpu3_alert1>; 5508 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5509 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5510 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5511 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5512 }; 5513 }; 5514 }; 5515 5516 cpu4-thermal { 5517 polling-delay-passive = <250>; 5518 polling-delay = <0>; 5519 5520 thermal-sensors = <&tsens0 7>; 5521 5522 trips { 5523 cpu4_alert0: trip-point0 { 5524 temperature = <90000>; 5525 hysteresis = <2000>; 5526 type = "passive"; 5527 }; 5528 5529 cpu4_alert1: trip-point1 { 5530 temperature = <95000>; 5531 hysteresis = <2000>; 5532 type = "passive"; 5533 }; 5534 5535 cpu4_crit: cpu-crit { 5536 temperature = <110000>; 5537 hysteresis = <0>; 5538 type = "critical"; 5539 }; 5540 }; 5541 5542 cooling-maps { 5543 map0 { 5544 trip = <&cpu4_alert0>; 5545 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5546 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5547 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5548 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5549 }; 5550 map1 { 5551 trip = <&cpu4_alert1>; 5552 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5553 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5554 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5555 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5556 }; 5557 }; 5558 }; 5559 5560 cpu5-thermal { 5561 polling-delay-passive = <250>; 5562 polling-delay = <0>; 5563 5564 thermal-sensors = <&tsens0 8>; 5565 5566 trips { 5567 cpu5_alert0: trip-point0 { 5568 temperature = <90000>; 5569 hysteresis = <2000>; 5570 type = "passive"; 5571 }; 5572 5573 cpu5_alert1: trip-point1 { 5574 temperature = <95000>; 5575 hysteresis = <2000>; 5576 type = "passive"; 5577 }; 5578 5579 cpu5_crit: cpu-crit { 5580 temperature = <110000>; 5581 hysteresis = <0>; 5582 type = "critical"; 5583 }; 5584 }; 5585 5586 cooling-maps { 5587 map0 { 5588 trip = <&cpu5_alert0>; 5589 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5590 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5591 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5592 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5593 }; 5594 map1 { 5595 trip = <&cpu5_alert1>; 5596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5600 }; 5601 }; 5602 }; 5603 5604 cpu6-thermal { 5605 polling-delay-passive = <250>; 5606 polling-delay = <0>; 5607 5608 thermal-sensors = <&tsens0 9>; 5609 5610 trips { 5611 cpu6_alert0: trip-point0 { 5612 temperature = <90000>; 5613 hysteresis = <2000>; 5614 type = "passive"; 5615 }; 5616 5617 cpu6_alert1: trip-point1 { 5618 temperature = <95000>; 5619 hysteresis = <2000>; 5620 type = "passive"; 5621 }; 5622 5623 cpu6_crit: cpu-crit { 5624 temperature = <110000>; 5625 hysteresis = <0>; 5626 type = "critical"; 5627 }; 5628 }; 5629 5630 cooling-maps { 5631 map0 { 5632 trip = <&cpu6_alert0>; 5633 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5634 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5635 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5636 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5637 }; 5638 map1 { 5639 trip = <&cpu6_alert1>; 5640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5644 }; 5645 }; 5646 }; 5647 5648 cpu7-thermal { 5649 polling-delay-passive = <250>; 5650 polling-delay = <0>; 5651 5652 thermal-sensors = <&tsens0 10>; 5653 5654 trips { 5655 cpu7_alert0: trip-point0 { 5656 temperature = <90000>; 5657 hysteresis = <2000>; 5658 type = "passive"; 5659 }; 5660 5661 cpu7_alert1: trip-point1 { 5662 temperature = <95000>; 5663 hysteresis = <2000>; 5664 type = "passive"; 5665 }; 5666 5667 cpu7_crit: cpu-crit { 5668 temperature = <110000>; 5669 hysteresis = <0>; 5670 type = "critical"; 5671 }; 5672 }; 5673 5674 cooling-maps { 5675 map0 { 5676 trip = <&cpu7_alert0>; 5677 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5678 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5679 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5680 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5681 }; 5682 map1 { 5683 trip = <&cpu7_alert1>; 5684 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5686 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5687 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5688 }; 5689 }; 5690 }; 5691 5692 cpu8-thermal { 5693 polling-delay-passive = <250>; 5694 polling-delay = <0>; 5695 5696 thermal-sensors = <&tsens0 11>; 5697 5698 trips { 5699 cpu8_alert0: trip-point0 { 5700 temperature = <90000>; 5701 hysteresis = <2000>; 5702 type = "passive"; 5703 }; 5704 5705 cpu8_alert1: trip-point1 { 5706 temperature = <95000>; 5707 hysteresis = <2000>; 5708 type = "passive"; 5709 }; 5710 5711 cpu8_crit: cpu-crit { 5712 temperature = <110000>; 5713 hysteresis = <0>; 5714 type = "critical"; 5715 }; 5716 }; 5717 5718 cooling-maps { 5719 map0 { 5720 trip = <&cpu8_alert0>; 5721 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5722 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5723 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5724 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5725 }; 5726 map1 { 5727 trip = <&cpu8_alert1>; 5728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5732 }; 5733 }; 5734 }; 5735 5736 cpu9-thermal { 5737 polling-delay-passive = <250>; 5738 polling-delay = <0>; 5739 5740 thermal-sensors = <&tsens0 12>; 5741 5742 trips { 5743 cpu9_alert0: trip-point0 { 5744 temperature = <90000>; 5745 hysteresis = <2000>; 5746 type = "passive"; 5747 }; 5748 5749 cpu9_alert1: trip-point1 { 5750 temperature = <95000>; 5751 hysteresis = <2000>; 5752 type = "passive"; 5753 }; 5754 5755 cpu9_crit: cpu-crit { 5756 temperature = <110000>; 5757 hysteresis = <0>; 5758 type = "critical"; 5759 }; 5760 }; 5761 5762 cooling-maps { 5763 map0 { 5764 trip = <&cpu9_alert0>; 5765 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5767 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5768 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5769 }; 5770 map1 { 5771 trip = <&cpu9_alert1>; 5772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5776 }; 5777 }; 5778 }; 5779 5780 cpu10-thermal { 5781 polling-delay-passive = <250>; 5782 polling-delay = <0>; 5783 5784 thermal-sensors = <&tsens0 13>; 5785 5786 trips { 5787 cpu10_alert0: trip-point0 { 5788 temperature = <90000>; 5789 hysteresis = <2000>; 5790 type = "passive"; 5791 }; 5792 5793 cpu10_alert1: trip-point1 { 5794 temperature = <95000>; 5795 hysteresis = <2000>; 5796 type = "passive"; 5797 }; 5798 5799 cpu10_crit: cpu-crit { 5800 temperature = <110000>; 5801 hysteresis = <0>; 5802 type = "critical"; 5803 }; 5804 }; 5805 5806 cooling-maps { 5807 map0 { 5808 trip = <&cpu10_alert0>; 5809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5813 }; 5814 map1 { 5815 trip = <&cpu10_alert1>; 5816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5820 }; 5821 }; 5822 }; 5823 5824 cpu11-thermal { 5825 polling-delay-passive = <250>; 5826 polling-delay = <0>; 5827 5828 thermal-sensors = <&tsens0 14>; 5829 5830 trips { 5831 cpu11_alert0: trip-point0 { 5832 temperature = <90000>; 5833 hysteresis = <2000>; 5834 type = "passive"; 5835 }; 5836 5837 cpu11_alert1: trip-point1 { 5838 temperature = <95000>; 5839 hysteresis = <2000>; 5840 type = "passive"; 5841 }; 5842 5843 cpu11_crit: cpu-crit { 5844 temperature = <110000>; 5845 hysteresis = <0>; 5846 type = "critical"; 5847 }; 5848 }; 5849 5850 cooling-maps { 5851 map0 { 5852 trip = <&cpu11_alert0>; 5853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5855 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5856 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5857 }; 5858 map1 { 5859 trip = <&cpu11_alert1>; 5860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5864 }; 5865 }; 5866 }; 5867 5868 aoss0-thermal { 5869 polling-delay-passive = <0>; 5870 polling-delay = <0>; 5871 5872 thermal-sensors = <&tsens0 0>; 5873 5874 trips { 5875 aoss0_alert0: trip-point0 { 5876 temperature = <90000>; 5877 hysteresis = <2000>; 5878 type = "hot"; 5879 }; 5880 5881 aoss0_crit: aoss0-crit { 5882 temperature = <110000>; 5883 hysteresis = <0>; 5884 type = "critical"; 5885 }; 5886 }; 5887 }; 5888 5889 aoss1-thermal { 5890 polling-delay-passive = <0>; 5891 polling-delay = <0>; 5892 5893 thermal-sensors = <&tsens1 0>; 5894 5895 trips { 5896 aoss1_alert0: trip-point0 { 5897 temperature = <90000>; 5898 hysteresis = <2000>; 5899 type = "hot"; 5900 }; 5901 5902 aoss1_crit: aoss1-crit { 5903 temperature = <110000>; 5904 hysteresis = <0>; 5905 type = "critical"; 5906 }; 5907 }; 5908 }; 5909 5910 cpuss0-thermal { 5911 polling-delay-passive = <0>; 5912 polling-delay = <0>; 5913 5914 thermal-sensors = <&tsens0 5>; 5915 5916 trips { 5917 cpuss0_alert0: trip-point0 { 5918 temperature = <90000>; 5919 hysteresis = <2000>; 5920 type = "hot"; 5921 }; 5922 cpuss0_crit: cluster0-crit { 5923 temperature = <110000>; 5924 hysteresis = <0>; 5925 type = "critical"; 5926 }; 5927 }; 5928 }; 5929 5930 cpuss1-thermal { 5931 polling-delay-passive = <0>; 5932 polling-delay = <0>; 5933 5934 thermal-sensors = <&tsens0 6>; 5935 5936 trips { 5937 cpuss1_alert0: trip-point0 { 5938 temperature = <90000>; 5939 hysteresis = <2000>; 5940 type = "hot"; 5941 }; 5942 cpuss1_crit: cluster0-crit { 5943 temperature = <110000>; 5944 hysteresis = <0>; 5945 type = "critical"; 5946 }; 5947 }; 5948 }; 5949 5950 gpuss0-thermal { 5951 polling-delay-passive = <100>; 5952 polling-delay = <0>; 5953 5954 thermal-sensors = <&tsens1 1>; 5955 5956 trips { 5957 gpuss0_alert0: trip-point0 { 5958 temperature = <95000>; 5959 hysteresis = <2000>; 5960 type = "passive"; 5961 }; 5962 5963 gpuss0_crit: gpuss0-crit { 5964 temperature = <110000>; 5965 hysteresis = <0>; 5966 type = "critical"; 5967 }; 5968 }; 5969 5970 cooling-maps { 5971 map0 { 5972 trip = <&gpuss0_alert0>; 5973 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5974 }; 5975 }; 5976 }; 5977 5978 gpuss1-thermal { 5979 polling-delay-passive = <100>; 5980 polling-delay = <0>; 5981 5982 thermal-sensors = <&tsens1 2>; 5983 5984 trips { 5985 gpuss1_alert0: trip-point0 { 5986 temperature = <95000>; 5987 hysteresis = <2000>; 5988 type = "passive"; 5989 }; 5990 5991 gpuss1_crit: gpuss1-crit { 5992 temperature = <110000>; 5993 hysteresis = <0>; 5994 type = "critical"; 5995 }; 5996 }; 5997 5998 cooling-maps { 5999 map0 { 6000 trip = <&gpuss1_alert0>; 6001 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6002 }; 6003 }; 6004 }; 6005 6006 nspss0-thermal { 6007 polling-delay-passive = <0>; 6008 polling-delay = <0>; 6009 6010 thermal-sensors = <&tsens1 3>; 6011 6012 trips { 6013 nspss0_alert0: trip-point0 { 6014 temperature = <90000>; 6015 hysteresis = <2000>; 6016 type = "hot"; 6017 }; 6018 6019 nspss0_crit: nspss0-crit { 6020 temperature = <110000>; 6021 hysteresis = <0>; 6022 type = "critical"; 6023 }; 6024 }; 6025 }; 6026 6027 nspss1-thermal { 6028 polling-delay-passive = <0>; 6029 polling-delay = <0>; 6030 6031 thermal-sensors = <&tsens1 4>; 6032 6033 trips { 6034 nspss1_alert0: trip-point0 { 6035 temperature = <90000>; 6036 hysteresis = <2000>; 6037 type = "hot"; 6038 }; 6039 6040 nspss1_crit: nspss1-crit { 6041 temperature = <110000>; 6042 hysteresis = <0>; 6043 type = "critical"; 6044 }; 6045 }; 6046 }; 6047 6048 video-thermal { 6049 polling-delay-passive = <0>; 6050 polling-delay = <0>; 6051 6052 thermal-sensors = <&tsens1 5>; 6053 6054 trips { 6055 video_alert0: trip-point0 { 6056 temperature = <90000>; 6057 hysteresis = <2000>; 6058 type = "hot"; 6059 }; 6060 6061 video_crit: video-crit { 6062 temperature = <110000>; 6063 hysteresis = <0>; 6064 type = "critical"; 6065 }; 6066 }; 6067 }; 6068 6069 ddr-thermal { 6070 polling-delay-passive = <0>; 6071 polling-delay = <0>; 6072 6073 thermal-sensors = <&tsens1 6>; 6074 6075 trips { 6076 ddr_alert0: trip-point0 { 6077 temperature = <90000>; 6078 hysteresis = <2000>; 6079 type = "hot"; 6080 }; 6081 6082 ddr_crit: ddr-crit { 6083 temperature = <110000>; 6084 hysteresis = <0>; 6085 type = "critical"; 6086 }; 6087 }; 6088 }; 6089 6090 mdmss0-thermal { 6091 polling-delay-passive = <0>; 6092 polling-delay = <0>; 6093 6094 thermal-sensors = <&tsens1 7>; 6095 6096 trips { 6097 mdmss0_alert0: trip-point0 { 6098 temperature = <90000>; 6099 hysteresis = <2000>; 6100 type = "hot"; 6101 }; 6102 6103 mdmss0_crit: mdmss0-crit { 6104 temperature = <110000>; 6105 hysteresis = <0>; 6106 type = "critical"; 6107 }; 6108 }; 6109 }; 6110 6111 mdmss1-thermal { 6112 polling-delay-passive = <0>; 6113 polling-delay = <0>; 6114 6115 thermal-sensors = <&tsens1 8>; 6116 6117 trips { 6118 mdmss1_alert0: trip-point0 { 6119 temperature = <90000>; 6120 hysteresis = <2000>; 6121 type = "hot"; 6122 }; 6123 6124 mdmss1_crit: mdmss1-crit { 6125 temperature = <110000>; 6126 hysteresis = <0>; 6127 type = "critical"; 6128 }; 6129 }; 6130 }; 6131 6132 mdmss2-thermal { 6133 polling-delay-passive = <0>; 6134 polling-delay = <0>; 6135 6136 thermal-sensors = <&tsens1 9>; 6137 6138 trips { 6139 mdmss2_alert0: trip-point0 { 6140 temperature = <90000>; 6141 hysteresis = <2000>; 6142 type = "hot"; 6143 }; 6144 6145 mdmss2_crit: mdmss2-crit { 6146 temperature = <110000>; 6147 hysteresis = <0>; 6148 type = "critical"; 6149 }; 6150 }; 6151 }; 6152 6153 mdmss3-thermal { 6154 polling-delay-passive = <0>; 6155 polling-delay = <0>; 6156 6157 thermal-sensors = <&tsens1 10>; 6158 6159 trips { 6160 mdmss3_alert0: trip-point0 { 6161 temperature = <90000>; 6162 hysteresis = <2000>; 6163 type = "hot"; 6164 }; 6165 6166 mdmss3_crit: mdmss3-crit { 6167 temperature = <110000>; 6168 hysteresis = <0>; 6169 type = "critical"; 6170 }; 6171 }; 6172 }; 6173 6174 camera0-thermal { 6175 polling-delay-passive = <0>; 6176 polling-delay = <0>; 6177 6178 thermal-sensors = <&tsens1 11>; 6179 6180 trips { 6181 camera0_alert0: trip-point0 { 6182 temperature = <90000>; 6183 hysteresis = <2000>; 6184 type = "hot"; 6185 }; 6186 6187 camera0_crit: camera0-crit { 6188 temperature = <110000>; 6189 hysteresis = <0>; 6190 type = "critical"; 6191 }; 6192 }; 6193 }; 6194 }; 6195 6196 timer { 6197 compatible = "arm,armv8-timer"; 6198 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6199 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6200 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6201 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6202 }; 6203}; 6204