1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7280.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/mailbox/qcom-ipcc.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,lpass.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 aliases { 37 i2c0 = &i2c0; 38 i2c1 = &i2c1; 39 i2c2 = &i2c2; 40 i2c3 = &i2c3; 41 i2c4 = &i2c4; 42 i2c5 = &i2c5; 43 i2c6 = &i2c6; 44 i2c7 = &i2c7; 45 i2c8 = &i2c8; 46 i2c9 = &i2c9; 47 i2c10 = &i2c10; 48 i2c11 = &i2c11; 49 i2c12 = &i2c12; 50 i2c13 = &i2c13; 51 i2c14 = &i2c14; 52 i2c15 = &i2c15; 53 mmc1 = &sdhc_1; 54 mmc2 = &sdhc_2; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 }; 72 73 clocks { 74 xo_board: xo-board { 75 compatible = "fixed-clock"; 76 clock-frequency = <76800000>; 77 #clock-cells = <0>; 78 }; 79 80 sleep_clk: sleep-clk { 81 compatible = "fixed-clock"; 82 clock-frequency = <32000>; 83 #clock-cells = <0>; 84 }; 85 }; 86 87 reserved-memory { 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges; 91 92 wlan_ce_mem: memory@4cd000 { 93 no-map; 94 reg = <0x0 0x004cd000 0x0 0x1000>; 95 }; 96 97 hyp_mem: memory@80000000 { 98 reg = <0x0 0x80000000 0x0 0x600000>; 99 no-map; 100 }; 101 102 xbl_mem: memory@80600000 { 103 reg = <0x0 0x80600000 0x0 0x200000>; 104 no-map; 105 }; 106 107 aop_mem: memory@80800000 { 108 reg = <0x0 0x80800000 0x0 0x60000>; 109 no-map; 110 }; 111 112 aop_cmd_db_mem: memory@80860000 { 113 reg = <0x0 0x80860000 0x0 0x20000>; 114 compatible = "qcom,cmd-db"; 115 no-map; 116 }; 117 118 reserved_xbl_uefi_log: memory@80880000 { 119 reg = <0x0 0x80884000 0x0 0x10000>; 120 no-map; 121 }; 122 123 sec_apps_mem: memory@808ff000 { 124 reg = <0x0 0x808ff000 0x0 0x1000>; 125 no-map; 126 }; 127 128 smem_mem: memory@80900000 { 129 reg = <0x0 0x80900000 0x0 0x200000>; 130 no-map; 131 }; 132 133 cpucp_mem: memory@80b00000 { 134 no-map; 135 reg = <0x0 0x80b00000 0x0 0x100000>; 136 }; 137 138 wlan_fw_mem: memory@80c00000 { 139 reg = <0x0 0x80c00000 0x0 0xc00000>; 140 no-map; 141 }; 142 143 video_mem: memory@8b200000 { 144 reg = <0x0 0x8b200000 0x0 0x500000>; 145 no-map; 146 }; 147 148 ipa_fw_mem: memory@8b700000 { 149 reg = <0 0x8b700000 0 0x10000>; 150 no-map; 151 }; 152 153 rmtfs_mem: memory@9c900000 { 154 compatible = "qcom,rmtfs-mem"; 155 reg = <0x0 0x9c900000 0x0 0x280000>; 156 no-map; 157 158 qcom,client-id = <1>; 159 qcom,vmid = <15>; 160 }; 161 }; 162 163 cpus { 164 #address-cells = <2>; 165 #size-cells = <0>; 166 167 CPU0: cpu@0 { 168 device_type = "cpu"; 169 compatible = "arm,kryo"; 170 reg = <0x0 0x0>; 171 enable-method = "psci"; 172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 173 &LITTLE_CPU_SLEEP_1 174 &CLUSTER_SLEEP_0>; 175 next-level-cache = <&L2_0>; 176 operating-points-v2 = <&cpu0_opp_table>; 177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 179 qcom,freq-domain = <&cpufreq_hw 0>; 180 #cooling-cells = <2>; 181 L2_0: l2-cache { 182 compatible = "cache"; 183 next-level-cache = <&L3_0>; 184 L3_0: l3-cache { 185 compatible = "cache"; 186 }; 187 }; 188 }; 189 190 CPU1: cpu@100 { 191 device_type = "cpu"; 192 compatible = "arm,kryo"; 193 reg = <0x0 0x100>; 194 enable-method = "psci"; 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 196 &LITTLE_CPU_SLEEP_1 197 &CLUSTER_SLEEP_0>; 198 next-level-cache = <&L2_100>; 199 operating-points-v2 = <&cpu0_opp_table>; 200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 202 qcom,freq-domain = <&cpufreq_hw 0>; 203 #cooling-cells = <2>; 204 L2_100: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU2: cpu@200 { 211 device_type = "cpu"; 212 compatible = "arm,kryo"; 213 reg = <0x0 0x200>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 next-level-cache = <&L2_200>; 219 operating-points-v2 = <&cpu0_opp_table>; 220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 222 qcom,freq-domain = <&cpufreq_hw 0>; 223 #cooling-cells = <2>; 224 L2_200: l2-cache { 225 compatible = "cache"; 226 next-level-cache = <&L3_0>; 227 }; 228 }; 229 230 CPU3: cpu@300 { 231 device_type = "cpu"; 232 compatible = "arm,kryo"; 233 reg = <0x0 0x300>; 234 enable-method = "psci"; 235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 236 &LITTLE_CPU_SLEEP_1 237 &CLUSTER_SLEEP_0>; 238 next-level-cache = <&L2_300>; 239 operating-points-v2 = <&cpu0_opp_table>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 L2_300: l2-cache { 245 compatible = "cache"; 246 next-level-cache = <&L3_0>; 247 }; 248 }; 249 250 CPU4: cpu@400 { 251 device_type = "cpu"; 252 compatible = "arm,kryo"; 253 reg = <0x0 0x400>; 254 enable-method = "psci"; 255 cpu-idle-states = <&BIG_CPU_SLEEP_0 256 &BIG_CPU_SLEEP_1 257 &CLUSTER_SLEEP_0>; 258 next-level-cache = <&L2_400>; 259 operating-points-v2 = <&cpu4_opp_table>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 1>; 263 #cooling-cells = <2>; 264 L2_400: l2-cache { 265 compatible = "cache"; 266 next-level-cache = <&L3_0>; 267 }; 268 }; 269 270 CPU5: cpu@500 { 271 device_type = "cpu"; 272 compatible = "arm,kryo"; 273 reg = <0x0 0x500>; 274 enable-method = "psci"; 275 cpu-idle-states = <&BIG_CPU_SLEEP_0 276 &BIG_CPU_SLEEP_1 277 &CLUSTER_SLEEP_0>; 278 next-level-cache = <&L2_500>; 279 operating-points-v2 = <&cpu4_opp_table>; 280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 282 qcom,freq-domain = <&cpufreq_hw 1>; 283 #cooling-cells = <2>; 284 L2_500: l2-cache { 285 compatible = "cache"; 286 next-level-cache = <&L3_0>; 287 }; 288 }; 289 290 CPU6: cpu@600 { 291 device_type = "cpu"; 292 compatible = "arm,kryo"; 293 reg = <0x0 0x600>; 294 enable-method = "psci"; 295 cpu-idle-states = <&BIG_CPU_SLEEP_0 296 &BIG_CPU_SLEEP_1 297 &CLUSTER_SLEEP_0>; 298 next-level-cache = <&L2_600>; 299 operating-points-v2 = <&cpu4_opp_table>; 300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 302 qcom,freq-domain = <&cpufreq_hw 1>; 303 #cooling-cells = <2>; 304 L2_600: l2-cache { 305 compatible = "cache"; 306 next-level-cache = <&L3_0>; 307 }; 308 }; 309 310 CPU7: cpu@700 { 311 device_type = "cpu"; 312 compatible = "arm,kryo"; 313 reg = <0x0 0x700>; 314 enable-method = "psci"; 315 cpu-idle-states = <&BIG_CPU_SLEEP_0 316 &BIG_CPU_SLEEP_1 317 &CLUSTER_SLEEP_0>; 318 next-level-cache = <&L2_700>; 319 operating-points-v2 = <&cpu7_opp_table>; 320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 322 qcom,freq-domain = <&cpufreq_hw 2>; 323 #cooling-cells = <2>; 324 L2_700: l2-cache { 325 compatible = "cache"; 326 next-level-cache = <&L3_0>; 327 }; 328 }; 329 330 cpu-map { 331 cluster0 { 332 core0 { 333 cpu = <&CPU0>; 334 }; 335 336 core1 { 337 cpu = <&CPU1>; 338 }; 339 340 core2 { 341 cpu = <&CPU2>; 342 }; 343 344 core3 { 345 cpu = <&CPU3>; 346 }; 347 348 core4 { 349 cpu = <&CPU4>; 350 }; 351 352 core5 { 353 cpu = <&CPU5>; 354 }; 355 356 core6 { 357 cpu = <&CPU6>; 358 }; 359 360 core7 { 361 cpu = <&CPU7>; 362 }; 363 }; 364 }; 365 366 idle-states { 367 entry-method = "psci"; 368 369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 370 compatible = "arm,idle-state"; 371 idle-state-name = "little-power-down"; 372 arm,psci-suspend-param = <0x40000003>; 373 entry-latency-us = <549>; 374 exit-latency-us = <901>; 375 min-residency-us = <1774>; 376 local-timer-stop; 377 }; 378 379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 380 compatible = "arm,idle-state"; 381 idle-state-name = "little-rail-power-down"; 382 arm,psci-suspend-param = <0x40000004>; 383 entry-latency-us = <702>; 384 exit-latency-us = <915>; 385 min-residency-us = <4001>; 386 local-timer-stop; 387 }; 388 389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "big-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <523>; 394 exit-latency-us = <1244>; 395 min-residency-us = <2207>; 396 local-timer-stop; 397 }; 398 399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "big-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <526>; 404 exit-latency-us = <1854>; 405 min-residency-us = <5555>; 406 local-timer-stop; 407 }; 408 409 CLUSTER_SLEEP_0: cluster-sleep-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "cluster-power-down"; 412 arm,psci-suspend-param = <0x40003444>; 413 entry-latency-us = <3263>; 414 exit-latency-us = <6562>; 415 min-residency-us = <9926>; 416 local-timer-stop; 417 }; 418 }; 419 }; 420 421 cpu0_opp_table: opp-table-cpu0 { 422 compatible = "operating-points-v2"; 423 opp-shared; 424 425 cpu0_opp_300mhz: opp-300000000 { 426 opp-hz = /bits/ 64 <300000000>; 427 opp-peak-kBps = <800000 9600000>; 428 }; 429 430 cpu0_opp_691mhz: opp-691200000 { 431 opp-hz = /bits/ 64 <691200000>; 432 opp-peak-kBps = <800000 17817600>; 433 }; 434 435 cpu0_opp_806mhz: opp-806400000 { 436 opp-hz = /bits/ 64 <806400000>; 437 opp-peak-kBps = <800000 20889600>; 438 }; 439 440 cpu0_opp_941mhz: opp-940800000 { 441 opp-hz = /bits/ 64 <940800000>; 442 opp-peak-kBps = <1804000 24576000>; 443 }; 444 445 cpu0_opp_1152mhz: opp-1152000000 { 446 opp-hz = /bits/ 64 <1152000000>; 447 opp-peak-kBps = <2188000 27033600>; 448 }; 449 450 cpu0_opp_1325mhz: opp-1324800000 { 451 opp-hz = /bits/ 64 <1324800000>; 452 opp-peak-kBps = <2188000 33792000>; 453 }; 454 455 cpu0_opp_1517mhz: opp-1516800000 { 456 opp-hz = /bits/ 64 <1516800000>; 457 opp-peak-kBps = <3072000 38092800>; 458 }; 459 460 cpu0_opp_1651mhz: opp-1651200000 { 461 opp-hz = /bits/ 64 <1651200000>; 462 opp-peak-kBps = <3072000 41779200>; 463 }; 464 465 cpu0_opp_1805mhz: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 48537600>; 468 }; 469 470 cpu0_opp_1958mhz: opp-1958400000 { 471 opp-hz = /bits/ 64 <1958400000>; 472 opp-peak-kBps = <4068000 48537600>; 473 }; 474 475 cpu0_opp_2016mhz: opp-2016000000 { 476 opp-hz = /bits/ 64 <2016000000>; 477 opp-peak-kBps = <6220000 48537600>; 478 }; 479 }; 480 481 cpu4_opp_table: opp-table-cpu4 { 482 compatible = "operating-points-v2"; 483 opp-shared; 484 485 cpu4_opp_691mhz: opp-691200000 { 486 opp-hz = /bits/ 64 <691200000>; 487 opp-peak-kBps = <1804000 9600000>; 488 }; 489 490 cpu4_opp_941mhz: opp-940800000 { 491 opp-hz = /bits/ 64 <940800000>; 492 opp-peak-kBps = <2188000 17817600>; 493 }; 494 495 cpu4_opp_1229mhz: opp-1228800000 { 496 opp-hz = /bits/ 64 <1228800000>; 497 opp-peak-kBps = <4068000 24576000>; 498 }; 499 500 cpu4_opp_1344mhz: opp-1344000000 { 501 opp-hz = /bits/ 64 <1344000000>; 502 opp-peak-kBps = <4068000 24576000>; 503 }; 504 505 cpu4_opp_1517mhz: opp-1516800000 { 506 opp-hz = /bits/ 64 <1516800000>; 507 opp-peak-kBps = <4068000 24576000>; 508 }; 509 510 cpu4_opp_1651mhz: opp-1651200000 { 511 opp-hz = /bits/ 64 <1651200000>; 512 opp-peak-kBps = <6220000 38092800>; 513 }; 514 515 cpu4_opp_1901mhz: opp-1900800000 { 516 opp-hz = /bits/ 64 <1900800000>; 517 opp-peak-kBps = <6220000 44851200>; 518 }; 519 520 cpu4_opp_2054mhz: opp-2054400000 { 521 opp-hz = /bits/ 64 <2054400000>; 522 opp-peak-kBps = <6220000 44851200>; 523 }; 524 525 cpu4_opp_2112mhz: opp-2112000000 { 526 opp-hz = /bits/ 64 <2112000000>; 527 opp-peak-kBps = <6220000 44851200>; 528 }; 529 530 cpu4_opp_2131mhz: opp-2131200000 { 531 opp-hz = /bits/ 64 <2131200000>; 532 opp-peak-kBps = <6220000 44851200>; 533 }; 534 535 cpu4_opp_2208mhz: opp-2208000000 { 536 opp-hz = /bits/ 64 <2208000000>; 537 opp-peak-kBps = <6220000 44851200>; 538 }; 539 540 cpu4_opp_2400mhz: opp-2400000000 { 541 opp-hz = /bits/ 64 <2400000000>; 542 opp-peak-kBps = <8532000 48537600>; 543 }; 544 545 cpu4_opp_2611mhz: opp-2611200000 { 546 opp-hz = /bits/ 64 <2611200000>; 547 opp-peak-kBps = <8532000 48537600>; 548 }; 549 }; 550 551 cpu7_opp_table: opp-table-cpu7 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 cpu7_opp_806mhz: opp-806400000 { 556 opp-hz = /bits/ 64 <806400000>; 557 opp-peak-kBps = <1804000 9600000>; 558 }; 559 560 cpu7_opp_1056mhz: opp-1056000000 { 561 opp-hz = /bits/ 64 <1056000000>; 562 opp-peak-kBps = <2188000 17817600>; 563 }; 564 565 cpu7_opp_1325mhz: opp-1324800000 { 566 opp-hz = /bits/ 64 <1324800000>; 567 opp-peak-kBps = <4068000 24576000>; 568 }; 569 570 cpu7_opp_1517mhz: opp-1516800000 { 571 opp-hz = /bits/ 64 <1516800000>; 572 opp-peak-kBps = <4068000 24576000>; 573 }; 574 575 cpu7_opp_1766mhz: opp-1766400000 { 576 opp-hz = /bits/ 64 <1766400000>; 577 opp-peak-kBps = <6220000 38092800>; 578 }; 579 580 cpu7_opp_1862mhz: opp-1862400000 { 581 opp-hz = /bits/ 64 <1862400000>; 582 opp-peak-kBps = <6220000 38092800>; 583 }; 584 585 cpu7_opp_2035mhz: opp-2035200000 { 586 opp-hz = /bits/ 64 <2035200000>; 587 opp-peak-kBps = <6220000 38092800>; 588 }; 589 590 cpu7_opp_2112mhz: opp-2112000000 { 591 opp-hz = /bits/ 64 <2112000000>; 592 opp-peak-kBps = <6220000 44851200>; 593 }; 594 595 cpu7_opp_2208mhz: opp-2208000000 { 596 opp-hz = /bits/ 64 <2208000000>; 597 opp-peak-kBps = <6220000 44851200>; 598 }; 599 600 cpu7_opp_2381mhz: opp-2380800000 { 601 opp-hz = /bits/ 64 <2380800000>; 602 opp-peak-kBps = <6832000 44851200>; 603 }; 604 605 cpu7_opp_2400mhz: opp-2400000000 { 606 opp-hz = /bits/ 64 <2400000000>; 607 opp-peak-kBps = <8532000 48537600>; 608 }; 609 610 cpu7_opp_2515mhz: opp-2515200000 { 611 opp-hz = /bits/ 64 <2515200000>; 612 opp-peak-kBps = <8532000 48537600>; 613 }; 614 615 cpu7_opp_2707mhz: opp-2707200000 { 616 opp-hz = /bits/ 64 <2707200000>; 617 opp-peak-kBps = <8532000 48537600>; 618 }; 619 620 cpu7_opp_3014mhz: opp-3014400000 { 621 opp-hz = /bits/ 64 <3014400000>; 622 opp-peak-kBps = <8532000 48537600>; 623 }; 624 }; 625 626 memory@80000000 { 627 device_type = "memory"; 628 /* We expect the bootloader to fill in the size */ 629 reg = <0 0x80000000 0 0>; 630 }; 631 632 firmware { 633 scm { 634 compatible = "qcom,scm-sc7280", "qcom,scm"; 635 }; 636 }; 637 638 clk_virt: interconnect { 639 compatible = "qcom,sc7280-clk-virt"; 640 #interconnect-cells = <2>; 641 qcom,bcm-voters = <&apps_bcm_voter>; 642 }; 643 644 smem { 645 compatible = "qcom,smem"; 646 memory-region = <&smem_mem>; 647 hwlocks = <&tcsr_mutex 3>; 648 }; 649 650 smp2p-adsp { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <443>, <429>; 653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 654 IPCC_MPROC_SIGNAL_SMP2P 655 IRQ_TYPE_EDGE_RISING>; 656 mboxes = <&ipcc IPCC_CLIENT_LPASS 657 IPCC_MPROC_SIGNAL_SMP2P>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <2>; 661 662 adsp_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 adsp_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 smp2p-cdsp { 675 compatible = "qcom,smp2p"; 676 qcom,smem = <94>, <432>; 677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 678 IPCC_MPROC_SIGNAL_SMP2P 679 IRQ_TYPE_EDGE_RISING>; 680 mboxes = <&ipcc IPCC_CLIENT_CDSP 681 IPCC_MPROC_SIGNAL_SMP2P>; 682 683 qcom,local-pid = <0>; 684 qcom,remote-pid = <5>; 685 686 cdsp_smp2p_out: master-kernel { 687 qcom,entry-name = "master-kernel"; 688 #qcom,smem-state-cells = <1>; 689 }; 690 691 cdsp_smp2p_in: slave-kernel { 692 qcom,entry-name = "slave-kernel"; 693 interrupt-controller; 694 #interrupt-cells = <2>; 695 }; 696 }; 697 698 smp2p-mpss { 699 compatible = "qcom,smp2p"; 700 qcom,smem = <435>, <428>; 701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 702 IPCC_MPROC_SIGNAL_SMP2P 703 IRQ_TYPE_EDGE_RISING>; 704 mboxes = <&ipcc IPCC_CLIENT_MPSS 705 IPCC_MPROC_SIGNAL_SMP2P>; 706 707 qcom,local-pid = <0>; 708 qcom,remote-pid = <1>; 709 710 modem_smp2p_out: master-kernel { 711 qcom,entry-name = "master-kernel"; 712 #qcom,smem-state-cells = <1>; 713 }; 714 715 modem_smp2p_in: slave-kernel { 716 qcom,entry-name = "slave-kernel"; 717 interrupt-controller; 718 #interrupt-cells = <2>; 719 }; 720 721 ipa_smp2p_out: ipa-ap-to-modem { 722 qcom,entry-name = "ipa"; 723 #qcom,smem-state-cells = <1>; 724 }; 725 726 ipa_smp2p_in: ipa-modem-to-ap { 727 qcom,entry-name = "ipa"; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 }; 732 733 smp2p-wpss { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <617>, <616>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_WPSS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <13>; 744 745 wpss_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 wpss_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 pmu { 758 compatible = "arm,armv8-pmuv3"; 759 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 760 }; 761 762 psci { 763 compatible = "arm,psci-1.0"; 764 method = "smc"; 765 }; 766 767 qspi_opp_table: opp-table-qspi { 768 compatible = "operating-points-v2"; 769 770 opp-75000000 { 771 opp-hz = /bits/ 64 <75000000>; 772 required-opps = <&rpmhpd_opp_low_svs>; 773 }; 774 775 opp-150000000 { 776 opp-hz = /bits/ 64 <150000000>; 777 required-opps = <&rpmhpd_opp_svs>; 778 }; 779 780 opp-200000000 { 781 opp-hz = /bits/ 64 <200000000>; 782 required-opps = <&rpmhpd_opp_svs_l1>; 783 }; 784 785 opp-300000000 { 786 opp-hz = /bits/ 64 <300000000>; 787 required-opps = <&rpmhpd_opp_nom>; 788 }; 789 }; 790 791 qup_opp_table: opp-table-qup { 792 compatible = "operating-points-v2"; 793 794 opp-75000000 { 795 opp-hz = /bits/ 64 <75000000>; 796 required-opps = <&rpmhpd_opp_low_svs>; 797 }; 798 799 opp-100000000 { 800 opp-hz = /bits/ 64 <100000000>; 801 required-opps = <&rpmhpd_opp_svs>; 802 }; 803 804 opp-128000000 { 805 opp-hz = /bits/ 64 <128000000>; 806 required-opps = <&rpmhpd_opp_nom>; 807 }; 808 }; 809 810 soc: soc@0 { 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges = <0 0 0 0 0x10 0>; 814 dma-ranges = <0 0 0 0 0x10 0>; 815 compatible = "simple-bus"; 816 817 gcc: clock-controller@100000 { 818 compatible = "qcom,gcc-sc7280"; 819 reg = <0 0x00100000 0 0x1f0000>; 820 clocks = <&rpmhcc RPMH_CXO_CLK>, 821 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 822 <0>, <&pcie1_lane>, 823 <0>, <0>, <0>, <0>; 824 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 825 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 826 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 827 "ufs_phy_tx_symbol_0_clk", 828 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 power-domains = <&rpmhpd SC7280_CX>; 833 }; 834 835 ipcc: mailbox@408000 { 836 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 837 reg = <0 0x00408000 0 0x1000>; 838 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-controller; 840 #interrupt-cells = <3>; 841 #mbox-cells = <2>; 842 }; 843 844 qfprom: efuse@784000 { 845 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 846 reg = <0 0x00784000 0 0xa20>, 847 <0 0x00780000 0 0xa20>, 848 <0 0x00782000 0 0x120>, 849 <0 0x00786000 0 0x1fff>; 850 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 851 clock-names = "core"; 852 power-domains = <&rpmhpd SC7280_MX>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 856 gpu_speed_bin: gpu_speed_bin@1e9 { 857 reg = <0x1e9 0x2>; 858 bits = <5 8>; 859 }; 860 }; 861 862 sdhc_1: mmc@7c4000 { 863 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 864 pinctrl-names = "default", "sleep"; 865 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 866 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 867 status = "disabled"; 868 869 reg = <0 0x007c4000 0 0x1000>, 870 <0 0x007c5000 0 0x1000>; 871 reg-names = "hc", "cqhci"; 872 873 iommus = <&apps_smmu 0xc0 0x0>; 874 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "hc_irq", "pwr_irq"; 877 878 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 879 <&gcc GCC_SDCC1_APPS_CLK>, 880 <&rpmhcc RPMH_CXO_CLK>; 881 clock-names = "iface", "core", "xo"; 882 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 883 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 884 interconnect-names = "sdhc-ddr","cpu-sdhc"; 885 power-domains = <&rpmhpd SC7280_CX>; 886 operating-points-v2 = <&sdhc1_opp_table>; 887 888 bus-width = <8>; 889 supports-cqe; 890 891 qcom,dll-config = <0x0007642c>; 892 qcom,ddr-config = <0x80040868>; 893 894 mmc-ddr-1_8v; 895 mmc-hs200-1_8v; 896 mmc-hs400-1_8v; 897 mmc-hs400-enhanced-strobe; 898 899 resets = <&gcc GCC_SDCC1_BCR>; 900 901 sdhc1_opp_table: opp-table { 902 compatible = "operating-points-v2"; 903 904 opp-100000000 { 905 opp-hz = /bits/ 64 <100000000>; 906 required-opps = <&rpmhpd_opp_low_svs>; 907 opp-peak-kBps = <1800000 400000>; 908 opp-avg-kBps = <100000 0>; 909 }; 910 911 opp-384000000 { 912 opp-hz = /bits/ 64 <384000000>; 913 required-opps = <&rpmhpd_opp_nom>; 914 opp-peak-kBps = <5400000 1600000>; 915 opp-avg-kBps = <390000 0>; 916 }; 917 }; 918 919 }; 920 921 gpi_dma0: dma-controller@900000 { 922 #dma-cells = <3>; 923 compatible = "qcom,sc7280-gpi-dma"; 924 reg = <0 0x00900000 0 0x60000>; 925 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 937 dma-channels = <12>; 938 dma-channel-mask = <0x7f>; 939 iommus = <&apps_smmu 0x0136 0x0>; 940 status = "disabled"; 941 }; 942 943 qupv3_id_0: geniqup@9c0000 { 944 compatible = "qcom,geni-se-qup"; 945 reg = <0 0x009c0000 0 0x2000>; 946 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 947 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 948 clock-names = "m-ahb", "s-ahb"; 949 #address-cells = <2>; 950 #size-cells = <2>; 951 ranges; 952 iommus = <&apps_smmu 0x123 0x0>; 953 status = "disabled"; 954 955 i2c0: i2c@980000 { 956 compatible = "qcom,geni-i2c"; 957 reg = <0 0x00980000 0 0x4000>; 958 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 959 clock-names = "se"; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&qup_i2c0_data_clk>; 962 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 963 #address-cells = <1>; 964 #size-cells = <0>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 967 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", 969 "qup-memory"; 970 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 971 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 972 dma-names = "tx", "rx"; 973 status = "disabled"; 974 }; 975 976 spi0: spi@980000 { 977 compatible = "qcom,geni-spi"; 978 reg = <0 0x00980000 0 0x4000>; 979 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 980 clock-names = "se"; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 983 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 power-domains = <&rpmhpd SC7280_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 992 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 993 dma-names = "tx", "rx"; 994 status = "disabled"; 995 }; 996 997 uart0: serial@980000 { 998 compatible = "qcom,geni-uart"; 999 reg = <0 0x00980000 0 0x4000>; 1000 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1001 clock-names = "se"; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1004 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1005 power-domains = <&rpmhpd SC7280_CX>; 1006 operating-points-v2 = <&qup_opp_table>; 1007 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1009 interconnect-names = "qup-core", "qup-config"; 1010 status = "disabled"; 1011 }; 1012 1013 i2c1: i2c@984000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x00984000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017 clock-names = "se"; 1018 pinctrl-names = "default"; 1019 pinctrl-0 = <&qup_i2c1_data_clk>; 1020 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1025 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1026 interconnect-names = "qup-core", "qup-config", 1027 "qup-memory"; 1028 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1029 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 status = "disabled"; 1032 }; 1033 1034 spi1: spi@984000 { 1035 compatible = "qcom,geni-spi"; 1036 reg = <0 0x00984000 0 0x4000>; 1037 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1038 clock-names = "se"; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1041 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 power-domains = <&rpmhpd SC7280_CX>; 1045 operating-points-v2 = <&qup_opp_table>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1048 interconnect-names = "qup-core", "qup-config"; 1049 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1050 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1051 dma-names = "tx", "rx"; 1052 status = "disabled"; 1053 }; 1054 1055 uart1: serial@984000 { 1056 compatible = "qcom,geni-uart"; 1057 reg = <0 0x00984000 0 0x4000>; 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1059 clock-names = "se"; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1062 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1063 power-domains = <&rpmhpd SC7280_CX>; 1064 operating-points-v2 = <&qup_opp_table>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c2: i2c@988000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x00988000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1075 clock-names = "se"; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_i2c2_data_clk>; 1078 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1082 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1083 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1084 interconnect-names = "qup-core", "qup-config", 1085 "qup-memory"; 1086 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1087 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 status = "disabled"; 1090 }; 1091 1092 spi2: spi@988000 { 1093 compatible = "qcom,geni-spi"; 1094 reg = <0 0x00988000 0 0x4000>; 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1096 clock-names = "se"; 1097 pinctrl-names = "default"; 1098 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1099 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 power-domains = <&rpmhpd SC7280_CX>; 1103 operating-points-v2 = <&qup_opp_table>; 1104 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1105 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1106 interconnect-names = "qup-core", "qup-config"; 1107 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1108 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1109 dma-names = "tx", "rx"; 1110 status = "disabled"; 1111 }; 1112 1113 uart2: serial@988000 { 1114 compatible = "qcom,geni-uart"; 1115 reg = <0 0x00988000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1120 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1121 power-domains = <&rpmhpd SC7280_CX>; 1122 operating-points-v2 = <&qup_opp_table>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1125 interconnect-names = "qup-core", "qup-config"; 1126 status = "disabled"; 1127 }; 1128 1129 i2c3: i2c@98c000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0 0x0098c000 0 0x4000>; 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1133 clock-names = "se"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c3_data_clk>; 1136 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1140 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1141 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "qup-core", "qup-config", 1143 "qup-memory"; 1144 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1145 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1146 dma-names = "tx", "rx"; 1147 status = "disabled"; 1148 }; 1149 1150 spi3: spi@98c000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0 0x0098c000 0 0x4000>; 1153 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1154 clock-names = "se"; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1157 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 power-domains = <&rpmhpd SC7280_CX>; 1161 operating-points-v2 = <&qup_opp_table>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1164 interconnect-names = "qup-core", "qup-config"; 1165 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1166 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1167 dma-names = "tx", "rx"; 1168 status = "disabled"; 1169 }; 1170 1171 uart3: serial@98c000 { 1172 compatible = "qcom,geni-uart"; 1173 reg = <0 0x0098c000 0 0x4000>; 1174 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1175 clock-names = "se"; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1178 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1179 power-domains = <&rpmhpd SC7280_CX>; 1180 operating-points-v2 = <&qup_opp_table>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1183 interconnect-names = "qup-core", "qup-config"; 1184 status = "disabled"; 1185 }; 1186 1187 i2c4: i2c@990000 { 1188 compatible = "qcom,geni-i2c"; 1189 reg = <0 0x00990000 0 0x4000>; 1190 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1191 clock-names = "se"; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_i2c4_data_clk>; 1194 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1199 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1200 interconnect-names = "qup-core", "qup-config", 1201 "qup-memory"; 1202 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1203 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1204 dma-names = "tx", "rx"; 1205 status = "disabled"; 1206 }; 1207 1208 spi4: spi@990000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00990000 0 0x4000>; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1212 clock-names = "se"; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1215 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 power-domains = <&rpmhpd SC7280_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1224 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1225 dma-names = "tx", "rx"; 1226 status = "disabled"; 1227 }; 1228 1229 uart4: serial@990000 { 1230 compatible = "qcom,geni-uart"; 1231 reg = <0 0x00990000 0 0x4000>; 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1233 clock-names = "se"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1236 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1237 power-domains = <&rpmhpd SC7280_CX>; 1238 operating-points-v2 = <&qup_opp_table>; 1239 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1240 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1241 interconnect-names = "qup-core", "qup-config"; 1242 status = "disabled"; 1243 }; 1244 1245 i2c5: i2c@994000 { 1246 compatible = "qcom,geni-i2c"; 1247 reg = <0 0x00994000 0 0x4000>; 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1249 clock-names = "se"; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_i2c5_data_clk>; 1252 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1257 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1258 interconnect-names = "qup-core", "qup-config", 1259 "qup-memory"; 1260 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1261 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 spi5: spi@994000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00994000 0 0x4000>; 1269 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1270 clock-names = "se"; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1273 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 power-domains = <&rpmhpd SC7280_CX>; 1277 operating-points-v2 = <&qup_opp_table>; 1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1280 interconnect-names = "qup-core", "qup-config"; 1281 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1282 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1283 dma-names = "tx", "rx"; 1284 status = "disabled"; 1285 }; 1286 1287 uart5: serial@994000 { 1288 compatible = "qcom,geni-uart"; 1289 reg = <0 0x00994000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1291 clock-names = "se"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1294 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 operating-points-v2 = <&qup_opp_table>; 1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c6: i2c@998000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00998000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c6_data_clk>; 1310 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1316 interconnect-names = "qup-core", "qup-config", 1317 "qup-memory"; 1318 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1319 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1320 dma-names = "tx", "rx"; 1321 status = "disabled"; 1322 }; 1323 1324 spi6: spi@998000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0x00998000 0 0x4000>; 1327 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1328 clock-names = "se"; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1331 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 power-domains = <&rpmhpd SC7280_CX>; 1335 operating-points-v2 = <&qup_opp_table>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1340 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1341 dma-names = "tx", "rx"; 1342 status = "disabled"; 1343 }; 1344 1345 uart6: serial@998000 { 1346 compatible = "qcom,geni-uart"; 1347 reg = <0 0x00998000 0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1349 clock-names = "se"; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1352 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1353 power-domains = <&rpmhpd SC7280_CX>; 1354 operating-points-v2 = <&qup_opp_table>; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1356 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1357 interconnect-names = "qup-core", "qup-config"; 1358 status = "disabled"; 1359 }; 1360 1361 i2c7: i2c@99c000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0 0x0099c000 0 0x4000>; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1365 clock-names = "se"; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_i2c7_data_clk>; 1368 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1372 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1373 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1374 interconnect-names = "qup-core", "qup-config", 1375 "qup-memory"; 1376 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1377 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1378 dma-names = "tx", "rx"; 1379 status = "disabled"; 1380 }; 1381 1382 spi7: spi@99c000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0 0x0099c000 0 0x4000>; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1386 clock-names = "se"; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1389 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 power-domains = <&rpmhpd SC7280_CX>; 1393 operating-points-v2 = <&qup_opp_table>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1396 interconnect-names = "qup-core", "qup-config"; 1397 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1398 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 status = "disabled"; 1401 }; 1402 1403 uart7: serial@99c000 { 1404 compatible = "qcom,geni-uart"; 1405 reg = <0 0x0099c000 0 0x4000>; 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1407 clock-names = "se"; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1410 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1411 power-domains = <&rpmhpd SC7280_CX>; 1412 operating-points-v2 = <&qup_opp_table>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1415 interconnect-names = "qup-core", "qup-config"; 1416 status = "disabled"; 1417 }; 1418 }; 1419 1420 gpi_dma1: dma-controller@a00000 { 1421 #dma-cells = <3>; 1422 compatible = "qcom,sc7280-gpi-dma"; 1423 reg = <0 0x00a00000 0 0x60000>; 1424 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1436 dma-channels = <12>; 1437 dma-channel-mask = <0x1e>; 1438 iommus = <&apps_smmu 0x56 0x0>; 1439 status = "disabled"; 1440 }; 1441 1442 qupv3_id_1: geniqup@ac0000 { 1443 compatible = "qcom,geni-se-qup"; 1444 reg = <0 0x00ac0000 0 0x2000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1446 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1447 clock-names = "m-ahb", "s-ahb"; 1448 #address-cells = <2>; 1449 #size-cells = <2>; 1450 ranges; 1451 iommus = <&apps_smmu 0x43 0x0>; 1452 status = "disabled"; 1453 1454 i2c8: i2c@a80000 { 1455 compatible = "qcom,geni-i2c"; 1456 reg = <0 0x00a80000 0 0x4000>; 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1458 clock-names = "se"; 1459 pinctrl-names = "default"; 1460 pinctrl-0 = <&qup_i2c8_data_clk>; 1461 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1465 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1466 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1467 interconnect-names = "qup-core", "qup-config", 1468 "qup-memory"; 1469 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1470 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1471 dma-names = "tx", "rx"; 1472 status = "disabled"; 1473 }; 1474 1475 spi8: spi@a80000 { 1476 compatible = "qcom,geni-spi"; 1477 reg = <0 0x00a80000 0 0x4000>; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1479 clock-names = "se"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 power-domains = <&rpmhpd SC7280_CX>; 1486 operating-points-v2 = <&qup_opp_table>; 1487 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1488 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1489 interconnect-names = "qup-core", "qup-config"; 1490 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1491 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 uart8: serial@a80000 { 1497 compatible = "qcom,geni-uart"; 1498 reg = <0 0x00a80000 0 0x4000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1500 clock-names = "se"; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd SC7280_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1508 interconnect-names = "qup-core", "qup-config"; 1509 status = "disabled"; 1510 }; 1511 1512 i2c9: i2c@a84000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0 0x00a84000 0 0x4000>; 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1516 clock-names = "se"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_i2c9_data_clk>; 1519 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1524 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", 1526 "qup-memory"; 1527 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1528 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1529 dma-names = "tx", "rx"; 1530 status = "disabled"; 1531 }; 1532 1533 spi9: spi@a84000 { 1534 compatible = "qcom,geni-spi"; 1535 reg = <0 0x00a84000 0 0x4000>; 1536 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1537 clock-names = "se"; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 power-domains = <&rpmhpd SC7280_CX>; 1544 operating-points-v2 = <&qup_opp_table>; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1546 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1547 interconnect-names = "qup-core", "qup-config"; 1548 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1549 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1550 dma-names = "tx", "rx"; 1551 status = "disabled"; 1552 }; 1553 1554 uart9: serial@a84000 { 1555 compatible = "qcom,geni-uart"; 1556 reg = <0 0x00a84000 0 0x4000>; 1557 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1558 clock-names = "se"; 1559 pinctrl-names = "default"; 1560 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1561 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1562 power-domains = <&rpmhpd SC7280_CX>; 1563 operating-points-v2 = <&qup_opp_table>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1565 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1566 interconnect-names = "qup-core", "qup-config"; 1567 status = "disabled"; 1568 }; 1569 1570 i2c10: i2c@a88000 { 1571 compatible = "qcom,geni-i2c"; 1572 reg = <0 0x00a88000 0 0x4000>; 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1574 clock-names = "se"; 1575 pinctrl-names = "default"; 1576 pinctrl-0 = <&qup_i2c10_data_clk>; 1577 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1581 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1582 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1583 interconnect-names = "qup-core", "qup-config", 1584 "qup-memory"; 1585 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1586 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1587 dma-names = "tx", "rx"; 1588 status = "disabled"; 1589 }; 1590 1591 spi10: spi@a88000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00a88000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1595 clock-names = "se"; 1596 pinctrl-names = "default"; 1597 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1598 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 power-domains = <&rpmhpd SC7280_CX>; 1602 operating-points-v2 = <&qup_opp_table>; 1603 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1604 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1605 interconnect-names = "qup-core", "qup-config"; 1606 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1607 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1608 dma-names = "tx", "rx"; 1609 status = "disabled"; 1610 }; 1611 1612 uart10: serial@a88000 { 1613 compatible = "qcom,geni-uart"; 1614 reg = <0 0x00a88000 0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1616 clock-names = "se"; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1619 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1620 power-domains = <&rpmhpd SC7280_CX>; 1621 operating-points-v2 = <&qup_opp_table>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1623 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1624 interconnect-names = "qup-core", "qup-config"; 1625 status = "disabled"; 1626 }; 1627 1628 i2c11: i2c@a8c000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a8c000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c11_data_clk>; 1635 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", 1642 "qup-memory"; 1643 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1644 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1645 dma-names = "tx", "rx"; 1646 status = "disabled"; 1647 }; 1648 1649 spi11: spi@a8c000 { 1650 compatible = "qcom,geni-spi"; 1651 reg = <0 0x00a8c000 0 0x4000>; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1653 clock-names = "se"; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1656 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 power-domains = <&rpmhpd SC7280_CX>; 1660 operating-points-v2 = <&qup_opp_table>; 1661 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1662 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1663 interconnect-names = "qup-core", "qup-config"; 1664 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1665 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1666 dma-names = "tx", "rx"; 1667 status = "disabled"; 1668 }; 1669 1670 uart11: serial@a8c000 { 1671 compatible = "qcom,geni-uart"; 1672 reg = <0 0x00a8c000 0 0x4000>; 1673 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1674 clock-names = "se"; 1675 pinctrl-names = "default"; 1676 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1677 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1678 power-domains = <&rpmhpd SC7280_CX>; 1679 operating-points-v2 = <&qup_opp_table>; 1680 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1681 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1682 interconnect-names = "qup-core", "qup-config"; 1683 status = "disabled"; 1684 }; 1685 1686 i2c12: i2c@a90000 { 1687 compatible = "qcom,geni-i2c"; 1688 reg = <0 0x00a90000 0 0x4000>; 1689 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1690 clock-names = "se"; 1691 pinctrl-names = "default"; 1692 pinctrl-0 = <&qup_i2c12_data_clk>; 1693 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1698 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1699 interconnect-names = "qup-core", "qup-config", 1700 "qup-memory"; 1701 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1702 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1703 dma-names = "tx", "rx"; 1704 status = "disabled"; 1705 }; 1706 1707 spi12: spi@a90000 { 1708 compatible = "qcom,geni-spi"; 1709 reg = <0 0x00a90000 0 0x4000>; 1710 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1711 clock-names = "se"; 1712 pinctrl-names = "default"; 1713 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1714 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 power-domains = <&rpmhpd SC7280_CX>; 1718 operating-points-v2 = <&qup_opp_table>; 1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1721 interconnect-names = "qup-core", "qup-config"; 1722 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1723 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1724 dma-names = "tx", "rx"; 1725 status = "disabled"; 1726 }; 1727 1728 uart12: serial@a90000 { 1729 compatible = "qcom,geni-uart"; 1730 reg = <0 0x00a90000 0 0x4000>; 1731 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1732 clock-names = "se"; 1733 pinctrl-names = "default"; 1734 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1735 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1736 power-domains = <&rpmhpd SC7280_CX>; 1737 operating-points-v2 = <&qup_opp_table>; 1738 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1739 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1740 interconnect-names = "qup-core", "qup-config"; 1741 status = "disabled"; 1742 }; 1743 1744 i2c13: i2c@a94000 { 1745 compatible = "qcom,geni-i2c"; 1746 reg = <0 0x00a94000 0 0x4000>; 1747 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1748 clock-names = "se"; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&qup_i2c13_data_clk>; 1751 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1755 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1756 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1757 interconnect-names = "qup-core", "qup-config", 1758 "qup-memory"; 1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1760 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1761 dma-names = "tx", "rx"; 1762 status = "disabled"; 1763 }; 1764 1765 spi13: spi@a94000 { 1766 compatible = "qcom,geni-spi"; 1767 reg = <0 0x00a94000 0 0x4000>; 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1769 clock-names = "se"; 1770 pinctrl-names = "default"; 1771 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1772 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 power-domains = <&rpmhpd SC7280_CX>; 1776 operating-points-v2 = <&qup_opp_table>; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1778 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1779 interconnect-names = "qup-core", "qup-config"; 1780 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1781 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1782 dma-names = "tx", "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 uart13: serial@a94000 { 1787 compatible = "qcom,geni-uart"; 1788 reg = <0 0x00a94000 0 0x4000>; 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1790 clock-names = "se"; 1791 pinctrl-names = "default"; 1792 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1793 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1794 power-domains = <&rpmhpd SC7280_CX>; 1795 operating-points-v2 = <&qup_opp_table>; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1797 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1798 interconnect-names = "qup-core", "qup-config"; 1799 status = "disabled"; 1800 }; 1801 1802 i2c14: i2c@a98000 { 1803 compatible = "qcom,geni-i2c"; 1804 reg = <0 0x00a98000 0 0x4000>; 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1806 clock-names = "se"; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_i2c14_data_clk>; 1809 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1814 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1815 interconnect-names = "qup-core", "qup-config", 1816 "qup-memory"; 1817 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1818 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1819 dma-names = "tx", "rx"; 1820 status = "disabled"; 1821 }; 1822 1823 spi14: spi@a98000 { 1824 compatible = "qcom,geni-spi"; 1825 reg = <0 0x00a98000 0 0x4000>; 1826 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1827 clock-names = "se"; 1828 pinctrl-names = "default"; 1829 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1830 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 power-domains = <&rpmhpd SC7280_CX>; 1834 operating-points-v2 = <&qup_opp_table>; 1835 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1836 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1837 interconnect-names = "qup-core", "qup-config"; 1838 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1839 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1840 dma-names = "tx", "rx"; 1841 status = "disabled"; 1842 }; 1843 1844 uart14: serial@a98000 { 1845 compatible = "qcom,geni-uart"; 1846 reg = <0 0x00a98000 0 0x4000>; 1847 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1848 clock-names = "se"; 1849 pinctrl-names = "default"; 1850 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1851 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1852 power-domains = <&rpmhpd SC7280_CX>; 1853 operating-points-v2 = <&qup_opp_table>; 1854 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1855 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1856 interconnect-names = "qup-core", "qup-config"; 1857 status = "disabled"; 1858 }; 1859 1860 i2c15: i2c@a9c000 { 1861 compatible = "qcom,geni-i2c"; 1862 reg = <0 0x00a9c000 0 0x4000>; 1863 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1864 clock-names = "se"; 1865 pinctrl-names = "default"; 1866 pinctrl-0 = <&qup_i2c15_data_clk>; 1867 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1871 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "qup-core", "qup-config", 1874 "qup-memory"; 1875 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1876 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1877 dma-names = "tx", "rx"; 1878 status = "disabled"; 1879 }; 1880 1881 spi15: spi@a9c000 { 1882 compatible = "qcom,geni-spi"; 1883 reg = <0 0x00a9c000 0 0x4000>; 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1885 clock-names = "se"; 1886 pinctrl-names = "default"; 1887 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1888 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 power-domains = <&rpmhpd SC7280_CX>; 1892 operating-points-v2 = <&qup_opp_table>; 1893 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1894 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1895 interconnect-names = "qup-core", "qup-config"; 1896 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1897 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1898 dma-names = "tx", "rx"; 1899 status = "disabled"; 1900 }; 1901 1902 uart15: serial@a9c000 { 1903 compatible = "qcom,geni-uart"; 1904 reg = <0 0x00a9c000 0 0x4000>; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1906 clock-names = "se"; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 1909 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1910 power-domains = <&rpmhpd SC7280_CX>; 1911 operating-points-v2 = <&qup_opp_table>; 1912 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1913 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1914 interconnect-names = "qup-core", "qup-config"; 1915 status = "disabled"; 1916 }; 1917 }; 1918 1919 cnoc2: interconnect@1500000 { 1920 reg = <0 0x01500000 0 0x1000>; 1921 compatible = "qcom,sc7280-cnoc2"; 1922 #interconnect-cells = <2>; 1923 qcom,bcm-voters = <&apps_bcm_voter>; 1924 }; 1925 1926 cnoc3: interconnect@1502000 { 1927 reg = <0 0x01502000 0 0x1000>; 1928 compatible = "qcom,sc7280-cnoc3"; 1929 #interconnect-cells = <2>; 1930 qcom,bcm-voters = <&apps_bcm_voter>; 1931 }; 1932 1933 mc_virt: interconnect@1580000 { 1934 reg = <0 0x01580000 0 0x4>; 1935 compatible = "qcom,sc7280-mc-virt"; 1936 #interconnect-cells = <2>; 1937 qcom,bcm-voters = <&apps_bcm_voter>; 1938 }; 1939 1940 system_noc: interconnect@1680000 { 1941 reg = <0 0x01680000 0 0x15480>; 1942 compatible = "qcom,sc7280-system-noc"; 1943 #interconnect-cells = <2>; 1944 qcom,bcm-voters = <&apps_bcm_voter>; 1945 }; 1946 1947 aggre1_noc: interconnect@16e0000 { 1948 compatible = "qcom,sc7280-aggre1-noc"; 1949 reg = <0 0x016e0000 0 0x1c080>; 1950 #interconnect-cells = <2>; 1951 qcom,bcm-voters = <&apps_bcm_voter>; 1952 }; 1953 1954 aggre2_noc: interconnect@1700000 { 1955 reg = <0 0x01700000 0 0x2b080>; 1956 compatible = "qcom,sc7280-aggre2-noc"; 1957 #interconnect-cells = <2>; 1958 qcom,bcm-voters = <&apps_bcm_voter>; 1959 }; 1960 1961 mmss_noc: interconnect@1740000 { 1962 reg = <0 0x01740000 0 0x1e080>; 1963 compatible = "qcom,sc7280-mmss-noc"; 1964 #interconnect-cells = <2>; 1965 qcom,bcm-voters = <&apps_bcm_voter>; 1966 }; 1967 1968 wifi: wifi@17a10040 { 1969 compatible = "qcom,wcn6750-wifi"; 1970 reg = <0 0x17a10040 0 0x0>; 1971 iommus = <&apps_smmu 0x1c00 0x1>; 1972 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 1973 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 1974 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 1975 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 1976 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 1977 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 1978 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 1979 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 1980 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 1981 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 1982 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 1983 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 1984 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 1985 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 1986 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 1987 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 1988 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 1989 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 1990 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 1991 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 1992 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 1993 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 1994 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 1995 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 1996 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 1997 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 1998 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 1999 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2000 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2001 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2002 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2003 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2004 qcom,rproc = <&remoteproc_wpss>; 2005 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2006 status = "disabled"; 2007 }; 2008 2009 pcie1: pci@1c08000 { 2010 compatible = "qcom,pcie-sc7280"; 2011 reg = <0 0x01c08000 0 0x3000>, 2012 <0 0x40000000 0 0xf1d>, 2013 <0 0x40000f20 0 0xa8>, 2014 <0 0x40001000 0 0x1000>, 2015 <0 0x40100000 0 0x100000>; 2016 2017 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2018 device_type = "pci"; 2019 linux,pci-domain = <1>; 2020 bus-range = <0x00 0xff>; 2021 num-lanes = <2>; 2022 2023 #address-cells = <3>; 2024 #size-cells = <2>; 2025 2026 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 2027 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2028 2029 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2030 interrupt-names = "msi"; 2031 #interrupt-cells = <1>; 2032 interrupt-map-mask = <0 0 0 0x7>; 2033 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2034 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2035 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2036 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2037 2038 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2039 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2040 <&pcie1_lane>, 2041 <&rpmhcc RPMH_CXO_CLK>, 2042 <&gcc GCC_PCIE_1_AUX_CLK>, 2043 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2044 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2045 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2046 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2047 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2048 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2049 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2050 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2051 2052 clock-names = "pipe", 2053 "pipe_mux", 2054 "phy_pipe", 2055 "ref", 2056 "aux", 2057 "cfg", 2058 "bus_master", 2059 "bus_slave", 2060 "slave_q2a", 2061 "tbu", 2062 "ddrss_sf_tbu", 2063 "aggre0", 2064 "aggre1"; 2065 2066 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2067 assigned-clock-rates = <19200000>; 2068 2069 resets = <&gcc GCC_PCIE_1_BCR>; 2070 reset-names = "pci"; 2071 2072 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2073 2074 phys = <&pcie1_lane>; 2075 phy-names = "pciephy"; 2076 2077 pinctrl-names = "default"; 2078 pinctrl-0 = <&pcie1_clkreq_n>; 2079 2080 iommus = <&apps_smmu 0x1c80 0x1>; 2081 2082 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2083 <0x100 &apps_smmu 0x1c81 0x1>; 2084 2085 status = "disabled"; 2086 }; 2087 2088 pcie1_phy: phy@1c0e000 { 2089 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2090 reg = <0 0x01c0e000 0 0x1c0>; 2091 #address-cells = <2>; 2092 #size-cells = <2>; 2093 ranges; 2094 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2095 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2096 <&gcc GCC_PCIE_CLKREF_EN>, 2097 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2098 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2099 2100 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2101 reset-names = "phy"; 2102 2103 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2104 assigned-clock-rates = <100000000>; 2105 2106 status = "disabled"; 2107 2108 pcie1_lane: phy@1c0e200 { 2109 reg = <0 0x01c0e200 0 0x170>, 2110 <0 0x01c0e400 0 0x200>, 2111 <0 0x01c0ea00 0 0x1f0>, 2112 <0 0x01c0e600 0 0x170>, 2113 <0 0x01c0e800 0 0x200>, 2114 <0 0x01c0ee00 0 0xf4>; 2115 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2116 clock-names = "pipe0"; 2117 2118 #phy-cells = <0>; 2119 #clock-cells = <0>; 2120 clock-output-names = "pcie_1_pipe_clk"; 2121 }; 2122 }; 2123 2124 ipa: ipa@1e40000 { 2125 compatible = "qcom,sc7280-ipa"; 2126 2127 iommus = <&apps_smmu 0x480 0x0>, 2128 <&apps_smmu 0x482 0x0>; 2129 reg = <0 0x1e40000 0 0x8000>, 2130 <0 0x1e50000 0 0x4ad0>, 2131 <0 0x1e04000 0 0x23000>; 2132 reg-names = "ipa-reg", 2133 "ipa-shared", 2134 "gsi"; 2135 2136 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2137 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2138 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2139 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2140 interrupt-names = "ipa", 2141 "gsi", 2142 "ipa-clock-query", 2143 "ipa-setup-ready"; 2144 2145 clocks = <&rpmhcc RPMH_IPA_CLK>; 2146 clock-names = "core"; 2147 2148 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2150 interconnect-names = "memory", 2151 "config"; 2152 2153 qcom,qmp = <&aoss_qmp>; 2154 2155 qcom,smem-states = <&ipa_smp2p_out 0>, 2156 <&ipa_smp2p_out 1>; 2157 qcom,smem-state-names = "ipa-clock-enabled-valid", 2158 "ipa-clock-enabled"; 2159 2160 status = "disabled"; 2161 }; 2162 2163 tcsr_mutex: hwlock@1f40000 { 2164 compatible = "qcom,tcsr-mutex"; 2165 reg = <0 0x01f40000 0 0x20000>; 2166 #hwlock-cells = <1>; 2167 }; 2168 2169 tcsr_1: syscon@1f60000 { 2170 compatible = "qcom,sc7280-tcsr", "syscon"; 2171 reg = <0 0x01f60000 0 0x20000>; 2172 }; 2173 2174 tcsr_2: syscon@1fc0000 { 2175 compatible = "qcom,sc7280-tcsr", "syscon"; 2176 reg = <0 0x01fc0000 0 0x30000>; 2177 }; 2178 2179 lpasscc: lpasscc@3000000 { 2180 compatible = "qcom,sc7280-lpasscc"; 2181 reg = <0 0x03000000 0 0x40>, 2182 <0 0x03c04000 0 0x4>; 2183 reg-names = "qdsp6ss", "top_cc"; 2184 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2185 clock-names = "iface"; 2186 #clock-cells = <1>; 2187 }; 2188 2189 lpass_rx_macro: codec@3200000 { 2190 compatible = "qcom,sc7280-lpass-rx-macro"; 2191 reg = <0 0x03200000 0 0x1000>; 2192 2193 pinctrl-names = "default"; 2194 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2195 2196 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2197 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2198 <&lpass_va_macro>; 2199 clock-names = "mclk", "npl", "fsgen"; 2200 2201 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2202 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2203 power-domain-names = "macro", "dcodec"; 2204 2205 #clock-cells = <0>; 2206 #sound-dai-cells = <1>; 2207 2208 status = "disabled"; 2209 }; 2210 2211 swr0: soundwire@3210000 { 2212 compatible = "qcom,soundwire-v1.6.0"; 2213 reg = <0 0x03210000 0 0x2000>; 2214 2215 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&lpass_rx_macro>; 2217 clock-names = "iface"; 2218 2219 qcom,din-ports = <0>; 2220 qcom,dout-ports = <5>; 2221 2222 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2223 reset-names = "swr_audio_cgcr"; 2224 2225 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2226 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2227 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2228 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2229 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2230 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2231 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2232 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2233 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2234 2235 #sound-dai-cells = <1>; 2236 #address-cells = <2>; 2237 #size-cells = <0>; 2238 2239 status = "disabled"; 2240 }; 2241 2242 lpass_tx_macro: codec@3220000 { 2243 compatible = "qcom,sc7280-lpass-tx-macro"; 2244 reg = <0 0x03220000 0 0x1000>; 2245 2246 pinctrl-names = "default"; 2247 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2248 2249 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2250 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2251 <&lpass_va_macro>; 2252 clock-names = "mclk", "npl", "fsgen"; 2253 2254 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2255 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2256 power-domain-names = "macro", "dcodec"; 2257 2258 #clock-cells = <0>; 2259 #sound-dai-cells = <1>; 2260 2261 status = "disabled"; 2262 }; 2263 2264 swr1: soundwire@3230000 { 2265 compatible = "qcom,soundwire-v1.6.0"; 2266 reg = <0 0x03230000 0 0x2000>; 2267 2268 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2269 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2270 clocks = <&lpass_tx_macro>; 2271 clock-names = "iface"; 2272 2273 qcom,din-ports = <3>; 2274 qcom,dout-ports = <0>; 2275 2276 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2277 reset-names = "swr_audio_cgcr"; 2278 2279 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2280 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2281 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2282 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2283 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2284 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2285 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2286 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2287 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2288 qcom,port-offset = <1>; 2289 2290 #sound-dai-cells = <1>; 2291 #address-cells = <2>; 2292 #size-cells = <0>; 2293 2294 status = "disabled"; 2295 }; 2296 2297 lpass_audiocc: clock-controller@3300000 { 2298 compatible = "qcom,sc7280-lpassaudiocc"; 2299 reg = <0 0x03300000 0 0x30000>; 2300 clocks = <&rpmhcc RPMH_CXO_CLK>, 2301 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2302 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2303 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2304 #clock-cells = <1>; 2305 #power-domain-cells = <1>; 2306 #reset-cells = <1>; 2307 }; 2308 2309 lpass_va_macro: codec@3370000 { 2310 compatible = "qcom,sc7280-lpass-va-macro"; 2311 reg = <0 0x03370000 0 0x1000>; 2312 2313 pinctrl-names = "default"; 2314 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2315 2316 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2317 clock-names = "mclk"; 2318 2319 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2320 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2321 power-domain-names = "macro", "dcodec"; 2322 2323 #clock-cells = <0>; 2324 #sound-dai-cells = <1>; 2325 2326 status = "disabled"; 2327 }; 2328 2329 lpass_aon: clock-controller@3380000 { 2330 compatible = "qcom,sc7280-lpassaoncc"; 2331 reg = <0 0x03380000 0 0x30000>; 2332 clocks = <&rpmhcc RPMH_CXO_CLK>, 2333 <&rpmhcc RPMH_CXO_CLK_A>, 2334 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2335 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2336 #clock-cells = <1>; 2337 #power-domain-cells = <1>; 2338 }; 2339 2340 lpass_core: clock-controller@3900000 { 2341 compatible = "qcom,sc7280-lpasscorecc"; 2342 reg = <0 0x03900000 0 0x50000>; 2343 clocks = <&rpmhcc RPMH_CXO_CLK>; 2344 clock-names = "bi_tcxo"; 2345 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2346 #clock-cells = <1>; 2347 #power-domain-cells = <1>; 2348 }; 2349 2350 lpass_cpu: audio@3987000 { 2351 compatible = "qcom,sc7280-lpass-cpu"; 2352 2353 reg = <0 0x03987000 0 0x68000>, 2354 <0 0x03b00000 0 0x29000>, 2355 <0 0x03260000 0 0xc000>, 2356 <0 0x03280000 0 0x29000>, 2357 <0 0x03340000 0 0x29000>, 2358 <0 0x0336c000 0 0x3000>; 2359 reg-names = "lpass-hdmiif", 2360 "lpass-lpaif", 2361 "lpass-rxtx-cdc-dma-lpm", 2362 "lpass-rxtx-lpaif", 2363 "lpass-va-lpaif", 2364 "lpass-va-cdc-dma-lpm"; 2365 2366 iommus = <&apps_smmu 0x1820 0>, 2367 <&apps_smmu 0x1821 0>, 2368 <&apps_smmu 0x1832 0>; 2369 2370 power-domains = <&rpmhpd SC7280_LCX>; 2371 power-domain-names = "lcx"; 2372 required-opps = <&rpmhpd_opp_nom>; 2373 2374 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2375 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2376 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2377 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2378 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2379 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2380 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2381 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2382 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2383 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2384 clock-names = "aon_cc_audio_hm_h", 2385 "audio_cc_ext_mclk0", 2386 "core_cc_sysnoc_mport_core", 2387 "core_cc_ext_if0_ibit", 2388 "core_cc_ext_if1_ibit", 2389 "audio_cc_codec_mem", 2390 "audio_cc_codec_mem0", 2391 "audio_cc_codec_mem1", 2392 "audio_cc_codec_mem2", 2393 "aon_cc_va_mem0"; 2394 2395 #sound-dai-cells = <1>; 2396 #address-cells = <1>; 2397 #size-cells = <0>; 2398 2399 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2403 interrupt-names = "lpass-irq-lpaif", 2404 "lpass-irq-hdmi", 2405 "lpass-irq-vaif", 2406 "lpass-irq-rxtxif"; 2407 2408 status = "disabled"; 2409 }; 2410 2411 lpass_hm: clock-controller@3c00000 { 2412 compatible = "qcom,sc7280-lpasshm"; 2413 reg = <0 0x3c00000 0 0x28>; 2414 clocks = <&rpmhcc RPMH_CXO_CLK>; 2415 clock-names = "bi_tcxo"; 2416 #clock-cells = <1>; 2417 #power-domain-cells = <1>; 2418 }; 2419 2420 lpass_ag_noc: interconnect@3c40000 { 2421 reg = <0 0x03c40000 0 0xf080>; 2422 compatible = "qcom,sc7280-lpass-ag-noc"; 2423 #interconnect-cells = <2>; 2424 qcom,bcm-voters = <&apps_bcm_voter>; 2425 }; 2426 2427 lpass_tlmm: pinctrl@33c0000 { 2428 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2429 reg = <0 0x033c0000 0x0 0x20000>, 2430 <0 0x03550000 0x0 0x10000>; 2431 qcom,adsp-bypass-mode; 2432 gpio-controller; 2433 #gpio-cells = <2>; 2434 gpio-ranges = <&lpass_tlmm 0 0 15>; 2435 2436 #clock-cells = <1>; 2437 2438 lpass_dmic01_clk: dmic01-clk { 2439 pins = "gpio6"; 2440 function = "dmic1_clk"; 2441 }; 2442 2443 lpass_dmic01_clk_sleep: dmic01-clk-sleep { 2444 pins = "gpio6"; 2445 function = "dmic1_clk"; 2446 }; 2447 2448 lpass_dmic01_data: dmic01-data { 2449 pins = "gpio7"; 2450 function = "dmic1_data"; 2451 }; 2452 2453 lpass_dmic01_data_sleep: dmic01-data-sleep { 2454 pins = "gpio7"; 2455 function = "dmic1_data"; 2456 }; 2457 2458 lpass_dmic23_clk: dmic23-clk { 2459 pins = "gpio8"; 2460 function = "dmic2_clk"; 2461 }; 2462 2463 lpass_dmic23_clk_sleep: dmic23-clk-sleep { 2464 pins = "gpio8"; 2465 function = "dmic2_clk"; 2466 }; 2467 2468 lpass_dmic23_data: dmic23-data { 2469 pins = "gpio9"; 2470 function = "dmic2_data"; 2471 }; 2472 2473 lpass_dmic23_data_sleep: dmic23-data-sleep { 2474 pins = "gpio9"; 2475 function = "dmic2_data"; 2476 }; 2477 2478 lpass_rx_swr_clk: rx-swr-clk { 2479 pins = "gpio3"; 2480 function = "swr_rx_clk"; 2481 }; 2482 2483 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { 2484 pins = "gpio3"; 2485 function = "swr_rx_clk"; 2486 }; 2487 2488 lpass_rx_swr_data: rx-swr-data { 2489 pins = "gpio4", "gpio5"; 2490 function = "swr_rx_data"; 2491 }; 2492 2493 lpass_rx_swr_data_sleep: rx-swr-data-sleep { 2494 pins = "gpio4", "gpio5"; 2495 function = "swr_rx_data"; 2496 }; 2497 2498 lpass_tx_swr_clk: tx-swr-clk { 2499 pins = "gpio0"; 2500 function = "swr_tx_clk"; 2501 }; 2502 2503 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { 2504 pins = "gpio0"; 2505 function = "swr_tx_clk"; 2506 }; 2507 2508 lpass_tx_swr_data: tx-swr-data { 2509 pins = "gpio1", "gpio2", "gpio14"; 2510 function = "swr_tx_data"; 2511 }; 2512 2513 lpass_tx_swr_data_sleep: tx-swr-data-sleep { 2514 pins = "gpio1", "gpio2", "gpio14"; 2515 function = "swr_tx_data"; 2516 }; 2517 }; 2518 2519 gpu: gpu@3d00000 { 2520 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2521 reg = <0 0x03d00000 0 0x40000>, 2522 <0 0x03d9e000 0 0x1000>, 2523 <0 0x03d61000 0 0x800>; 2524 reg-names = "kgsl_3d0_reg_memory", 2525 "cx_mem", 2526 "cx_dbgc"; 2527 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2528 iommus = <&adreno_smmu 0 0x401>; 2529 operating-points-v2 = <&gpu_opp_table>; 2530 qcom,gmu = <&gmu>; 2531 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2532 interconnect-names = "gfx-mem"; 2533 #cooling-cells = <2>; 2534 2535 nvmem-cells = <&gpu_speed_bin>; 2536 nvmem-cell-names = "speed_bin"; 2537 2538 gpu_opp_table: opp-table { 2539 compatible = "operating-points-v2"; 2540 2541 opp-315000000 { 2542 opp-hz = /bits/ 64 <315000000>; 2543 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2544 opp-peak-kBps = <1804000>; 2545 opp-supported-hw = <0x03>; 2546 }; 2547 2548 opp-450000000 { 2549 opp-hz = /bits/ 64 <450000000>; 2550 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2551 opp-peak-kBps = <4068000>; 2552 opp-supported-hw = <0x03>; 2553 }; 2554 2555 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2556 opp-550000000-0 { 2557 opp-hz = /bits/ 64 <550000000>; 2558 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2559 opp-peak-kBps = <8368000>; 2560 opp-supported-hw = <0x01>; 2561 }; 2562 2563 opp-550000000-1 { 2564 opp-hz = /bits/ 64 <550000000>; 2565 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2566 opp-peak-kBps = <6832000>; 2567 opp-supported-hw = <0x02>; 2568 }; 2569 2570 opp-608000000 { 2571 opp-hz = /bits/ 64 <608000000>; 2572 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2573 opp-peak-kBps = <8368000>; 2574 opp-supported-hw = <0x02>; 2575 }; 2576 2577 opp-700000000 { 2578 opp-hz = /bits/ 64 <700000000>; 2579 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2580 opp-peak-kBps = <8532000>; 2581 opp-supported-hw = <0x02>; 2582 }; 2583 2584 opp-812000000 { 2585 opp-hz = /bits/ 64 <812000000>; 2586 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2587 opp-peak-kBps = <8532000>; 2588 opp-supported-hw = <0x02>; 2589 }; 2590 2591 opp-840000000 { 2592 opp-hz = /bits/ 64 <840000000>; 2593 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2594 opp-peak-kBps = <8532000>; 2595 opp-supported-hw = <0x02>; 2596 }; 2597 2598 opp-900000000 { 2599 opp-hz = /bits/ 64 <900000000>; 2600 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2601 opp-peak-kBps = <8532000>; 2602 opp-supported-hw = <0x02>; 2603 }; 2604 }; 2605 }; 2606 2607 gmu: gmu@3d6a000 { 2608 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2609 reg = <0 0x03d6a000 0 0x34000>, 2610 <0 0x3de0000 0 0x10000>, 2611 <0 0x0b290000 0 0x10000>; 2612 reg-names = "gmu", "rscc", "gmu_pdc"; 2613 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2615 interrupt-names = "hfi", "gmu"; 2616 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2617 <&gpucc GPU_CC_CXO_CLK>, 2618 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2619 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2620 <&gpucc GPU_CC_AHB_CLK>, 2621 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2622 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2623 clock-names = "gmu", 2624 "cxo", 2625 "axi", 2626 "memnoc", 2627 "ahb", 2628 "hub", 2629 "smmu_vote"; 2630 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2631 <&gpucc GPU_CC_GX_GDSC>; 2632 power-domain-names = "cx", 2633 "gx"; 2634 iommus = <&adreno_smmu 5 0x400>; 2635 operating-points-v2 = <&gmu_opp_table>; 2636 2637 gmu_opp_table: opp-table { 2638 compatible = "operating-points-v2"; 2639 2640 opp-200000000 { 2641 opp-hz = /bits/ 64 <200000000>; 2642 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2643 }; 2644 }; 2645 }; 2646 2647 gpucc: clock-controller@3d90000 { 2648 compatible = "qcom,sc7280-gpucc"; 2649 reg = <0 0x03d90000 0 0x9000>; 2650 clocks = <&rpmhcc RPMH_CXO_CLK>, 2651 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2652 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2653 clock-names = "bi_tcxo", 2654 "gcc_gpu_gpll0_clk_src", 2655 "gcc_gpu_gpll0_div_clk_src"; 2656 #clock-cells = <1>; 2657 #reset-cells = <1>; 2658 #power-domain-cells = <1>; 2659 }; 2660 2661 adreno_smmu: iommu@3da0000 { 2662 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2663 reg = <0 0x03da0000 0 0x20000>; 2664 #iommu-cells = <2>; 2665 #global-interrupts = <2>; 2666 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2678 2679 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2680 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2681 <&gpucc GPU_CC_AHB_CLK>, 2682 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2683 <&gpucc GPU_CC_CX_GMU_CLK>, 2684 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2685 <&gpucc GPU_CC_HUB_AON_CLK>; 2686 clock-names = "gcc_gpu_memnoc_gfx_clk", 2687 "gcc_gpu_snoc_dvm_gfx_clk", 2688 "gpu_cc_ahb_clk", 2689 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2690 "gpu_cc_cx_gmu_clk", 2691 "gpu_cc_hub_cx_int_clk", 2692 "gpu_cc_hub_aon_clk"; 2693 2694 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2695 }; 2696 2697 remoteproc_mpss: remoteproc@4080000 { 2698 compatible = "qcom,sc7280-mpss-pas"; 2699 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2700 reg-names = "qdsp6", "rmb"; 2701 2702 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2703 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2704 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2705 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2706 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2707 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2708 interrupt-names = "wdog", "fatal", "ready", "handover", 2709 "stop-ack", "shutdown-ack"; 2710 2711 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2712 <&gcc GCC_MSS_OFFLINE_AXI_CLK>, 2713 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2714 <&rpmhcc RPMH_PKA_CLK>, 2715 <&rpmhcc RPMH_CXO_CLK>; 2716 clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; 2717 2718 power-domains = <&rpmhpd SC7280_CX>, 2719 <&rpmhpd SC7280_MSS>; 2720 power-domain-names = "cx", "mss"; 2721 2722 memory-region = <&mpss_mem>; 2723 2724 qcom,qmp = <&aoss_qmp>; 2725 2726 qcom,smem-states = <&modem_smp2p_out 0>; 2727 qcom,smem-state-names = "stop"; 2728 2729 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2730 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2731 reset-names = "mss_restart", "pdc_reset"; 2732 2733 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; 2734 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; 2735 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; 2736 2737 status = "disabled"; 2738 2739 glink-edge { 2740 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2741 IPCC_MPROC_SIGNAL_GLINK_QMP 2742 IRQ_TYPE_EDGE_RISING>; 2743 mboxes = <&ipcc IPCC_CLIENT_MPSS 2744 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2745 label = "modem"; 2746 qcom,remote-pid = <1>; 2747 }; 2748 }; 2749 2750 stm@6002000 { 2751 compatible = "arm,coresight-stm", "arm,primecell"; 2752 reg = <0 0x06002000 0 0x1000>, 2753 <0 0x16280000 0 0x180000>; 2754 reg-names = "stm-base", "stm-stimulus-base"; 2755 2756 clocks = <&aoss_qmp>; 2757 clock-names = "apb_pclk"; 2758 2759 out-ports { 2760 port { 2761 stm_out: endpoint { 2762 remote-endpoint = <&funnel0_in7>; 2763 }; 2764 }; 2765 }; 2766 }; 2767 2768 funnel@6041000 { 2769 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2770 reg = <0 0x06041000 0 0x1000>; 2771 2772 clocks = <&aoss_qmp>; 2773 clock-names = "apb_pclk"; 2774 2775 out-ports { 2776 port { 2777 funnel0_out: endpoint { 2778 remote-endpoint = <&merge_funnel_in0>; 2779 }; 2780 }; 2781 }; 2782 2783 in-ports { 2784 #address-cells = <1>; 2785 #size-cells = <0>; 2786 2787 port@7 { 2788 reg = <7>; 2789 funnel0_in7: endpoint { 2790 remote-endpoint = <&stm_out>; 2791 }; 2792 }; 2793 }; 2794 }; 2795 2796 funnel@6042000 { 2797 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2798 reg = <0 0x06042000 0 0x1000>; 2799 2800 clocks = <&aoss_qmp>; 2801 clock-names = "apb_pclk"; 2802 2803 out-ports { 2804 port { 2805 funnel1_out: endpoint { 2806 remote-endpoint = <&merge_funnel_in1>; 2807 }; 2808 }; 2809 }; 2810 2811 in-ports { 2812 #address-cells = <1>; 2813 #size-cells = <0>; 2814 2815 port@4 { 2816 reg = <4>; 2817 funnel1_in4: endpoint { 2818 remote-endpoint = <&apss_merge_funnel_out>; 2819 }; 2820 }; 2821 }; 2822 }; 2823 2824 funnel@6045000 { 2825 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2826 reg = <0 0x06045000 0 0x1000>; 2827 2828 clocks = <&aoss_qmp>; 2829 clock-names = "apb_pclk"; 2830 2831 out-ports { 2832 port { 2833 merge_funnel_out: endpoint { 2834 remote-endpoint = <&swao_funnel_in>; 2835 }; 2836 }; 2837 }; 2838 2839 in-ports { 2840 #address-cells = <1>; 2841 #size-cells = <0>; 2842 2843 port@0 { 2844 reg = <0>; 2845 merge_funnel_in0: endpoint { 2846 remote-endpoint = <&funnel0_out>; 2847 }; 2848 }; 2849 2850 port@1 { 2851 reg = <1>; 2852 merge_funnel_in1: endpoint { 2853 remote-endpoint = <&funnel1_out>; 2854 }; 2855 }; 2856 }; 2857 }; 2858 2859 replicator@6046000 { 2860 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2861 reg = <0 0x06046000 0 0x1000>; 2862 2863 clocks = <&aoss_qmp>; 2864 clock-names = "apb_pclk"; 2865 2866 out-ports { 2867 port { 2868 replicator_out: endpoint { 2869 remote-endpoint = <&etr_in>; 2870 }; 2871 }; 2872 }; 2873 2874 in-ports { 2875 port { 2876 replicator_in: endpoint { 2877 remote-endpoint = <&swao_replicator_out>; 2878 }; 2879 }; 2880 }; 2881 }; 2882 2883 etr@6048000 { 2884 compatible = "arm,coresight-tmc", "arm,primecell"; 2885 reg = <0 0x06048000 0 0x1000>; 2886 iommus = <&apps_smmu 0x04c0 0>; 2887 2888 clocks = <&aoss_qmp>; 2889 clock-names = "apb_pclk"; 2890 arm,scatter-gather; 2891 2892 in-ports { 2893 port { 2894 etr_in: endpoint { 2895 remote-endpoint = <&replicator_out>; 2896 }; 2897 }; 2898 }; 2899 }; 2900 2901 funnel@6b04000 { 2902 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2903 reg = <0 0x06b04000 0 0x1000>; 2904 2905 clocks = <&aoss_qmp>; 2906 clock-names = "apb_pclk"; 2907 2908 out-ports { 2909 port { 2910 swao_funnel_out: endpoint { 2911 remote-endpoint = <&etf_in>; 2912 }; 2913 }; 2914 }; 2915 2916 in-ports { 2917 #address-cells = <1>; 2918 #size-cells = <0>; 2919 2920 port@7 { 2921 reg = <7>; 2922 swao_funnel_in: endpoint { 2923 remote-endpoint = <&merge_funnel_out>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 etf@6b05000 { 2930 compatible = "arm,coresight-tmc", "arm,primecell"; 2931 reg = <0 0x06b05000 0 0x1000>; 2932 2933 clocks = <&aoss_qmp>; 2934 clock-names = "apb_pclk"; 2935 2936 out-ports { 2937 port { 2938 etf_out: endpoint { 2939 remote-endpoint = <&swao_replicator_in>; 2940 }; 2941 }; 2942 }; 2943 2944 in-ports { 2945 port { 2946 etf_in: endpoint { 2947 remote-endpoint = <&swao_funnel_out>; 2948 }; 2949 }; 2950 }; 2951 }; 2952 2953 replicator@6b06000 { 2954 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2955 reg = <0 0x06b06000 0 0x1000>; 2956 2957 clocks = <&aoss_qmp>; 2958 clock-names = "apb_pclk"; 2959 qcom,replicator-loses-context; 2960 2961 out-ports { 2962 port { 2963 swao_replicator_out: endpoint { 2964 remote-endpoint = <&replicator_in>; 2965 }; 2966 }; 2967 }; 2968 2969 in-ports { 2970 port { 2971 swao_replicator_in: endpoint { 2972 remote-endpoint = <&etf_out>; 2973 }; 2974 }; 2975 }; 2976 }; 2977 2978 etm@7040000 { 2979 compatible = "arm,coresight-etm4x", "arm,primecell"; 2980 reg = <0 0x07040000 0 0x1000>; 2981 2982 cpu = <&CPU0>; 2983 2984 clocks = <&aoss_qmp>; 2985 clock-names = "apb_pclk"; 2986 arm,coresight-loses-context-with-cpu; 2987 qcom,skip-power-up; 2988 2989 out-ports { 2990 port { 2991 etm0_out: endpoint { 2992 remote-endpoint = <&apss_funnel_in0>; 2993 }; 2994 }; 2995 }; 2996 }; 2997 2998 etm@7140000 { 2999 compatible = "arm,coresight-etm4x", "arm,primecell"; 3000 reg = <0 0x07140000 0 0x1000>; 3001 3002 cpu = <&CPU1>; 3003 3004 clocks = <&aoss_qmp>; 3005 clock-names = "apb_pclk"; 3006 arm,coresight-loses-context-with-cpu; 3007 qcom,skip-power-up; 3008 3009 out-ports { 3010 port { 3011 etm1_out: endpoint { 3012 remote-endpoint = <&apss_funnel_in1>; 3013 }; 3014 }; 3015 }; 3016 }; 3017 3018 etm@7240000 { 3019 compatible = "arm,coresight-etm4x", "arm,primecell"; 3020 reg = <0 0x07240000 0 0x1000>; 3021 3022 cpu = <&CPU2>; 3023 3024 clocks = <&aoss_qmp>; 3025 clock-names = "apb_pclk"; 3026 arm,coresight-loses-context-with-cpu; 3027 qcom,skip-power-up; 3028 3029 out-ports { 3030 port { 3031 etm2_out: endpoint { 3032 remote-endpoint = <&apss_funnel_in2>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 etm@7340000 { 3039 compatible = "arm,coresight-etm4x", "arm,primecell"; 3040 reg = <0 0x07340000 0 0x1000>; 3041 3042 cpu = <&CPU3>; 3043 3044 clocks = <&aoss_qmp>; 3045 clock-names = "apb_pclk"; 3046 arm,coresight-loses-context-with-cpu; 3047 qcom,skip-power-up; 3048 3049 out-ports { 3050 port { 3051 etm3_out: endpoint { 3052 remote-endpoint = <&apss_funnel_in3>; 3053 }; 3054 }; 3055 }; 3056 }; 3057 3058 etm@7440000 { 3059 compatible = "arm,coresight-etm4x", "arm,primecell"; 3060 reg = <0 0x07440000 0 0x1000>; 3061 3062 cpu = <&CPU4>; 3063 3064 clocks = <&aoss_qmp>; 3065 clock-names = "apb_pclk"; 3066 arm,coresight-loses-context-with-cpu; 3067 qcom,skip-power-up; 3068 3069 out-ports { 3070 port { 3071 etm4_out: endpoint { 3072 remote-endpoint = <&apss_funnel_in4>; 3073 }; 3074 }; 3075 }; 3076 }; 3077 3078 etm@7540000 { 3079 compatible = "arm,coresight-etm4x", "arm,primecell"; 3080 reg = <0 0x07540000 0 0x1000>; 3081 3082 cpu = <&CPU5>; 3083 3084 clocks = <&aoss_qmp>; 3085 clock-names = "apb_pclk"; 3086 arm,coresight-loses-context-with-cpu; 3087 qcom,skip-power-up; 3088 3089 out-ports { 3090 port { 3091 etm5_out: endpoint { 3092 remote-endpoint = <&apss_funnel_in5>; 3093 }; 3094 }; 3095 }; 3096 }; 3097 3098 etm@7640000 { 3099 compatible = "arm,coresight-etm4x", "arm,primecell"; 3100 reg = <0 0x07640000 0 0x1000>; 3101 3102 cpu = <&CPU6>; 3103 3104 clocks = <&aoss_qmp>; 3105 clock-names = "apb_pclk"; 3106 arm,coresight-loses-context-with-cpu; 3107 qcom,skip-power-up; 3108 3109 out-ports { 3110 port { 3111 etm6_out: endpoint { 3112 remote-endpoint = <&apss_funnel_in6>; 3113 }; 3114 }; 3115 }; 3116 }; 3117 3118 etm@7740000 { 3119 compatible = "arm,coresight-etm4x", "arm,primecell"; 3120 reg = <0 0x07740000 0 0x1000>; 3121 3122 cpu = <&CPU7>; 3123 3124 clocks = <&aoss_qmp>; 3125 clock-names = "apb_pclk"; 3126 arm,coresight-loses-context-with-cpu; 3127 qcom,skip-power-up; 3128 3129 out-ports { 3130 port { 3131 etm7_out: endpoint { 3132 remote-endpoint = <&apss_funnel_in7>; 3133 }; 3134 }; 3135 }; 3136 }; 3137 3138 funnel@7800000 { /* APSS Funnel */ 3139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3140 reg = <0 0x07800000 0 0x1000>; 3141 3142 clocks = <&aoss_qmp>; 3143 clock-names = "apb_pclk"; 3144 3145 out-ports { 3146 port { 3147 apss_funnel_out: endpoint { 3148 remote-endpoint = <&apss_merge_funnel_in>; 3149 }; 3150 }; 3151 }; 3152 3153 in-ports { 3154 #address-cells = <1>; 3155 #size-cells = <0>; 3156 3157 port@0 { 3158 reg = <0>; 3159 apss_funnel_in0: endpoint { 3160 remote-endpoint = <&etm0_out>; 3161 }; 3162 }; 3163 3164 port@1 { 3165 reg = <1>; 3166 apss_funnel_in1: endpoint { 3167 remote-endpoint = <&etm1_out>; 3168 }; 3169 }; 3170 3171 port@2 { 3172 reg = <2>; 3173 apss_funnel_in2: endpoint { 3174 remote-endpoint = <&etm2_out>; 3175 }; 3176 }; 3177 3178 port@3 { 3179 reg = <3>; 3180 apss_funnel_in3: endpoint { 3181 remote-endpoint = <&etm3_out>; 3182 }; 3183 }; 3184 3185 port@4 { 3186 reg = <4>; 3187 apss_funnel_in4: endpoint { 3188 remote-endpoint = <&etm4_out>; 3189 }; 3190 }; 3191 3192 port@5 { 3193 reg = <5>; 3194 apss_funnel_in5: endpoint { 3195 remote-endpoint = <&etm5_out>; 3196 }; 3197 }; 3198 3199 port@6 { 3200 reg = <6>; 3201 apss_funnel_in6: endpoint { 3202 remote-endpoint = <&etm6_out>; 3203 }; 3204 }; 3205 3206 port@7 { 3207 reg = <7>; 3208 apss_funnel_in7: endpoint { 3209 remote-endpoint = <&etm7_out>; 3210 }; 3211 }; 3212 }; 3213 }; 3214 3215 funnel@7810000 { 3216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3217 reg = <0 0x07810000 0 0x1000>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 3222 out-ports { 3223 port { 3224 apss_merge_funnel_out: endpoint { 3225 remote-endpoint = <&funnel1_in4>; 3226 }; 3227 }; 3228 }; 3229 3230 in-ports { 3231 port { 3232 apss_merge_funnel_in: endpoint { 3233 remote-endpoint = <&apss_funnel_out>; 3234 }; 3235 }; 3236 }; 3237 }; 3238 3239 sdhc_2: mmc@8804000 { 3240 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3241 pinctrl-names = "default", "sleep"; 3242 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3243 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3244 status = "disabled"; 3245 3246 reg = <0 0x08804000 0 0x1000>; 3247 3248 iommus = <&apps_smmu 0x100 0x0>; 3249 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3251 interrupt-names = "hc_irq", "pwr_irq"; 3252 3253 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3254 <&gcc GCC_SDCC2_APPS_CLK>, 3255 <&rpmhcc RPMH_CXO_CLK>; 3256 clock-names = "iface", "core", "xo"; 3257 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3258 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3259 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3260 power-domains = <&rpmhpd SC7280_CX>; 3261 operating-points-v2 = <&sdhc2_opp_table>; 3262 3263 bus-width = <4>; 3264 3265 qcom,dll-config = <0x0007642c>; 3266 3267 resets = <&gcc GCC_SDCC2_BCR>; 3268 3269 sdhc2_opp_table: opp-table { 3270 compatible = "operating-points-v2"; 3271 3272 opp-100000000 { 3273 opp-hz = /bits/ 64 <100000000>; 3274 required-opps = <&rpmhpd_opp_low_svs>; 3275 opp-peak-kBps = <1800000 400000>; 3276 opp-avg-kBps = <100000 0>; 3277 }; 3278 3279 opp-202000000 { 3280 opp-hz = /bits/ 64 <202000000>; 3281 required-opps = <&rpmhpd_opp_nom>; 3282 opp-peak-kBps = <5400000 1600000>; 3283 opp-avg-kBps = <200000 0>; 3284 }; 3285 }; 3286 3287 }; 3288 3289 usb_1_hsphy: phy@88e3000 { 3290 compatible = "qcom,sc7280-usb-hs-phy", 3291 "qcom,usb-snps-hs-7nm-phy"; 3292 reg = <0 0x088e3000 0 0x400>; 3293 status = "disabled"; 3294 #phy-cells = <0>; 3295 3296 clocks = <&rpmhcc RPMH_CXO_CLK>; 3297 clock-names = "ref"; 3298 3299 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3300 }; 3301 3302 usb_2_hsphy: phy@88e4000 { 3303 compatible = "qcom,sc7280-usb-hs-phy", 3304 "qcom,usb-snps-hs-7nm-phy"; 3305 reg = <0 0x088e4000 0 0x400>; 3306 status = "disabled"; 3307 #phy-cells = <0>; 3308 3309 clocks = <&rpmhcc RPMH_CXO_CLK>; 3310 clock-names = "ref"; 3311 3312 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3313 }; 3314 3315 usb_1_qmpphy: phy-wrapper@88e9000 { 3316 compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3317 "qcom,sm8250-qmp-usb3-dp-phy"; 3318 reg = <0 0x088e9000 0 0x200>, 3319 <0 0x088e8000 0 0x40>, 3320 <0 0x088ea000 0 0x200>; 3321 status = "disabled"; 3322 #address-cells = <2>; 3323 #size-cells = <2>; 3324 ranges; 3325 3326 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3327 <&rpmhcc RPMH_CXO_CLK>, 3328 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3329 clock-names = "aux", "ref_clk_src", "com_aux"; 3330 3331 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3332 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3333 reset-names = "phy", "common"; 3334 3335 usb_1_ssphy: usb3-phy@88e9200 { 3336 reg = <0 0x088e9200 0 0x200>, 3337 <0 0x088e9400 0 0x200>, 3338 <0 0x088e9c00 0 0x400>, 3339 <0 0x088e9600 0 0x200>, 3340 <0 0x088e9800 0 0x200>, 3341 <0 0x088e9a00 0 0x100>; 3342 #clock-cells = <0>; 3343 #phy-cells = <0>; 3344 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3345 clock-names = "pipe0"; 3346 clock-output-names = "usb3_phy_pipe_clk_src"; 3347 }; 3348 3349 dp_phy: dp-phy@88ea200 { 3350 reg = <0 0x088ea200 0 0x200>, 3351 <0 0x088ea400 0 0x200>, 3352 <0 0x088eaa00 0 0x200>, 3353 <0 0x088ea600 0 0x200>, 3354 <0 0x088ea800 0 0x200>; 3355 #phy-cells = <0>; 3356 #clock-cells = <1>; 3357 }; 3358 }; 3359 3360 usb_2: usb@8cf8800 { 3361 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3362 reg = <0 0x08cf8800 0 0x400>; 3363 status = "disabled"; 3364 #address-cells = <2>; 3365 #size-cells = <2>; 3366 ranges; 3367 dma-ranges; 3368 3369 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3370 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3371 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3372 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3373 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3374 clock-names = "cfg_noc", 3375 "core", 3376 "iface", 3377 "sleep", 3378 "mock_utmi"; 3379 3380 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3381 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3382 assigned-clock-rates = <19200000>, <200000000>; 3383 3384 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3385 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3386 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3387 interrupt-names = "hs_phy_irq", 3388 "dp_hs_phy_irq", 3389 "dm_hs_phy_irq"; 3390 3391 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3392 required-opps = <&rpmhpd_opp_nom>; 3393 3394 resets = <&gcc GCC_USB30_SEC_BCR>; 3395 3396 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3397 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3398 interconnect-names = "usb-ddr", "apps-usb"; 3399 3400 usb_2_dwc3: usb@8c00000 { 3401 compatible = "snps,dwc3"; 3402 reg = <0 0x08c00000 0 0xe000>; 3403 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3404 iommus = <&apps_smmu 0xa0 0x0>; 3405 snps,dis_u2_susphy_quirk; 3406 snps,dis_enblslpm_quirk; 3407 phys = <&usb_2_hsphy>; 3408 phy-names = "usb2-phy"; 3409 maximum-speed = "high-speed"; 3410 usb-role-switch; 3411 port { 3412 usb2_role_switch: endpoint { 3413 remote-endpoint = <&eud_ep>; 3414 }; 3415 }; 3416 }; 3417 }; 3418 3419 qspi: spi@88dc000 { 3420 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3421 reg = <0 0x088dc000 0 0x1000>; 3422 #address-cells = <1>; 3423 #size-cells = <0>; 3424 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3425 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3426 <&gcc GCC_QSPI_CORE_CLK>; 3427 clock-names = "iface", "core"; 3428 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3429 &cnoc2 SLAVE_QSPI_0 0>; 3430 interconnect-names = "qspi-config"; 3431 power-domains = <&rpmhpd SC7280_CX>; 3432 operating-points-v2 = <&qspi_opp_table>; 3433 status = "disabled"; 3434 }; 3435 3436 remoteproc_wpss: remoteproc@8a00000 { 3437 compatible = "qcom,sc7280-wpss-pil"; 3438 reg = <0 0x08a00000 0 0x10000>; 3439 3440 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3441 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3442 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3443 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3444 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3445 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3446 interrupt-names = "wdog", "fatal", "ready", "handover", 3447 "stop-ack", "shutdown-ack"; 3448 3449 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3450 <&gcc GCC_WPSS_AHB_CLK>, 3451 <&gcc GCC_WPSS_RSCP_CLK>, 3452 <&rpmhcc RPMH_CXO_CLK>; 3453 clock-names = "ahb_bdg", "ahb", 3454 "rscp", "xo"; 3455 3456 power-domains = <&rpmhpd SC7280_CX>, 3457 <&rpmhpd SC7280_MX>; 3458 power-domain-names = "cx", "mx"; 3459 3460 memory-region = <&wpss_mem>; 3461 3462 qcom,qmp = <&aoss_qmp>; 3463 3464 qcom,smem-states = <&wpss_smp2p_out 0>; 3465 qcom,smem-state-names = "stop"; 3466 3467 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3468 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3469 reset-names = "restart", "pdc_sync"; 3470 3471 qcom,halt-regs = <&tcsr_1 0x17000>; 3472 3473 status = "disabled"; 3474 3475 glink-edge { 3476 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3477 IPCC_MPROC_SIGNAL_GLINK_QMP 3478 IRQ_TYPE_EDGE_RISING>; 3479 mboxes = <&ipcc IPCC_CLIENT_WPSS 3480 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3481 3482 label = "wpss"; 3483 qcom,remote-pid = <13>; 3484 }; 3485 }; 3486 3487 pmu@9091000 { 3488 compatible = "qcom,sc7280-llcc-bwmon"; 3489 reg = <0 0x9091000 0 0x1000>; 3490 3491 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3492 3493 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3494 3495 operating-points-v2 = <&llcc_bwmon_opp_table>; 3496 3497 llcc_bwmon_opp_table: opp-table { 3498 compatible = "operating-points-v2"; 3499 3500 opp-0 { 3501 opp-peak-kBps = <800000>; 3502 }; 3503 opp-1 { 3504 opp-peak-kBps = <1804000>; 3505 }; 3506 opp-2 { 3507 opp-peak-kBps = <2188000>; 3508 }; 3509 opp-3 { 3510 opp-peak-kBps = <3072000>; 3511 }; 3512 opp-4 { 3513 opp-peak-kBps = <4068000>; 3514 }; 3515 opp-5 { 3516 opp-peak-kBps = <6220000>; 3517 }; 3518 opp-6 { 3519 opp-peak-kBps = <6832000>; 3520 }; 3521 opp-7 { 3522 opp-peak-kBps = <8532000>; 3523 }; 3524 }; 3525 }; 3526 3527 pmu@90b6400 { 3528 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; 3529 reg = <0 0x090b6400 0 0x600>; 3530 3531 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3532 3533 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3534 operating-points-v2 = <&cpu_bwmon_opp_table>; 3535 3536 cpu_bwmon_opp_table: opp-table { 3537 compatible = "operating-points-v2"; 3538 3539 opp-0 { 3540 opp-peak-kBps = <2400000>; 3541 }; 3542 opp-1 { 3543 opp-peak-kBps = <4800000>; 3544 }; 3545 opp-2 { 3546 opp-peak-kBps = <7456000>; 3547 }; 3548 opp-3 { 3549 opp-peak-kBps = <9600000>; 3550 }; 3551 opp-4 { 3552 opp-peak-kBps = <12896000>; 3553 }; 3554 opp-5 { 3555 opp-peak-kBps = <14928000>; 3556 }; 3557 opp-6 { 3558 opp-peak-kBps = <17056000>; 3559 }; 3560 }; 3561 }; 3562 3563 dc_noc: interconnect@90e0000 { 3564 reg = <0 0x090e0000 0 0x5080>; 3565 compatible = "qcom,sc7280-dc-noc"; 3566 #interconnect-cells = <2>; 3567 qcom,bcm-voters = <&apps_bcm_voter>; 3568 }; 3569 3570 gem_noc: interconnect@9100000 { 3571 reg = <0 0x9100000 0 0xe2200>; 3572 compatible = "qcom,sc7280-gem-noc"; 3573 #interconnect-cells = <2>; 3574 qcom,bcm-voters = <&apps_bcm_voter>; 3575 }; 3576 3577 system-cache-controller@9200000 { 3578 compatible = "qcom,sc7280-llcc"; 3579 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; 3580 reg-names = "llcc_base", "llcc_broadcast_base"; 3581 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3582 }; 3583 3584 eud: eud@88e0000 { 3585 compatible = "qcom,sc7280-eud","qcom,eud"; 3586 reg = <0 0x88e0000 0 0x2000>, 3587 <0 0x88e2000 0 0x1000>; 3588 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3589 ports { 3590 port@0 { 3591 eud_ep: endpoint { 3592 remote-endpoint = <&usb2_role_switch>; 3593 }; 3594 }; 3595 port@1 { 3596 eud_con: endpoint { 3597 remote-endpoint = <&con_eud>; 3598 }; 3599 }; 3600 }; 3601 }; 3602 3603 eud_typec: connector { 3604 compatible = "usb-c-connector"; 3605 ports { 3606 port@0 { 3607 con_eud: endpoint { 3608 remote-endpoint = <&eud_con>; 3609 }; 3610 }; 3611 }; 3612 }; 3613 3614 nsp_noc: interconnect@a0c0000 { 3615 reg = <0 0x0a0c0000 0 0x10000>; 3616 compatible = "qcom,sc7280-nsp-noc"; 3617 #interconnect-cells = <2>; 3618 qcom,bcm-voters = <&apps_bcm_voter>; 3619 }; 3620 3621 usb_1: usb@a6f8800 { 3622 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3623 reg = <0 0x0a6f8800 0 0x400>; 3624 status = "disabled"; 3625 #address-cells = <2>; 3626 #size-cells = <2>; 3627 ranges; 3628 dma-ranges; 3629 3630 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3631 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3632 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3633 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3634 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3635 clock-names = "cfg_noc", 3636 "core", 3637 "iface", 3638 "sleep", 3639 "mock_utmi"; 3640 3641 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3642 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3643 assigned-clock-rates = <19200000>, <200000000>; 3644 3645 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3646 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3647 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3648 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3649 interrupt-names = "hs_phy_irq", 3650 "dp_hs_phy_irq", 3651 "dm_hs_phy_irq", 3652 "ss_phy_irq"; 3653 3654 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3655 required-opps = <&rpmhpd_opp_nom>; 3656 3657 resets = <&gcc GCC_USB30_PRIM_BCR>; 3658 3659 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3660 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3661 interconnect-names = "usb-ddr", "apps-usb"; 3662 3663 wakeup-source; 3664 3665 usb_1_dwc3: usb@a600000 { 3666 compatible = "snps,dwc3"; 3667 reg = <0 0x0a600000 0 0xe000>; 3668 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3669 iommus = <&apps_smmu 0xe0 0x0>; 3670 snps,dis_u2_susphy_quirk; 3671 snps,dis_enblslpm_quirk; 3672 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3673 phy-names = "usb2-phy", "usb3-phy"; 3674 maximum-speed = "super-speed"; 3675 }; 3676 }; 3677 3678 venus: video-codec@aa00000 { 3679 compatible = "qcom,sc7280-venus"; 3680 reg = <0 0x0aa00000 0 0xd0600>; 3681 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3682 3683 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3684 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3685 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3686 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3687 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3688 clock-names = "core", "bus", "iface", 3689 "vcodec_core", "vcodec_bus"; 3690 3691 power-domains = <&videocc MVSC_GDSC>, 3692 <&videocc MVS0_GDSC>, 3693 <&rpmhpd SC7280_CX>; 3694 power-domain-names = "venus", "vcodec0", "cx"; 3695 operating-points-v2 = <&venus_opp_table>; 3696 3697 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3698 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3699 interconnect-names = "cpu-cfg", "video-mem"; 3700 3701 iommus = <&apps_smmu 0x2180 0x20>, 3702 <&apps_smmu 0x2184 0x20>; 3703 memory-region = <&video_mem>; 3704 3705 video-decoder { 3706 compatible = "venus-decoder"; 3707 }; 3708 3709 video-encoder { 3710 compatible = "venus-encoder"; 3711 }; 3712 3713 video-firmware { 3714 iommus = <&apps_smmu 0x21a2 0x0>; 3715 }; 3716 3717 venus_opp_table: opp-table { 3718 compatible = "operating-points-v2"; 3719 3720 opp-133330000 { 3721 opp-hz = /bits/ 64 <133330000>; 3722 required-opps = <&rpmhpd_opp_low_svs>; 3723 }; 3724 3725 opp-240000000 { 3726 opp-hz = /bits/ 64 <240000000>; 3727 required-opps = <&rpmhpd_opp_svs>; 3728 }; 3729 3730 opp-335000000 { 3731 opp-hz = /bits/ 64 <335000000>; 3732 required-opps = <&rpmhpd_opp_svs_l1>; 3733 }; 3734 3735 opp-424000000 { 3736 opp-hz = /bits/ 64 <424000000>; 3737 required-opps = <&rpmhpd_opp_nom>; 3738 }; 3739 3740 opp-460000048 { 3741 opp-hz = /bits/ 64 <460000048>; 3742 required-opps = <&rpmhpd_opp_turbo>; 3743 }; 3744 }; 3745 3746 }; 3747 3748 videocc: clock-controller@aaf0000 { 3749 compatible = "qcom,sc7280-videocc"; 3750 reg = <0 0xaaf0000 0 0x10000>; 3751 clocks = <&rpmhcc RPMH_CXO_CLK>, 3752 <&rpmhcc RPMH_CXO_CLK_A>; 3753 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3754 #clock-cells = <1>; 3755 #reset-cells = <1>; 3756 #power-domain-cells = <1>; 3757 }; 3758 3759 camcc: clock-controller@ad00000 { 3760 compatible = "qcom,sc7280-camcc"; 3761 reg = <0 0x0ad00000 0 0x10000>; 3762 clocks = <&rpmhcc RPMH_CXO_CLK>, 3763 <&rpmhcc RPMH_CXO_CLK_A>, 3764 <&sleep_clk>; 3765 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3766 #clock-cells = <1>; 3767 #reset-cells = <1>; 3768 #power-domain-cells = <1>; 3769 }; 3770 3771 dispcc: clock-controller@af00000 { 3772 compatible = "qcom,sc7280-dispcc"; 3773 reg = <0 0xaf00000 0 0x20000>; 3774 clocks = <&rpmhcc RPMH_CXO_CLK>, 3775 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3776 <&mdss_dsi_phy 0>, 3777 <&mdss_dsi_phy 1>, 3778 <&dp_phy 0>, 3779 <&dp_phy 1>, 3780 <&mdss_edp_phy 0>, 3781 <&mdss_edp_phy 1>; 3782 clock-names = "bi_tcxo", 3783 "gcc_disp_gpll0_clk", 3784 "dsi0_phy_pll_out_byteclk", 3785 "dsi0_phy_pll_out_dsiclk", 3786 "dp_phy_pll_link_clk", 3787 "dp_phy_pll_vco_div_clk", 3788 "edp_phy_pll_link_clk", 3789 "edp_phy_pll_vco_div_clk"; 3790 #clock-cells = <1>; 3791 #reset-cells = <1>; 3792 #power-domain-cells = <1>; 3793 }; 3794 3795 mdss: display-subsystem@ae00000 { 3796 compatible = "qcom,sc7280-mdss"; 3797 reg = <0 0x0ae00000 0 0x1000>; 3798 reg-names = "mdss"; 3799 3800 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3801 3802 clocks = <&gcc GCC_DISP_AHB_CLK>, 3803 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3804 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3805 clock-names = "iface", 3806 "ahb", 3807 "core"; 3808 3809 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3810 interrupt-controller; 3811 #interrupt-cells = <1>; 3812 3813 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3814 interconnect-names = "mdp0-mem"; 3815 3816 iommus = <&apps_smmu 0x900 0x402>; 3817 3818 #address-cells = <2>; 3819 #size-cells = <2>; 3820 ranges; 3821 3822 status = "disabled"; 3823 3824 mdss_mdp: display-controller@ae01000 { 3825 compatible = "qcom,sc7280-dpu"; 3826 reg = <0 0x0ae01000 0 0x8f030>, 3827 <0 0x0aeb0000 0 0x2008>; 3828 reg-names = "mdp", "vbif"; 3829 3830 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3831 <&gcc GCC_DISP_SF_AXI_CLK>, 3832 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3833 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3834 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3835 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3836 clock-names = "bus", 3837 "nrt_bus", 3838 "iface", 3839 "lut", 3840 "core", 3841 "vsync"; 3842 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3843 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3844 assigned-clock-rates = <19200000>, 3845 <19200000>; 3846 operating-points-v2 = <&mdp_opp_table>; 3847 power-domains = <&rpmhpd SC7280_CX>; 3848 3849 interrupt-parent = <&mdss>; 3850 interrupts = <0>; 3851 3852 status = "disabled"; 3853 3854 ports { 3855 #address-cells = <1>; 3856 #size-cells = <0>; 3857 3858 port@0 { 3859 reg = <0>; 3860 dpu_intf1_out: endpoint { 3861 remote-endpoint = <&dsi0_in>; 3862 }; 3863 }; 3864 3865 port@1 { 3866 reg = <1>; 3867 dpu_intf5_out: endpoint { 3868 remote-endpoint = <&edp_in>; 3869 }; 3870 }; 3871 3872 port@2 { 3873 reg = <2>; 3874 dpu_intf0_out: endpoint { 3875 remote-endpoint = <&dp_in>; 3876 }; 3877 }; 3878 }; 3879 3880 mdp_opp_table: opp-table { 3881 compatible = "operating-points-v2"; 3882 3883 opp-200000000 { 3884 opp-hz = /bits/ 64 <200000000>; 3885 required-opps = <&rpmhpd_opp_low_svs>; 3886 }; 3887 3888 opp-300000000 { 3889 opp-hz = /bits/ 64 <300000000>; 3890 required-opps = <&rpmhpd_opp_svs>; 3891 }; 3892 3893 opp-380000000 { 3894 opp-hz = /bits/ 64 <380000000>; 3895 required-opps = <&rpmhpd_opp_svs_l1>; 3896 }; 3897 3898 opp-506666667 { 3899 opp-hz = /bits/ 64 <506666667>; 3900 required-opps = <&rpmhpd_opp_nom>; 3901 }; 3902 }; 3903 }; 3904 3905 mdss_dsi: dsi@ae94000 { 3906 compatible = "qcom,mdss-dsi-ctrl"; 3907 reg = <0 0x0ae94000 0 0x400>; 3908 reg-names = "dsi_ctrl"; 3909 3910 interrupt-parent = <&mdss>; 3911 interrupts = <4>; 3912 3913 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3914 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3915 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3916 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3917 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3918 <&gcc GCC_DISP_HF_AXI_CLK>; 3919 clock-names = "byte", 3920 "byte_intf", 3921 "pixel", 3922 "core", 3923 "iface", 3924 "bus"; 3925 3926 operating-points-v2 = <&dsi_opp_table>; 3927 power-domains = <&rpmhpd SC7280_CX>; 3928 3929 phys = <&mdss_dsi_phy>; 3930 phy-names = "dsi"; 3931 3932 #address-cells = <1>; 3933 #size-cells = <0>; 3934 3935 status = "disabled"; 3936 3937 ports { 3938 #address-cells = <1>; 3939 #size-cells = <0>; 3940 3941 port@0 { 3942 reg = <0>; 3943 dsi0_in: endpoint { 3944 remote-endpoint = <&dpu_intf1_out>; 3945 }; 3946 }; 3947 3948 port@1 { 3949 reg = <1>; 3950 dsi0_out: endpoint { 3951 }; 3952 }; 3953 }; 3954 3955 dsi_opp_table: opp-table { 3956 compatible = "operating-points-v2"; 3957 3958 opp-187500000 { 3959 opp-hz = /bits/ 64 <187500000>; 3960 required-opps = <&rpmhpd_opp_low_svs>; 3961 }; 3962 3963 opp-300000000 { 3964 opp-hz = /bits/ 64 <300000000>; 3965 required-opps = <&rpmhpd_opp_svs>; 3966 }; 3967 3968 opp-358000000 { 3969 opp-hz = /bits/ 64 <358000000>; 3970 required-opps = <&rpmhpd_opp_svs_l1>; 3971 }; 3972 }; 3973 }; 3974 3975 mdss_dsi_phy: phy@ae94400 { 3976 compatible = "qcom,sc7280-dsi-phy-7nm"; 3977 reg = <0 0x0ae94400 0 0x200>, 3978 <0 0x0ae94600 0 0x280>, 3979 <0 0x0ae94900 0 0x280>; 3980 reg-names = "dsi_phy", 3981 "dsi_phy_lane", 3982 "dsi_pll"; 3983 3984 #clock-cells = <1>; 3985 #phy-cells = <0>; 3986 3987 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3988 <&rpmhcc RPMH_CXO_CLK>; 3989 clock-names = "iface", "ref"; 3990 3991 status = "disabled"; 3992 }; 3993 3994 mdss_edp: edp@aea0000 { 3995 compatible = "qcom,sc7280-edp"; 3996 pinctrl-names = "default"; 3997 pinctrl-0 = <&edp_hot_plug_det>; 3998 3999 reg = <0 0xaea0000 0 0x200>, 4000 <0 0xaea0200 0 0x200>, 4001 <0 0xaea0400 0 0xc00>, 4002 <0 0xaea1000 0 0x400>; 4003 4004 interrupt-parent = <&mdss>; 4005 interrupts = <14>; 4006 4007 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4008 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4009 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4010 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4011 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4012 clock-names = "core_iface", 4013 "core_aux", 4014 "ctrl_link", 4015 "ctrl_link_iface", 4016 "stream_pixel"; 4017 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4018 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4019 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4020 4021 phys = <&mdss_edp_phy>; 4022 phy-names = "dp"; 4023 4024 operating-points-v2 = <&edp_opp_table>; 4025 power-domains = <&rpmhpd SC7280_CX>; 4026 4027 status = "disabled"; 4028 4029 ports { 4030 #address-cells = <1>; 4031 #size-cells = <0>; 4032 4033 port@0 { 4034 reg = <0>; 4035 edp_in: endpoint { 4036 remote-endpoint = <&dpu_intf5_out>; 4037 }; 4038 }; 4039 4040 port@1 { 4041 reg = <1>; 4042 mdss_edp_out: endpoint { }; 4043 }; 4044 }; 4045 4046 edp_opp_table: opp-table { 4047 compatible = "operating-points-v2"; 4048 4049 opp-160000000 { 4050 opp-hz = /bits/ 64 <160000000>; 4051 required-opps = <&rpmhpd_opp_low_svs>; 4052 }; 4053 4054 opp-270000000 { 4055 opp-hz = /bits/ 64 <270000000>; 4056 required-opps = <&rpmhpd_opp_svs>; 4057 }; 4058 4059 opp-540000000 { 4060 opp-hz = /bits/ 64 <540000000>; 4061 required-opps = <&rpmhpd_opp_nom>; 4062 }; 4063 4064 opp-810000000 { 4065 opp-hz = /bits/ 64 <810000000>; 4066 required-opps = <&rpmhpd_opp_nom>; 4067 }; 4068 }; 4069 }; 4070 4071 mdss_edp_phy: phy@aec2a00 { 4072 compatible = "qcom,sc7280-edp-phy"; 4073 4074 reg = <0 0xaec2a00 0 0x19c>, 4075 <0 0xaec2200 0 0xa0>, 4076 <0 0xaec2600 0 0xa0>, 4077 <0 0xaec2000 0 0x1c0>; 4078 4079 clocks = <&rpmhcc RPMH_CXO_CLK>, 4080 <&gcc GCC_EDP_CLKREF_EN>; 4081 clock-names = "aux", 4082 "cfg_ahb"; 4083 4084 #clock-cells = <1>; 4085 #phy-cells = <0>; 4086 4087 status = "disabled"; 4088 }; 4089 4090 mdss_dp: displayport-controller@ae90000 { 4091 compatible = "qcom,sc7280-dp"; 4092 4093 reg = <0 0xae90000 0 0x200>, 4094 <0 0xae90200 0 0x200>, 4095 <0 0xae90400 0 0xc00>, 4096 <0 0xae91000 0 0x400>, 4097 <0 0xae91400 0 0x400>; 4098 4099 interrupt-parent = <&mdss>; 4100 interrupts = <12>; 4101 4102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4103 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4104 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4105 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4106 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4107 clock-names = "core_iface", 4108 "core_aux", 4109 "ctrl_link", 4110 "ctrl_link_iface", 4111 "stream_pixel"; 4112 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4113 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4114 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 4115 phys = <&dp_phy>; 4116 phy-names = "dp"; 4117 4118 operating-points-v2 = <&dp_opp_table>; 4119 power-domains = <&rpmhpd SC7280_CX>; 4120 4121 #sound-dai-cells = <0>; 4122 4123 status = "disabled"; 4124 4125 ports { 4126 #address-cells = <1>; 4127 #size-cells = <0>; 4128 4129 port@0 { 4130 reg = <0>; 4131 dp_in: endpoint { 4132 remote-endpoint = <&dpu_intf0_out>; 4133 }; 4134 }; 4135 4136 port@1 { 4137 reg = <1>; 4138 dp_out: endpoint { }; 4139 }; 4140 }; 4141 4142 dp_opp_table: opp-table { 4143 compatible = "operating-points-v2"; 4144 4145 opp-160000000 { 4146 opp-hz = /bits/ 64 <160000000>; 4147 required-opps = <&rpmhpd_opp_low_svs>; 4148 }; 4149 4150 opp-270000000 { 4151 opp-hz = /bits/ 64 <270000000>; 4152 required-opps = <&rpmhpd_opp_svs>; 4153 }; 4154 4155 opp-540000000 { 4156 opp-hz = /bits/ 64 <540000000>; 4157 required-opps = <&rpmhpd_opp_svs_l1>; 4158 }; 4159 4160 opp-810000000 { 4161 opp-hz = /bits/ 64 <810000000>; 4162 required-opps = <&rpmhpd_opp_nom>; 4163 }; 4164 }; 4165 }; 4166 }; 4167 4168 pdc: interrupt-controller@b220000 { 4169 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4170 reg = <0 0x0b220000 0 0x30000>; 4171 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4172 <55 306 4>, <59 312 3>, <62 374 2>, 4173 <64 434 2>, <66 438 3>, <69 86 1>, 4174 <70 520 54>, <124 609 31>, <155 63 1>, 4175 <156 716 12>; 4176 #interrupt-cells = <2>; 4177 interrupt-parent = <&intc>; 4178 interrupt-controller; 4179 }; 4180 4181 pdc_reset: reset-controller@b5e0000 { 4182 compatible = "qcom,sc7280-pdc-global"; 4183 reg = <0 0x0b5e0000 0 0x20000>; 4184 #reset-cells = <1>; 4185 }; 4186 4187 tsens0: thermal-sensor@c263000 { 4188 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4189 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4190 <0 0x0c222000 0 0x1ff>; /* SROT */ 4191 #qcom,sensors = <15>; 4192 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4194 interrupt-names = "uplow","critical"; 4195 #thermal-sensor-cells = <1>; 4196 }; 4197 4198 tsens1: thermal-sensor@c265000 { 4199 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4200 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4201 <0 0x0c223000 0 0x1ff>; /* SROT */ 4202 #qcom,sensors = <12>; 4203 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4205 interrupt-names = "uplow","critical"; 4206 #thermal-sensor-cells = <1>; 4207 }; 4208 4209 aoss_reset: reset-controller@c2a0000 { 4210 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4211 reg = <0 0x0c2a0000 0 0x31000>; 4212 #reset-cells = <1>; 4213 }; 4214 4215 aoss_qmp: power-controller@c300000 { 4216 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4217 reg = <0 0x0c300000 0 0x400>; 4218 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4219 IPCC_MPROC_SIGNAL_GLINK_QMP 4220 IRQ_TYPE_EDGE_RISING>; 4221 mboxes = <&ipcc IPCC_CLIENT_AOP 4222 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4223 4224 #clock-cells = <0>; 4225 }; 4226 4227 sram@c3f0000 { 4228 compatible = "qcom,rpmh-stats"; 4229 reg = <0 0x0c3f0000 0 0x400>; 4230 }; 4231 4232 spmi_bus: spmi@c440000 { 4233 compatible = "qcom,spmi-pmic-arb"; 4234 reg = <0 0x0c440000 0 0x1100>, 4235 <0 0x0c600000 0 0x2000000>, 4236 <0 0x0e600000 0 0x100000>, 4237 <0 0x0e700000 0 0xa0000>, 4238 <0 0x0c40a000 0 0x26000>; 4239 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4240 interrupt-names = "periph_irq"; 4241 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4242 qcom,ee = <0>; 4243 qcom,channel = <0>; 4244 #address-cells = <1>; 4245 #size-cells = <1>; 4246 interrupt-controller; 4247 #interrupt-cells = <4>; 4248 }; 4249 4250 tlmm: pinctrl@f100000 { 4251 compatible = "qcom,sc7280-pinctrl"; 4252 reg = <0 0x0f100000 0 0x300000>; 4253 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4254 gpio-controller; 4255 #gpio-cells = <2>; 4256 interrupt-controller; 4257 #interrupt-cells = <2>; 4258 gpio-ranges = <&tlmm 0 0 175>; 4259 wakeup-parent = <&pdc>; 4260 4261 dp_hot_plug_det: dp-hot-plug-det-pins { 4262 pins = "gpio47"; 4263 function = "dp_hot"; 4264 }; 4265 4266 edp_hot_plug_det: edp-hot-plug-det-pins { 4267 pins = "gpio60"; 4268 function = "edp_hot"; 4269 }; 4270 4271 mi2s0_data0: mi2s0-data0-pins { 4272 pins = "gpio98"; 4273 function = "mi2s0_data0"; 4274 }; 4275 4276 mi2s0_data1: mi2s0-data1-pins { 4277 pins = "gpio99"; 4278 function = "mi2s0_data1"; 4279 }; 4280 4281 mi2s0_mclk: mi2s0-mclk-pins { 4282 pins = "gpio96"; 4283 function = "pri_mi2s"; 4284 }; 4285 4286 mi2s0_sclk: mi2s0-sclk-pins { 4287 pins = "gpio97"; 4288 function = "mi2s0_sck"; 4289 }; 4290 4291 mi2s0_ws: mi2s0-ws-pins { 4292 pins = "gpio100"; 4293 function = "mi2s0_ws"; 4294 }; 4295 4296 mi2s1_data0: mi2s1-data0-pins { 4297 pins = "gpio107"; 4298 function = "mi2s1_data0"; 4299 }; 4300 4301 mi2s1_sclk: mi2s1-sclk-pins { 4302 pins = "gpio106"; 4303 function = "mi2s1_sck"; 4304 }; 4305 4306 mi2s1_ws: mi2s1-ws-pins { 4307 pins = "gpio108"; 4308 function = "mi2s1_ws"; 4309 }; 4310 4311 pcie1_clkreq_n: pcie1-clkreq-n-pins { 4312 pins = "gpio79"; 4313 function = "pcie1_clkreqn"; 4314 }; 4315 4316 qspi_clk: qspi-clk-pins { 4317 pins = "gpio14"; 4318 function = "qspi_clk"; 4319 }; 4320 4321 qspi_cs0: qspi-cs0-pins { 4322 pins = "gpio15"; 4323 function = "qspi_cs"; 4324 }; 4325 4326 qspi_cs1: qspi-cs1-pins { 4327 pins = "gpio19"; 4328 function = "qspi_cs"; 4329 }; 4330 4331 qspi_data01: qspi-data01-pins { 4332 pins = "gpio12", "gpio13"; 4333 function = "qspi_data"; 4334 }; 4335 4336 qspi_data12: qspi-data12-pins { 4337 pins = "gpio16", "gpio17"; 4338 function = "qspi_data"; 4339 }; 4340 4341 qup_i2c0_data_clk: qup-i2c0-data-clk-pins { 4342 pins = "gpio0", "gpio1"; 4343 function = "qup00"; 4344 }; 4345 4346 qup_i2c1_data_clk: qup-i2c1-data-clk-pins { 4347 pins = "gpio4", "gpio5"; 4348 function = "qup01"; 4349 }; 4350 4351 qup_i2c2_data_clk: qup-i2c2-data-clk-pins { 4352 pins = "gpio8", "gpio9"; 4353 function = "qup02"; 4354 }; 4355 4356 qup_i2c3_data_clk: qup-i2c3-data-clk-pins { 4357 pins = "gpio12", "gpio13"; 4358 function = "qup03"; 4359 }; 4360 4361 qup_i2c4_data_clk: qup-i2c4-data-clk-pins { 4362 pins = "gpio16", "gpio17"; 4363 function = "qup04"; 4364 }; 4365 4366 qup_i2c5_data_clk: qup-i2c5-data-clk-pins { 4367 pins = "gpio20", "gpio21"; 4368 function = "qup05"; 4369 }; 4370 4371 qup_i2c6_data_clk: qup-i2c6-data-clk-pins { 4372 pins = "gpio24", "gpio25"; 4373 function = "qup06"; 4374 }; 4375 4376 qup_i2c7_data_clk: qup-i2c7-data-clk-pins { 4377 pins = "gpio28", "gpio29"; 4378 function = "qup07"; 4379 }; 4380 4381 qup_i2c8_data_clk: qup-i2c8-data-clk-pins { 4382 pins = "gpio32", "gpio33"; 4383 function = "qup10"; 4384 }; 4385 4386 qup_i2c9_data_clk: qup-i2c9-data-clk-pins { 4387 pins = "gpio36", "gpio37"; 4388 function = "qup11"; 4389 }; 4390 4391 qup_i2c10_data_clk: qup-i2c10-data-clk-pins { 4392 pins = "gpio40", "gpio41"; 4393 function = "qup12"; 4394 }; 4395 4396 qup_i2c11_data_clk: qup-i2c11-data-clk-pins { 4397 pins = "gpio44", "gpio45"; 4398 function = "qup13"; 4399 }; 4400 4401 qup_i2c12_data_clk: qup-i2c12-data-clk-pins { 4402 pins = "gpio48", "gpio49"; 4403 function = "qup14"; 4404 }; 4405 4406 qup_i2c13_data_clk: qup-i2c13-data-clk-pins { 4407 pins = "gpio52", "gpio53"; 4408 function = "qup15"; 4409 }; 4410 4411 qup_i2c14_data_clk: qup-i2c14-data-clk-pins { 4412 pins = "gpio56", "gpio57"; 4413 function = "qup16"; 4414 }; 4415 4416 qup_i2c15_data_clk: qup-i2c15-data-clk-pins { 4417 pins = "gpio60", "gpio61"; 4418 function = "qup17"; 4419 }; 4420 4421 qup_spi0_data_clk: qup-spi0-data-clk-pins { 4422 pins = "gpio0", "gpio1", "gpio2"; 4423 function = "qup00"; 4424 }; 4425 4426 qup_spi0_cs: qup-spi0-cs-pins { 4427 pins = "gpio3"; 4428 function = "qup00"; 4429 }; 4430 4431 qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins { 4432 pins = "gpio3"; 4433 function = "gpio"; 4434 }; 4435 4436 qup_spi1_data_clk: qup-spi1-data-clk-pins { 4437 pins = "gpio4", "gpio5", "gpio6"; 4438 function = "qup01"; 4439 }; 4440 4441 qup_spi1_cs: qup-spi1-cs-pins { 4442 pins = "gpio7"; 4443 function = "qup01"; 4444 }; 4445 4446 qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins { 4447 pins = "gpio7"; 4448 function = "gpio"; 4449 }; 4450 4451 qup_spi2_data_clk: qup-spi2-data-clk-pins { 4452 pins = "gpio8", "gpio9", "gpio10"; 4453 function = "qup02"; 4454 }; 4455 4456 qup_spi2_cs: qup-spi2-cs-pins { 4457 pins = "gpio11"; 4458 function = "qup02"; 4459 }; 4460 4461 qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins { 4462 pins = "gpio11"; 4463 function = "gpio"; 4464 }; 4465 4466 qup_spi3_data_clk: qup-spi3-data-clk-pins { 4467 pins = "gpio12", "gpio13", "gpio14"; 4468 function = "qup03"; 4469 }; 4470 4471 qup_spi3_cs: qup-spi3-cs-pins { 4472 pins = "gpio15"; 4473 function = "qup03"; 4474 }; 4475 4476 qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins { 4477 pins = "gpio15"; 4478 function = "gpio"; 4479 }; 4480 4481 qup_spi4_data_clk: qup-spi4-data-clk-pins { 4482 pins = "gpio16", "gpio17", "gpio18"; 4483 function = "qup04"; 4484 }; 4485 4486 qup_spi4_cs: qup-spi4-cs-pins { 4487 pins = "gpio19"; 4488 function = "qup04"; 4489 }; 4490 4491 qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins { 4492 pins = "gpio19"; 4493 function = "gpio"; 4494 }; 4495 4496 qup_spi5_data_clk: qup-spi5-data-clk-pins { 4497 pins = "gpio20", "gpio21", "gpio22"; 4498 function = "qup05"; 4499 }; 4500 4501 qup_spi5_cs: qup-spi5-cs-pins { 4502 pins = "gpio23"; 4503 function = "qup05"; 4504 }; 4505 4506 qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins { 4507 pins = "gpio23"; 4508 function = "gpio"; 4509 }; 4510 4511 qup_spi6_data_clk: qup-spi6-data-clk-pins { 4512 pins = "gpio24", "gpio25", "gpio26"; 4513 function = "qup06"; 4514 }; 4515 4516 qup_spi6_cs: qup-spi6-cs-pins { 4517 pins = "gpio27"; 4518 function = "qup06"; 4519 }; 4520 4521 qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins { 4522 pins = "gpio27"; 4523 function = "gpio"; 4524 }; 4525 4526 qup_spi7_data_clk: qup-spi7-data-clk-pins { 4527 pins = "gpio28", "gpio29", "gpio30"; 4528 function = "qup07"; 4529 }; 4530 4531 qup_spi7_cs: qup-spi7-cs-pins { 4532 pins = "gpio31"; 4533 function = "qup07"; 4534 }; 4535 4536 qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins { 4537 pins = "gpio31"; 4538 function = "gpio"; 4539 }; 4540 4541 qup_spi8_data_clk: qup-spi8-data-clk-pins { 4542 pins = "gpio32", "gpio33", "gpio34"; 4543 function = "qup10"; 4544 }; 4545 4546 qup_spi8_cs: qup-spi8-cs-pins { 4547 pins = "gpio35"; 4548 function = "qup10"; 4549 }; 4550 4551 qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins { 4552 pins = "gpio35"; 4553 function = "gpio"; 4554 }; 4555 4556 qup_spi9_data_clk: qup-spi9-data-clk-pins { 4557 pins = "gpio36", "gpio37", "gpio38"; 4558 function = "qup11"; 4559 }; 4560 4561 qup_spi9_cs: qup-spi9-cs-pins { 4562 pins = "gpio39"; 4563 function = "qup11"; 4564 }; 4565 4566 qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins { 4567 pins = "gpio39"; 4568 function = "gpio"; 4569 }; 4570 4571 qup_spi10_data_clk: qup-spi10-data-clk-pins { 4572 pins = "gpio40", "gpio41", "gpio42"; 4573 function = "qup12"; 4574 }; 4575 4576 qup_spi10_cs: qup-spi10-cs-pins { 4577 pins = "gpio43"; 4578 function = "qup12"; 4579 }; 4580 4581 qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins { 4582 pins = "gpio43"; 4583 function = "gpio"; 4584 }; 4585 4586 qup_spi11_data_clk: qup-spi11-data-clk-pins { 4587 pins = "gpio44", "gpio45", "gpio46"; 4588 function = "qup13"; 4589 }; 4590 4591 qup_spi11_cs: qup-spi11-cs-pins { 4592 pins = "gpio47"; 4593 function = "qup13"; 4594 }; 4595 4596 qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins { 4597 pins = "gpio47"; 4598 function = "gpio"; 4599 }; 4600 4601 qup_spi12_data_clk: qup-spi12-data-clk-pins { 4602 pins = "gpio48", "gpio49", "gpio50"; 4603 function = "qup14"; 4604 }; 4605 4606 qup_spi12_cs: qup-spi12-cs-pins { 4607 pins = "gpio51"; 4608 function = "qup14"; 4609 }; 4610 4611 qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins { 4612 pins = "gpio51"; 4613 function = "gpio"; 4614 }; 4615 4616 qup_spi13_data_clk: qup-spi13-data-clk-pins { 4617 pins = "gpio52", "gpio53", "gpio54"; 4618 function = "qup15"; 4619 }; 4620 4621 qup_spi13_cs: qup-spi13-cs-pins { 4622 pins = "gpio55"; 4623 function = "qup15"; 4624 }; 4625 4626 qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins { 4627 pins = "gpio55"; 4628 function = "gpio"; 4629 }; 4630 4631 qup_spi14_data_clk: qup-spi14-data-clk-pins { 4632 pins = "gpio56", "gpio57", "gpio58"; 4633 function = "qup16"; 4634 }; 4635 4636 qup_spi14_cs: qup-spi14-cs-pins { 4637 pins = "gpio59"; 4638 function = "qup16"; 4639 }; 4640 4641 qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins { 4642 pins = "gpio59"; 4643 function = "gpio"; 4644 }; 4645 4646 qup_spi15_data_clk: qup-spi15-data-clk-pins { 4647 pins = "gpio60", "gpio61", "gpio62"; 4648 function = "qup17"; 4649 }; 4650 4651 qup_spi15_cs: qup-spi15-cs-pins { 4652 pins = "gpio63"; 4653 function = "qup17"; 4654 }; 4655 4656 qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins { 4657 pins = "gpio63"; 4658 function = "gpio"; 4659 }; 4660 4661 qup_uart0_cts: qup-uart0-cts-pins { 4662 pins = "gpio0"; 4663 function = "qup00"; 4664 }; 4665 4666 qup_uart0_rts: qup-uart0-rts-pins { 4667 pins = "gpio1"; 4668 function = "qup00"; 4669 }; 4670 4671 qup_uart0_tx: qup-uart0-tx-pins { 4672 pins = "gpio2"; 4673 function = "qup00"; 4674 }; 4675 4676 qup_uart0_rx: qup-uart0-rx-pins { 4677 pins = "gpio3"; 4678 function = "qup00"; 4679 }; 4680 4681 qup_uart1_cts: qup-uart1-cts-pins { 4682 pins = "gpio4"; 4683 function = "qup01"; 4684 }; 4685 4686 qup_uart1_rts: qup-uart1-rts-pins { 4687 pins = "gpio5"; 4688 function = "qup01"; 4689 }; 4690 4691 qup_uart1_tx: qup-uart1-tx-pins { 4692 pins = "gpio6"; 4693 function = "qup01"; 4694 }; 4695 4696 qup_uart1_rx: qup-uart1-rx-pins { 4697 pins = "gpio7"; 4698 function = "qup01"; 4699 }; 4700 4701 qup_uart2_cts: qup-uart2-cts-pins { 4702 pins = "gpio8"; 4703 function = "qup02"; 4704 }; 4705 4706 qup_uart2_rts: qup-uart2-rts-pins { 4707 pins = "gpio9"; 4708 function = "qup02"; 4709 }; 4710 4711 qup_uart2_tx: qup-uart2-tx-pins { 4712 pins = "gpio10"; 4713 function = "qup02"; 4714 }; 4715 4716 qup_uart2_rx: qup-uart2-rx-pins { 4717 pins = "gpio11"; 4718 function = "qup02"; 4719 }; 4720 4721 qup_uart3_cts: qup-uart3-cts-pins { 4722 pins = "gpio12"; 4723 function = "qup03"; 4724 }; 4725 4726 qup_uart3_rts: qup-uart3-rts-pins { 4727 pins = "gpio13"; 4728 function = "qup03"; 4729 }; 4730 4731 qup_uart3_tx: qup-uart3-tx-pins { 4732 pins = "gpio14"; 4733 function = "qup03"; 4734 }; 4735 4736 qup_uart3_rx: qup-uart3-rx-pins { 4737 pins = "gpio15"; 4738 function = "qup03"; 4739 }; 4740 4741 qup_uart4_cts: qup-uart4-cts-pins { 4742 pins = "gpio16"; 4743 function = "qup04"; 4744 }; 4745 4746 qup_uart4_rts: qup-uart4-rts-pins { 4747 pins = "gpio17"; 4748 function = "qup04"; 4749 }; 4750 4751 qup_uart4_tx: qup-uart4-tx-pins { 4752 pins = "gpio18"; 4753 function = "qup04"; 4754 }; 4755 4756 qup_uart4_rx: qup-uart4-rx-pins { 4757 pins = "gpio19"; 4758 function = "qup04"; 4759 }; 4760 4761 qup_uart5_cts: qup-uart5-cts-pins { 4762 pins = "gpio20"; 4763 function = "qup05"; 4764 }; 4765 4766 qup_uart5_rts: qup-uart5-rts-pins { 4767 pins = "gpio21"; 4768 function = "qup05"; 4769 }; 4770 4771 qup_uart5_tx: qup-uart5-tx-pins { 4772 pins = "gpio22"; 4773 function = "qup05"; 4774 }; 4775 4776 qup_uart5_rx: qup-uart5-rx-pins { 4777 pins = "gpio23"; 4778 function = "qup05"; 4779 }; 4780 4781 qup_uart6_cts: qup-uart6-cts-pins { 4782 pins = "gpio24"; 4783 function = "qup06"; 4784 }; 4785 4786 qup_uart6_rts: qup-uart6-rts-pins { 4787 pins = "gpio25"; 4788 function = "qup06"; 4789 }; 4790 4791 qup_uart6_tx: qup-uart6-tx-pins { 4792 pins = "gpio26"; 4793 function = "qup06"; 4794 }; 4795 4796 qup_uart6_rx: qup-uart6-rx-pins { 4797 pins = "gpio27"; 4798 function = "qup06"; 4799 }; 4800 4801 qup_uart7_cts: qup-uart7-cts-pins { 4802 pins = "gpio28"; 4803 function = "qup07"; 4804 }; 4805 4806 qup_uart7_rts: qup-uart7-rts-pins { 4807 pins = "gpio29"; 4808 function = "qup07"; 4809 }; 4810 4811 qup_uart7_tx: qup-uart7-tx-pins { 4812 pins = "gpio30"; 4813 function = "qup07"; 4814 }; 4815 4816 qup_uart7_rx: qup-uart7-rx-pins { 4817 pins = "gpio31"; 4818 function = "qup07"; 4819 }; 4820 4821 qup_uart8_cts: qup-uart8-cts-pins { 4822 pins = "gpio32"; 4823 function = "qup10"; 4824 }; 4825 4826 qup_uart8_rts: qup-uart8-rts-pins { 4827 pins = "gpio33"; 4828 function = "qup10"; 4829 }; 4830 4831 qup_uart8_tx: qup-uart8-tx-pins { 4832 pins = "gpio34"; 4833 function = "qup10"; 4834 }; 4835 4836 qup_uart8_rx: qup-uart8-rx-pins { 4837 pins = "gpio35"; 4838 function = "qup10"; 4839 }; 4840 4841 qup_uart9_cts: qup-uart9-cts-pins { 4842 pins = "gpio36"; 4843 function = "qup11"; 4844 }; 4845 4846 qup_uart9_rts: qup-uart9-rts-pins { 4847 pins = "gpio37"; 4848 function = "qup11"; 4849 }; 4850 4851 qup_uart9_tx: qup-uart9-tx-pins { 4852 pins = "gpio38"; 4853 function = "qup11"; 4854 }; 4855 4856 qup_uart9_rx: qup-uart9-rx-pins { 4857 pins = "gpio39"; 4858 function = "qup11"; 4859 }; 4860 4861 qup_uart10_cts: qup-uart10-cts-pins { 4862 pins = "gpio40"; 4863 function = "qup12"; 4864 }; 4865 4866 qup_uart10_rts: qup-uart10-rts-pins { 4867 pins = "gpio41"; 4868 function = "qup12"; 4869 }; 4870 4871 qup_uart10_tx: qup-uart10-tx-pins { 4872 pins = "gpio42"; 4873 function = "qup12"; 4874 }; 4875 4876 qup_uart10_rx: qup-uart10-rx-pins { 4877 pins = "gpio43"; 4878 function = "qup12"; 4879 }; 4880 4881 qup_uart11_cts: qup-uart11-cts-pins { 4882 pins = "gpio44"; 4883 function = "qup13"; 4884 }; 4885 4886 qup_uart11_rts: qup-uart11-rts-pins { 4887 pins = "gpio45"; 4888 function = "qup13"; 4889 }; 4890 4891 qup_uart11_tx: qup-uart11-tx-pins { 4892 pins = "gpio46"; 4893 function = "qup13"; 4894 }; 4895 4896 qup_uart11_rx: qup-uart11-rx-pins { 4897 pins = "gpio47"; 4898 function = "qup13"; 4899 }; 4900 4901 qup_uart12_cts: qup-uart12-cts-pins { 4902 pins = "gpio48"; 4903 function = "qup14"; 4904 }; 4905 4906 qup_uart12_rts: qup-uart12-rts-pins { 4907 pins = "gpio49"; 4908 function = "qup14"; 4909 }; 4910 4911 qup_uart12_tx: qup-uart12-tx-pins { 4912 pins = "gpio50"; 4913 function = "qup14"; 4914 }; 4915 4916 qup_uart12_rx: qup-uart12-rx-pins { 4917 pins = "gpio51"; 4918 function = "qup14"; 4919 }; 4920 4921 qup_uart13_cts: qup-uart13-cts-pins { 4922 pins = "gpio52"; 4923 function = "qup15"; 4924 }; 4925 4926 qup_uart13_rts: qup-uart13-rts-pins { 4927 pins = "gpio53"; 4928 function = "qup15"; 4929 }; 4930 4931 qup_uart13_tx: qup-uart13-tx-pins { 4932 pins = "gpio54"; 4933 function = "qup15"; 4934 }; 4935 4936 qup_uart13_rx: qup-uart13-rx-pins { 4937 pins = "gpio55"; 4938 function = "qup15"; 4939 }; 4940 4941 qup_uart14_cts: qup-uart14-cts-pins { 4942 pins = "gpio56"; 4943 function = "qup16"; 4944 }; 4945 4946 qup_uart14_rts: qup-uart14-rts-pins { 4947 pins = "gpio57"; 4948 function = "qup16"; 4949 }; 4950 4951 qup_uart14_tx: qup-uart14-tx-pins { 4952 pins = "gpio58"; 4953 function = "qup16"; 4954 }; 4955 4956 qup_uart14_rx: qup-uart14-rx-pins { 4957 pins = "gpio59"; 4958 function = "qup16"; 4959 }; 4960 4961 qup_uart15_cts: qup-uart15-cts-pins { 4962 pins = "gpio60"; 4963 function = "qup17"; 4964 }; 4965 4966 qup_uart15_rts: qup-uart15-rts-pins { 4967 pins = "gpio61"; 4968 function = "qup17"; 4969 }; 4970 4971 qup_uart15_tx: qup-uart15-tx-pins { 4972 pins = "gpio62"; 4973 function = "qup17"; 4974 }; 4975 4976 qup_uart15_rx: qup-uart15-rx-pins { 4977 pins = "gpio63"; 4978 function = "qup17"; 4979 }; 4980 4981 sdc1_clk: sdc1-clk-pins { 4982 pins = "sdc1_clk"; 4983 }; 4984 4985 sdc1_cmd: sdc1-cmd-pins { 4986 pins = "sdc1_cmd"; 4987 }; 4988 4989 sdc1_data: sdc1-data-pins { 4990 pins = "sdc1_data"; 4991 }; 4992 4993 sdc1_rclk: sdc1-rclk-pins { 4994 pins = "sdc1_rclk"; 4995 }; 4996 4997 sdc1_clk_sleep: sdc1-clk-sleep-pins { 4998 pins = "sdc1_clk"; 4999 drive-strength = <2>; 5000 bias-bus-hold; 5001 }; 5002 5003 sdc1_cmd_sleep: sdc1-cmd-sleep-pins { 5004 pins = "sdc1_cmd"; 5005 drive-strength = <2>; 5006 bias-bus-hold; 5007 }; 5008 5009 sdc1_data_sleep: sdc1-data-sleep-pins { 5010 pins = "sdc1_data"; 5011 drive-strength = <2>; 5012 bias-bus-hold; 5013 }; 5014 5015 sdc1_rclk_sleep: sdc1-rclk-sleep-pins { 5016 pins = "sdc1_rclk"; 5017 drive-strength = <2>; 5018 bias-bus-hold; 5019 }; 5020 5021 sdc2_clk: sdc2-clk-pins { 5022 pins = "sdc2_clk"; 5023 }; 5024 5025 sdc2_cmd: sdc2-cmd-pins { 5026 pins = "sdc2_cmd"; 5027 }; 5028 5029 sdc2_data: sdc2-data-pins { 5030 pins = "sdc2_data"; 5031 }; 5032 5033 sdc2_clk_sleep: sdc2-clk-sleep-pins { 5034 pins = "sdc2_clk"; 5035 drive-strength = <2>; 5036 bias-bus-hold; 5037 }; 5038 5039 sdc2_cmd_sleep: sdc2-cmd-sleep-pins { 5040 pins = "sdc2_cmd"; 5041 drive-strength = <2>; 5042 bias-bus-hold; 5043 }; 5044 5045 sdc2_data_sleep: sdc2-data-sleep-pins { 5046 pins = "sdc2_data"; 5047 drive-strength = <2>; 5048 bias-bus-hold; 5049 }; 5050 }; 5051 5052 sram@146a5000 { 5053 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5054 reg = <0 0x146a5000 0 0x6000>; 5055 5056 #address-cells = <1>; 5057 #size-cells = <1>; 5058 5059 ranges = <0 0 0x146a5000 0x6000>; 5060 5061 pil-reloc@594c { 5062 compatible = "qcom,pil-reloc-info"; 5063 reg = <0x594c 0xc8>; 5064 }; 5065 }; 5066 5067 apps_smmu: iommu@15000000 { 5068 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5069 reg = <0 0x15000000 0 0x100000>; 5070 #iommu-cells = <2>; 5071 #global-interrupts = <1>; 5072 dma-coherent; 5073 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5083 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5084 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5085 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5154 }; 5155 5156 intc: interrupt-controller@17a00000 { 5157 compatible = "arm,gic-v3"; 5158 #address-cells = <2>; 5159 #size-cells = <2>; 5160 ranges; 5161 #interrupt-cells = <3>; 5162 interrupt-controller; 5163 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5164 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5165 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5166 5167 gic-its@17a40000 { 5168 compatible = "arm,gic-v3-its"; 5169 msi-controller; 5170 #msi-cells = <1>; 5171 reg = <0 0x17a40000 0 0x20000>; 5172 status = "disabled"; 5173 }; 5174 }; 5175 5176 watchdog@17c10000 { 5177 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5178 reg = <0 0x17c10000 0 0x1000>; 5179 clocks = <&sleep_clk>; 5180 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5181 }; 5182 5183 timer@17c20000 { 5184 #address-cells = <1>; 5185 #size-cells = <1>; 5186 ranges = <0 0 0 0x20000000>; 5187 compatible = "arm,armv7-timer-mem"; 5188 reg = <0 0x17c20000 0 0x1000>; 5189 5190 frame@17c21000 { 5191 frame-number = <0>; 5192 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5194 reg = <0x17c21000 0x1000>, 5195 <0x17c22000 0x1000>; 5196 }; 5197 5198 frame@17c23000 { 5199 frame-number = <1>; 5200 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5201 reg = <0x17c23000 0x1000>; 5202 status = "disabled"; 5203 }; 5204 5205 frame@17c25000 { 5206 frame-number = <2>; 5207 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5208 reg = <0x17c25000 0x1000>; 5209 status = "disabled"; 5210 }; 5211 5212 frame@17c27000 { 5213 frame-number = <3>; 5214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5215 reg = <0x17c27000 0x1000>; 5216 status = "disabled"; 5217 }; 5218 5219 frame@17c29000 { 5220 frame-number = <4>; 5221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5222 reg = <0x17c29000 0x1000>; 5223 status = "disabled"; 5224 }; 5225 5226 frame@17c2b000 { 5227 frame-number = <5>; 5228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5229 reg = <0x17c2b000 0x1000>; 5230 status = "disabled"; 5231 }; 5232 5233 frame@17c2d000 { 5234 frame-number = <6>; 5235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5236 reg = <0x17c2d000 0x1000>; 5237 status = "disabled"; 5238 }; 5239 }; 5240 5241 apps_rsc: rsc@18200000 { 5242 compatible = "qcom,rpmh-rsc"; 5243 reg = <0 0x18200000 0 0x10000>, 5244 <0 0x18210000 0 0x10000>, 5245 <0 0x18220000 0 0x10000>; 5246 reg-names = "drv-0", "drv-1", "drv-2"; 5247 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5248 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5249 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5250 qcom,tcs-offset = <0xd00>; 5251 qcom,drv-id = <2>; 5252 qcom,tcs-config = <ACTIVE_TCS 2>, 5253 <SLEEP_TCS 3>, 5254 <WAKE_TCS 3>, 5255 <CONTROL_TCS 1>; 5256 5257 apps_bcm_voter: bcm-voter { 5258 compatible = "qcom,bcm-voter"; 5259 }; 5260 5261 rpmhpd: power-controller { 5262 compatible = "qcom,sc7280-rpmhpd"; 5263 #power-domain-cells = <1>; 5264 operating-points-v2 = <&rpmhpd_opp_table>; 5265 5266 rpmhpd_opp_table: opp-table { 5267 compatible = "operating-points-v2"; 5268 5269 rpmhpd_opp_ret: opp1 { 5270 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5271 }; 5272 5273 rpmhpd_opp_low_svs: opp2 { 5274 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5275 }; 5276 5277 rpmhpd_opp_svs: opp3 { 5278 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5279 }; 5280 5281 rpmhpd_opp_svs_l1: opp4 { 5282 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5283 }; 5284 5285 rpmhpd_opp_svs_l2: opp5 { 5286 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5287 }; 5288 5289 rpmhpd_opp_nom: opp6 { 5290 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5291 }; 5292 5293 rpmhpd_opp_nom_l1: opp7 { 5294 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5295 }; 5296 5297 rpmhpd_opp_turbo: opp8 { 5298 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5299 }; 5300 5301 rpmhpd_opp_turbo_l1: opp9 { 5302 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5303 }; 5304 }; 5305 }; 5306 5307 rpmhcc: clock-controller { 5308 compatible = "qcom,sc7280-rpmh-clk"; 5309 clocks = <&xo_board>; 5310 clock-names = "xo"; 5311 #clock-cells = <1>; 5312 }; 5313 }; 5314 5315 epss_l3: interconnect@18590000 { 5316 compatible = "qcom,sc7280-epss-l3"; 5317 reg = <0 0x18590000 0 0x1000>; 5318 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5319 clock-names = "xo", "alternate"; 5320 #interconnect-cells = <1>; 5321 }; 5322 5323 cpufreq_hw: cpufreq@18591000 { 5324 compatible = "qcom,cpufreq-epss"; 5325 reg = <0 0x18591000 0 0x1000>, 5326 <0 0x18592000 0 0x1000>, 5327 <0 0x18593000 0 0x1000>; 5328 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5329 clock-names = "xo", "alternate"; 5330 #freq-domain-cells = <1>; 5331 }; 5332 }; 5333 5334 thermal_zones: thermal-zones { 5335 cpu0-thermal { 5336 polling-delay-passive = <250>; 5337 polling-delay = <0>; 5338 5339 thermal-sensors = <&tsens0 1>; 5340 5341 trips { 5342 cpu0_alert0: trip-point0 { 5343 temperature = <90000>; 5344 hysteresis = <2000>; 5345 type = "passive"; 5346 }; 5347 5348 cpu0_alert1: trip-point1 { 5349 temperature = <95000>; 5350 hysteresis = <2000>; 5351 type = "passive"; 5352 }; 5353 5354 cpu0_crit: cpu-crit { 5355 temperature = <110000>; 5356 hysteresis = <0>; 5357 type = "critical"; 5358 }; 5359 }; 5360 5361 cooling-maps { 5362 map0 { 5363 trip = <&cpu0_alert0>; 5364 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5365 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5366 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5367 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5368 }; 5369 map1 { 5370 trip = <&cpu0_alert1>; 5371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5375 }; 5376 }; 5377 }; 5378 5379 cpu1-thermal { 5380 polling-delay-passive = <250>; 5381 polling-delay = <0>; 5382 5383 thermal-sensors = <&tsens0 2>; 5384 5385 trips { 5386 cpu1_alert0: trip-point0 { 5387 temperature = <90000>; 5388 hysteresis = <2000>; 5389 type = "passive"; 5390 }; 5391 5392 cpu1_alert1: trip-point1 { 5393 temperature = <95000>; 5394 hysteresis = <2000>; 5395 type = "passive"; 5396 }; 5397 5398 cpu1_crit: cpu-crit { 5399 temperature = <110000>; 5400 hysteresis = <0>; 5401 type = "critical"; 5402 }; 5403 }; 5404 5405 cooling-maps { 5406 map0 { 5407 trip = <&cpu1_alert0>; 5408 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5409 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5410 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5411 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5412 }; 5413 map1 { 5414 trip = <&cpu1_alert1>; 5415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5419 }; 5420 }; 5421 }; 5422 5423 cpu2-thermal { 5424 polling-delay-passive = <250>; 5425 polling-delay = <0>; 5426 5427 thermal-sensors = <&tsens0 3>; 5428 5429 trips { 5430 cpu2_alert0: trip-point0 { 5431 temperature = <90000>; 5432 hysteresis = <2000>; 5433 type = "passive"; 5434 }; 5435 5436 cpu2_alert1: trip-point1 { 5437 temperature = <95000>; 5438 hysteresis = <2000>; 5439 type = "passive"; 5440 }; 5441 5442 cpu2_crit: cpu-crit { 5443 temperature = <110000>; 5444 hysteresis = <0>; 5445 type = "critical"; 5446 }; 5447 }; 5448 5449 cooling-maps { 5450 map0 { 5451 trip = <&cpu2_alert0>; 5452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5456 }; 5457 map1 { 5458 trip = <&cpu2_alert1>; 5459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5463 }; 5464 }; 5465 }; 5466 5467 cpu3-thermal { 5468 polling-delay-passive = <250>; 5469 polling-delay = <0>; 5470 5471 thermal-sensors = <&tsens0 4>; 5472 5473 trips { 5474 cpu3_alert0: trip-point0 { 5475 temperature = <90000>; 5476 hysteresis = <2000>; 5477 type = "passive"; 5478 }; 5479 5480 cpu3_alert1: trip-point1 { 5481 temperature = <95000>; 5482 hysteresis = <2000>; 5483 type = "passive"; 5484 }; 5485 5486 cpu3_crit: cpu-crit { 5487 temperature = <110000>; 5488 hysteresis = <0>; 5489 type = "critical"; 5490 }; 5491 }; 5492 5493 cooling-maps { 5494 map0 { 5495 trip = <&cpu3_alert0>; 5496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5500 }; 5501 map1 { 5502 trip = <&cpu3_alert1>; 5503 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5504 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5505 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5506 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5507 }; 5508 }; 5509 }; 5510 5511 cpu4-thermal { 5512 polling-delay-passive = <250>; 5513 polling-delay = <0>; 5514 5515 thermal-sensors = <&tsens0 7>; 5516 5517 trips { 5518 cpu4_alert0: trip-point0 { 5519 temperature = <90000>; 5520 hysteresis = <2000>; 5521 type = "passive"; 5522 }; 5523 5524 cpu4_alert1: trip-point1 { 5525 temperature = <95000>; 5526 hysteresis = <2000>; 5527 type = "passive"; 5528 }; 5529 5530 cpu4_crit: cpu-crit { 5531 temperature = <110000>; 5532 hysteresis = <0>; 5533 type = "critical"; 5534 }; 5535 }; 5536 5537 cooling-maps { 5538 map0 { 5539 trip = <&cpu4_alert0>; 5540 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5543 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5544 }; 5545 map1 { 5546 trip = <&cpu4_alert1>; 5547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5551 }; 5552 }; 5553 }; 5554 5555 cpu5-thermal { 5556 polling-delay-passive = <250>; 5557 polling-delay = <0>; 5558 5559 thermal-sensors = <&tsens0 8>; 5560 5561 trips { 5562 cpu5_alert0: trip-point0 { 5563 temperature = <90000>; 5564 hysteresis = <2000>; 5565 type = "passive"; 5566 }; 5567 5568 cpu5_alert1: trip-point1 { 5569 temperature = <95000>; 5570 hysteresis = <2000>; 5571 type = "passive"; 5572 }; 5573 5574 cpu5_crit: cpu-crit { 5575 temperature = <110000>; 5576 hysteresis = <0>; 5577 type = "critical"; 5578 }; 5579 }; 5580 5581 cooling-maps { 5582 map0 { 5583 trip = <&cpu5_alert0>; 5584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5588 }; 5589 map1 { 5590 trip = <&cpu5_alert1>; 5591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5595 }; 5596 }; 5597 }; 5598 5599 cpu6-thermal { 5600 polling-delay-passive = <250>; 5601 polling-delay = <0>; 5602 5603 thermal-sensors = <&tsens0 9>; 5604 5605 trips { 5606 cpu6_alert0: trip-point0 { 5607 temperature = <90000>; 5608 hysteresis = <2000>; 5609 type = "passive"; 5610 }; 5611 5612 cpu6_alert1: trip-point1 { 5613 temperature = <95000>; 5614 hysteresis = <2000>; 5615 type = "passive"; 5616 }; 5617 5618 cpu6_crit: cpu-crit { 5619 temperature = <110000>; 5620 hysteresis = <0>; 5621 type = "critical"; 5622 }; 5623 }; 5624 5625 cooling-maps { 5626 map0 { 5627 trip = <&cpu6_alert0>; 5628 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5629 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5631 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5632 }; 5633 map1 { 5634 trip = <&cpu6_alert1>; 5635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5639 }; 5640 }; 5641 }; 5642 5643 cpu7-thermal { 5644 polling-delay-passive = <250>; 5645 polling-delay = <0>; 5646 5647 thermal-sensors = <&tsens0 10>; 5648 5649 trips { 5650 cpu7_alert0: trip-point0 { 5651 temperature = <90000>; 5652 hysteresis = <2000>; 5653 type = "passive"; 5654 }; 5655 5656 cpu7_alert1: trip-point1 { 5657 temperature = <95000>; 5658 hysteresis = <2000>; 5659 type = "passive"; 5660 }; 5661 5662 cpu7_crit: cpu-crit { 5663 temperature = <110000>; 5664 hysteresis = <0>; 5665 type = "critical"; 5666 }; 5667 }; 5668 5669 cooling-maps { 5670 map0 { 5671 trip = <&cpu7_alert0>; 5672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5676 }; 5677 map1 { 5678 trip = <&cpu7_alert1>; 5679 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5680 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5681 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5682 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5683 }; 5684 }; 5685 }; 5686 5687 cpu8-thermal { 5688 polling-delay-passive = <250>; 5689 polling-delay = <0>; 5690 5691 thermal-sensors = <&tsens0 11>; 5692 5693 trips { 5694 cpu8_alert0: trip-point0 { 5695 temperature = <90000>; 5696 hysteresis = <2000>; 5697 type = "passive"; 5698 }; 5699 5700 cpu8_alert1: trip-point1 { 5701 temperature = <95000>; 5702 hysteresis = <2000>; 5703 type = "passive"; 5704 }; 5705 5706 cpu8_crit: cpu-crit { 5707 temperature = <110000>; 5708 hysteresis = <0>; 5709 type = "critical"; 5710 }; 5711 }; 5712 5713 cooling-maps { 5714 map0 { 5715 trip = <&cpu8_alert0>; 5716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5720 }; 5721 map1 { 5722 trip = <&cpu8_alert1>; 5723 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5724 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5725 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5726 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5727 }; 5728 }; 5729 }; 5730 5731 cpu9-thermal { 5732 polling-delay-passive = <250>; 5733 polling-delay = <0>; 5734 5735 thermal-sensors = <&tsens0 12>; 5736 5737 trips { 5738 cpu9_alert0: trip-point0 { 5739 temperature = <90000>; 5740 hysteresis = <2000>; 5741 type = "passive"; 5742 }; 5743 5744 cpu9_alert1: trip-point1 { 5745 temperature = <95000>; 5746 hysteresis = <2000>; 5747 type = "passive"; 5748 }; 5749 5750 cpu9_crit: cpu-crit { 5751 temperature = <110000>; 5752 hysteresis = <0>; 5753 type = "critical"; 5754 }; 5755 }; 5756 5757 cooling-maps { 5758 map0 { 5759 trip = <&cpu9_alert0>; 5760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5764 }; 5765 map1 { 5766 trip = <&cpu9_alert1>; 5767 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5768 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5769 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5770 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5771 }; 5772 }; 5773 }; 5774 5775 cpu10-thermal { 5776 polling-delay-passive = <250>; 5777 polling-delay = <0>; 5778 5779 thermal-sensors = <&tsens0 13>; 5780 5781 trips { 5782 cpu10_alert0: trip-point0 { 5783 temperature = <90000>; 5784 hysteresis = <2000>; 5785 type = "passive"; 5786 }; 5787 5788 cpu10_alert1: trip-point1 { 5789 temperature = <95000>; 5790 hysteresis = <2000>; 5791 type = "passive"; 5792 }; 5793 5794 cpu10_crit: cpu-crit { 5795 temperature = <110000>; 5796 hysteresis = <0>; 5797 type = "critical"; 5798 }; 5799 }; 5800 5801 cooling-maps { 5802 map0 { 5803 trip = <&cpu10_alert0>; 5804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5808 }; 5809 map1 { 5810 trip = <&cpu10_alert1>; 5811 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5812 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5813 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5815 }; 5816 }; 5817 }; 5818 5819 cpu11-thermal { 5820 polling-delay-passive = <250>; 5821 polling-delay = <0>; 5822 5823 thermal-sensors = <&tsens0 14>; 5824 5825 trips { 5826 cpu11_alert0: trip-point0 { 5827 temperature = <90000>; 5828 hysteresis = <2000>; 5829 type = "passive"; 5830 }; 5831 5832 cpu11_alert1: trip-point1 { 5833 temperature = <95000>; 5834 hysteresis = <2000>; 5835 type = "passive"; 5836 }; 5837 5838 cpu11_crit: cpu-crit { 5839 temperature = <110000>; 5840 hysteresis = <0>; 5841 type = "critical"; 5842 }; 5843 }; 5844 5845 cooling-maps { 5846 map0 { 5847 trip = <&cpu11_alert0>; 5848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5852 }; 5853 map1 { 5854 trip = <&cpu11_alert1>; 5855 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5857 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5859 }; 5860 }; 5861 }; 5862 5863 aoss0-thermal { 5864 polling-delay-passive = <0>; 5865 polling-delay = <0>; 5866 5867 thermal-sensors = <&tsens0 0>; 5868 5869 trips { 5870 aoss0_alert0: trip-point0 { 5871 temperature = <90000>; 5872 hysteresis = <2000>; 5873 type = "hot"; 5874 }; 5875 5876 aoss0_crit: aoss0-crit { 5877 temperature = <110000>; 5878 hysteresis = <0>; 5879 type = "critical"; 5880 }; 5881 }; 5882 }; 5883 5884 aoss1-thermal { 5885 polling-delay-passive = <0>; 5886 polling-delay = <0>; 5887 5888 thermal-sensors = <&tsens1 0>; 5889 5890 trips { 5891 aoss1_alert0: trip-point0 { 5892 temperature = <90000>; 5893 hysteresis = <2000>; 5894 type = "hot"; 5895 }; 5896 5897 aoss1_crit: aoss1-crit { 5898 temperature = <110000>; 5899 hysteresis = <0>; 5900 type = "critical"; 5901 }; 5902 }; 5903 }; 5904 5905 cpuss0-thermal { 5906 polling-delay-passive = <0>; 5907 polling-delay = <0>; 5908 5909 thermal-sensors = <&tsens0 5>; 5910 5911 trips { 5912 cpuss0_alert0: trip-point0 { 5913 temperature = <90000>; 5914 hysteresis = <2000>; 5915 type = "hot"; 5916 }; 5917 cpuss0_crit: cluster0-crit { 5918 temperature = <110000>; 5919 hysteresis = <0>; 5920 type = "critical"; 5921 }; 5922 }; 5923 }; 5924 5925 cpuss1-thermal { 5926 polling-delay-passive = <0>; 5927 polling-delay = <0>; 5928 5929 thermal-sensors = <&tsens0 6>; 5930 5931 trips { 5932 cpuss1_alert0: trip-point0 { 5933 temperature = <90000>; 5934 hysteresis = <2000>; 5935 type = "hot"; 5936 }; 5937 cpuss1_crit: cluster0-crit { 5938 temperature = <110000>; 5939 hysteresis = <0>; 5940 type = "critical"; 5941 }; 5942 }; 5943 }; 5944 5945 gpuss0-thermal { 5946 polling-delay-passive = <100>; 5947 polling-delay = <0>; 5948 5949 thermal-sensors = <&tsens1 1>; 5950 5951 trips { 5952 gpuss0_alert0: trip-point0 { 5953 temperature = <95000>; 5954 hysteresis = <2000>; 5955 type = "passive"; 5956 }; 5957 5958 gpuss0_crit: gpuss0-crit { 5959 temperature = <110000>; 5960 hysteresis = <0>; 5961 type = "critical"; 5962 }; 5963 }; 5964 5965 cooling-maps { 5966 map0 { 5967 trip = <&gpuss0_alert0>; 5968 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5969 }; 5970 }; 5971 }; 5972 5973 gpuss1-thermal { 5974 polling-delay-passive = <100>; 5975 polling-delay = <0>; 5976 5977 thermal-sensors = <&tsens1 2>; 5978 5979 trips { 5980 gpuss1_alert0: trip-point0 { 5981 temperature = <95000>; 5982 hysteresis = <2000>; 5983 type = "passive"; 5984 }; 5985 5986 gpuss1_crit: gpuss1-crit { 5987 temperature = <110000>; 5988 hysteresis = <0>; 5989 type = "critical"; 5990 }; 5991 }; 5992 5993 cooling-maps { 5994 map0 { 5995 trip = <&gpuss1_alert0>; 5996 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5997 }; 5998 }; 5999 }; 6000 6001 nspss0-thermal { 6002 polling-delay-passive = <0>; 6003 polling-delay = <0>; 6004 6005 thermal-sensors = <&tsens1 3>; 6006 6007 trips { 6008 nspss0_alert0: trip-point0 { 6009 temperature = <90000>; 6010 hysteresis = <2000>; 6011 type = "hot"; 6012 }; 6013 6014 nspss0_crit: nspss0-crit { 6015 temperature = <110000>; 6016 hysteresis = <0>; 6017 type = "critical"; 6018 }; 6019 }; 6020 }; 6021 6022 nspss1-thermal { 6023 polling-delay-passive = <0>; 6024 polling-delay = <0>; 6025 6026 thermal-sensors = <&tsens1 4>; 6027 6028 trips { 6029 nspss1_alert0: trip-point0 { 6030 temperature = <90000>; 6031 hysteresis = <2000>; 6032 type = "hot"; 6033 }; 6034 6035 nspss1_crit: nspss1-crit { 6036 temperature = <110000>; 6037 hysteresis = <0>; 6038 type = "critical"; 6039 }; 6040 }; 6041 }; 6042 6043 video-thermal { 6044 polling-delay-passive = <0>; 6045 polling-delay = <0>; 6046 6047 thermal-sensors = <&tsens1 5>; 6048 6049 trips { 6050 video_alert0: trip-point0 { 6051 temperature = <90000>; 6052 hysteresis = <2000>; 6053 type = "hot"; 6054 }; 6055 6056 video_crit: video-crit { 6057 temperature = <110000>; 6058 hysteresis = <0>; 6059 type = "critical"; 6060 }; 6061 }; 6062 }; 6063 6064 ddr-thermal { 6065 polling-delay-passive = <0>; 6066 polling-delay = <0>; 6067 6068 thermal-sensors = <&tsens1 6>; 6069 6070 trips { 6071 ddr_alert0: trip-point0 { 6072 temperature = <90000>; 6073 hysteresis = <2000>; 6074 type = "hot"; 6075 }; 6076 6077 ddr_crit: ddr-crit { 6078 temperature = <110000>; 6079 hysteresis = <0>; 6080 type = "critical"; 6081 }; 6082 }; 6083 }; 6084 6085 mdmss0-thermal { 6086 polling-delay-passive = <0>; 6087 polling-delay = <0>; 6088 6089 thermal-sensors = <&tsens1 7>; 6090 6091 trips { 6092 mdmss0_alert0: trip-point0 { 6093 temperature = <90000>; 6094 hysteresis = <2000>; 6095 type = "hot"; 6096 }; 6097 6098 mdmss0_crit: mdmss0-crit { 6099 temperature = <110000>; 6100 hysteresis = <0>; 6101 type = "critical"; 6102 }; 6103 }; 6104 }; 6105 6106 mdmss1-thermal { 6107 polling-delay-passive = <0>; 6108 polling-delay = <0>; 6109 6110 thermal-sensors = <&tsens1 8>; 6111 6112 trips { 6113 mdmss1_alert0: trip-point0 { 6114 temperature = <90000>; 6115 hysteresis = <2000>; 6116 type = "hot"; 6117 }; 6118 6119 mdmss1_crit: mdmss1-crit { 6120 temperature = <110000>; 6121 hysteresis = <0>; 6122 type = "critical"; 6123 }; 6124 }; 6125 }; 6126 6127 mdmss2-thermal { 6128 polling-delay-passive = <0>; 6129 polling-delay = <0>; 6130 6131 thermal-sensors = <&tsens1 9>; 6132 6133 trips { 6134 mdmss2_alert0: trip-point0 { 6135 temperature = <90000>; 6136 hysteresis = <2000>; 6137 type = "hot"; 6138 }; 6139 6140 mdmss2_crit: mdmss2-crit { 6141 temperature = <110000>; 6142 hysteresis = <0>; 6143 type = "critical"; 6144 }; 6145 }; 6146 }; 6147 6148 mdmss3-thermal { 6149 polling-delay-passive = <0>; 6150 polling-delay = <0>; 6151 6152 thermal-sensors = <&tsens1 10>; 6153 6154 trips { 6155 mdmss3_alert0: trip-point0 { 6156 temperature = <90000>; 6157 hysteresis = <2000>; 6158 type = "hot"; 6159 }; 6160 6161 mdmss3_crit: mdmss3-crit { 6162 temperature = <110000>; 6163 hysteresis = <0>; 6164 type = "critical"; 6165 }; 6166 }; 6167 }; 6168 6169 camera0-thermal { 6170 polling-delay-passive = <0>; 6171 polling-delay = <0>; 6172 6173 thermal-sensors = <&tsens1 11>; 6174 6175 trips { 6176 camera0_alert0: trip-point0 { 6177 temperature = <90000>; 6178 hysteresis = <2000>; 6179 type = "hot"; 6180 }; 6181 6182 camera0_crit: camera0-crit { 6183 temperature = <110000>; 6184 hysteresis = <0>; 6185 type = "critical"; 6186 }; 6187 }; 6188 }; 6189 }; 6190 6191 timer { 6192 compatible = "arm,armv8-timer"; 6193 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6194 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6195 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6196 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6197 }; 6198}; 6199