1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/phy/phy-qcom-qusb2.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { }; 25 26 chosen { }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 CPU0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "qcom,kryo360"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 power-domains = <&CPU_PD0>; 38 power-domain-names = "psci"; 39 next-level-cache = <&L2_0>; 40 L2_0: l2-cache { 41 compatible = "cache"; 42 next-level-cache = <&L3_0>; 43 L3_0: l3-cache { 44 compatible = "cache"; 45 }; 46 }; 47 }; 48 49 CPU1: cpu@100 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo360"; 52 reg = <0x0 0x100>; 53 enable-method = "psci"; 54 power-domains = <&CPU_PD1>; 55 power-domain-names = "psci"; 56 next-level-cache = <&L2_100>; 57 L2_100: l2-cache { 58 compatible = "cache"; 59 next-level-cache = <&L3_0>; 60 }; 61 }; 62 63 CPU2: cpu@200 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo360"; 66 reg = <0x0 0x200>; 67 enable-method = "psci"; 68 power-domains = <&CPU_PD2>; 69 power-domain-names = "psci"; 70 next-level-cache = <&L2_200>; 71 L2_200: l2-cache { 72 compatible = "cache"; 73 next-level-cache = <&L3_0>; 74 }; 75 }; 76 77 CPU3: cpu@300 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo360"; 80 reg = <0x0 0x300>; 81 enable-method = "psci"; 82 power-domains = <&CPU_PD3>; 83 power-domain-names = "psci"; 84 next-level-cache = <&L2_300>; 85 L2_300: l2-cache { 86 compatible = "cache"; 87 next-level-cache = <&L3_0>; 88 }; 89 }; 90 91 CPU4: cpu@400 { 92 device_type = "cpu"; 93 compatible = "qcom,kryo360"; 94 reg = <0x0 0x400>; 95 enable-method = "psci"; 96 power-domains = <&CPU_PD4>; 97 power-domain-names = "psci"; 98 next-level-cache = <&L2_400>; 99 L2_400: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU5: cpu@500 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo360"; 108 reg = <0x0 0x500>; 109 enable-method = "psci"; 110 power-domains = <&CPU_PD5>; 111 power-domain-names = "psci"; 112 next-level-cache = <&L2_500>; 113 L2_500: l2-cache { 114 compatible = "cache"; 115 next-level-cache = <&L3_0>; 116 }; 117 }; 118 119 CPU6: cpu@600 { 120 device_type = "cpu"; 121 compatible = "qcom,kryo360"; 122 reg = <0x0 0x600>; 123 enable-method = "psci"; 124 power-domains = <&CPU_PD6>; 125 power-domain-names = "psci"; 126 next-level-cache = <&L2_600>; 127 L2_600: l2-cache { 128 compatible = "cache"; 129 next-level-cache = <&L3_0>; 130 }; 131 }; 132 133 CPU7: cpu@700 { 134 device_type = "cpu"; 135 compatible = "qcom,kryo360"; 136 reg = <0x0 0x700>; 137 enable-method = "psci"; 138 power-domains = <&CPU_PD7>; 139 power-domain-names = "psci"; 140 next-level-cache = <&L2_700>; 141 L2_700: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 cpu-map { 148 cluster0 { 149 core0 { 150 cpu = <&CPU0>; 151 }; 152 153 core1 { 154 cpu = <&CPU1>; 155 }; 156 157 core2 { 158 cpu = <&CPU2>; 159 }; 160 161 core3 { 162 cpu = <&CPU3>; 163 }; 164 165 core4 { 166 cpu = <&CPU4>; 167 }; 168 169 core5 { 170 cpu = <&CPU5>; 171 }; 172 173 core6 { 174 cpu = <&CPU6>; 175 }; 176 177 core7 { 178 cpu = <&CPU7>; 179 }; 180 }; 181 }; 182 183 idle-states { 184 entry-method = "psci"; 185 186 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 187 compatible = "arm,idle-state"; 188 idle-state-name = "little-rail-power-collapse"; 189 arm,psci-suspend-param = <0x40000004>; 190 entry-latency-us = <702>; 191 exit-latency-us = <915>; 192 min-residency-us = <1617>; 193 local-timer-stop; 194 }; 195 196 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 197 compatible = "arm,idle-state"; 198 idle-state-name = "big-rail-power-collapse"; 199 arm,psci-suspend-param = <0x40000004>; 200 entry-latency-us = <526>; 201 exit-latency-us = <1854>; 202 min-residency-us = <2380>; 203 local-timer-stop; 204 }; 205 }; 206 207 domain-idle-states { 208 CLUSTER_SLEEP_0: cluster-sleep-0 { 209 compatible = "domain-idle-state"; 210 arm,psci-suspend-param = <0x4100c244>; 211 entry-latency-us = <3263>; 212 exit-latency-us = <6562>; 213 min-residency-us = <9825>; 214 }; 215 }; 216 }; 217 218 firmware { 219 scm { 220 compatible = "qcom,scm-sdm670", "qcom,scm"; 221 }; 222 }; 223 224 memory@80000000 { 225 device_type = "memory"; 226 /* We expect the bootloader to fill in the size */ 227 reg = <0x0 0x80000000 0x0 0x0>; 228 }; 229 230 psci { 231 compatible = "arm,psci-1.0"; 232 method = "smc"; 233 234 CPU_PD0: power-domain-cpu0 { 235 #power-domain-cells = <0>; 236 power-domains = <&CLUSTER_PD>; 237 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 238 }; 239 240 CPU_PD1: power-domain-cpu1 { 241 #power-domain-cells = <0>; 242 power-domains = <&CLUSTER_PD>; 243 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 244 }; 245 246 CPU_PD2: power-domain-cpu2 { 247 #power-domain-cells = <0>; 248 power-domains = <&CLUSTER_PD>; 249 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 250 }; 251 252 CPU_PD3: power-domain-cpu3 { 253 #power-domain-cells = <0>; 254 power-domains = <&CLUSTER_PD>; 255 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 256 }; 257 258 CPU_PD4: power-domain-cpu4 { 259 #power-domain-cells = <0>; 260 power-domains = <&CLUSTER_PD>; 261 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 262 }; 263 264 CPU_PD5: power-domain-cpu5 { 265 #power-domain-cells = <0>; 266 power-domains = <&CLUSTER_PD>; 267 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 268 }; 269 270 CPU_PD6: power-domain-cpu6 { 271 #power-domain-cells = <0>; 272 power-domains = <&CLUSTER_PD>; 273 domain-idle-states = <&BIG_CPU_SLEEP_0>; 274 }; 275 276 CPU_PD7: power-domain-cpu7 { 277 #power-domain-cells = <0>; 278 power-domains = <&CLUSTER_PD>; 279 domain-idle-states = <&BIG_CPU_SLEEP_0>; 280 }; 281 282 CLUSTER_PD: power-domain-cluster { 283 #power-domain-cells = <0>; 284 domain-idle-states = <&CLUSTER_SLEEP_0>; 285 }; 286 }; 287 288 reserved-memory { 289 #address-cells = <2>; 290 #size-cells = <2>; 291 ranges; 292 293 hyp_mem: hyp-mem@85700000 { 294 reg = <0 0x85700000 0 0x600000>; 295 no-map; 296 }; 297 298 xbl_mem: xbl-mem@85e00000 { 299 reg = <0 0x85e00000 0 0x100000>; 300 no-map; 301 }; 302 303 aop_mem: aop-mem@85fc0000 { 304 reg = <0 0x85fc0000 0 0x20000>; 305 no-map; 306 }; 307 308 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 309 compatible = "qcom,cmd-db"; 310 reg = <0 0x85fe0000 0 0x20000>; 311 no-map; 312 }; 313 314 camera_mem: camera-mem@8ab00000 { 315 reg = <0 0x8ab00000 0 0x500000>; 316 no-map; 317 }; 318 319 mpss_region: mpss@8b000000 { 320 reg = <0 0x8b000000 0 0x7e00000>; 321 no-map; 322 }; 323 324 venus_mem: venus@92e00000 { 325 reg = <0 0x92e00000 0 0x500000>; 326 no-map; 327 }; 328 329 wlan_msa_mem: wlan-msa@93300000 { 330 reg = <0 0x93300000 0 0x100000>; 331 no-map; 332 }; 333 334 cdsp_mem: cdsp@93400000 { 335 reg = <0 0x93400000 0 0x800000>; 336 no-map; 337 }; 338 339 mba_region: mba@93c00000 { 340 reg = <0 0x93c00000 0 0x200000>; 341 no-map; 342 }; 343 344 adsp_mem: adsp@93e00000 { 345 reg = <0 0x93e00000 0 0x1e00000>; 346 no-map; 347 }; 348 349 ipa_fw_mem: ipa-fw@95c00000 { 350 reg = <0 0x95c00000 0 0x10000>; 351 no-map; 352 }; 353 354 ipa_gsi_mem: ipa-gsi@95c10000 { 355 reg = <0 0x95c10000 0 0x5000>; 356 no-map; 357 }; 358 359 gpu_mem: gpu@95c15000 { 360 reg = <0 0x95c15000 0 0x2000>; 361 no-map; 362 }; 363 364 spss_mem: spss@97b00000 { 365 reg = <0 0x97b00000 0 0x100000>; 366 no-map; 367 }; 368 369 qseecom_mem: qseecom@9e400000 { 370 reg = <0 0x9e400000 0 0x1400000>; 371 no-map; 372 }; 373 }; 374 375 timer { 376 compatible = "arm,armv8-timer"; 377 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 378 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 379 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 380 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 381 }; 382 383 soc: soc@0 { 384 #address-cells = <2>; 385 #size-cells = <2>; 386 ranges = <0 0 0 0 0x10 0>; 387 dma-ranges = <0 0 0 0 0x10 0>; 388 compatible = "simple-bus"; 389 390 gcc: clock-controller@100000 { 391 compatible = "qcom,gcc-sdm670"; 392 reg = <0 0x00100000 0 0x1f0000>; 393 clocks = <&rpmhcc RPMH_CXO_CLK>, 394 <&rpmhcc RPMH_CXO_CLK_A>, 395 <&sleep_clk>; 396 clock-names = "bi_tcxo", 397 "bi_tcxo_ao", 398 "sleep_clk"; 399 #clock-cells = <1>; 400 #reset-cells = <1>; 401 #power-domain-cells = <1>; 402 }; 403 404 qfprom: qfprom@784000 { 405 compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; 406 reg = <0 0x00784000 0 0x1000>; 407 #address-cells = <1>; 408 #size-cells = <1>; 409 410 qusb2_hstx_trim: hstx-trim@1eb { 411 reg = <0x1eb 0x1>; 412 bits = <1 4>; 413 }; 414 }; 415 416 sdhc_1: mmc@7c4000 { 417 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 418 reg = <0 0x007c4000 0 0x1000>, 419 <0 0x007c5000 0 0x1000>, 420 <0 0x007c8000 0 0x8000>; 421 reg-names = "hc", "cqhci", "ice"; 422 423 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "hc_irq", "pwr_irq"; 426 427 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 428 <&gcc GCC_SDCC1_APPS_CLK>, 429 <&rpmhcc RPMH_CXO_CLK>, 430 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 431 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 432 clock-names = "iface", "core", "xo", "ice", "bus"; 433 434 iommus = <&apps_smmu 0x140 0xf>; 435 436 pinctrl-names = "default", "sleep"; 437 pinctrl-0 = <&sdc1_state_on>; 438 pinctrl-1 = <&sdc1_state_off>; 439 power-domains = <&rpmhpd SDM670_CX>; 440 441 bus-width = <8>; 442 non-removable; 443 444 status = "disabled"; 445 }; 446 447 gpi_dma0: dma-controller@800000 { 448 #dma-cells = <3>; 449 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 450 reg = <0 0x00800000 0 0x60000>; 451 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 464 dma-channels = <13>; 465 dma-channel-mask = <0xfa>; 466 iommus = <&apps_smmu 0x16 0x0>; 467 status = "disabled"; 468 }; 469 470 qupv3_id_0: geniqup@8c0000 { 471 compatible = "qcom,geni-se-qup"; 472 reg = <0 0x008c0000 0 0x6000>; 473 clock-names = "m-ahb", "s-ahb"; 474 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 475 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 476 iommus = <&apps_smmu 0x3 0x0>; 477 #address-cells = <2>; 478 #size-cells = <2>; 479 ranges; 480 status = "disabled"; 481 482 i2c0: i2c@880000 { 483 compatible = "qcom,geni-i2c"; 484 reg = <0 0x00880000 0 0x4000>; 485 clock-names = "se"; 486 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&qup_i2c0_default>; 489 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 power-domains = <&rpmhpd SDM670_CX>; 493 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 494 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 495 dma-names = "tx", "rx"; 496 status = "disabled"; 497 }; 498 499 i2c1: i2c@884000 { 500 compatible = "qcom,geni-i2c"; 501 reg = <0 0x00884000 0 0x4000>; 502 clock-names = "se"; 503 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&qup_i2c1_default>; 506 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 power-domains = <&rpmhpd SDM670_CX>; 510 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 511 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 512 dma-names = "tx", "rx"; 513 status = "disabled"; 514 }; 515 516 i2c2: i2c@888000 { 517 compatible = "qcom,geni-i2c"; 518 reg = <0 0x00888000 0 0x4000>; 519 clock-names = "se"; 520 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&qup_i2c2_default>; 523 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 power-domains = <&rpmhpd SDM670_CX>; 527 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 528 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 529 dma-names = "tx", "rx"; 530 status = "disabled"; 531 }; 532 533 i2c3: i2c@88c000 { 534 compatible = "qcom,geni-i2c"; 535 reg = <0 0x0088c000 0 0x4000>; 536 clock-names = "se"; 537 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 538 pinctrl-names = "default"; 539 pinctrl-0 = <&qup_i2c3_default>; 540 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 power-domains = <&rpmhpd SDM670_CX>; 544 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 545 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 546 dma-names = "tx", "rx"; 547 status = "disabled"; 548 }; 549 550 i2c4: i2c@890000 { 551 compatible = "qcom,geni-i2c"; 552 reg = <0 0x00890000 0 0x4000>; 553 clock-names = "se"; 554 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&qup_i2c4_default>; 557 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 power-domains = <&rpmhpd SDM670_CX>; 561 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 562 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 563 dma-names = "tx", "rx"; 564 status = "disabled"; 565 }; 566 567 i2c5: i2c@894000 { 568 compatible = "qcom,geni-i2c"; 569 reg = <0 0x00894000 0 0x4000>; 570 clock-names = "se"; 571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&qup_i2c5_default>; 574 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 power-domains = <&rpmhpd SDM670_CX>; 578 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 579 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 580 dma-names = "tx", "rx"; 581 status = "disabled"; 582 }; 583 584 i2c6: i2c@898000 { 585 compatible = "qcom,geni-i2c"; 586 reg = <0 0x00898000 0 0x4000>; 587 clock-names = "se"; 588 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&qup_i2c6_default>; 591 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 power-domains = <&rpmhpd SDM670_CX>; 595 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 596 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 597 dma-names = "tx", "rx"; 598 status = "disabled"; 599 }; 600 601 i2c7: i2c@89c000 { 602 compatible = "qcom,geni-i2c"; 603 reg = <0 0x0089c000 0 0x4000>; 604 clock-names = "se"; 605 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&qup_i2c7_default>; 608 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 power-domains = <&rpmhpd SDM670_CX>; 612 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 613 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 614 dma-names = "tx", "rx"; 615 status = "disabled"; 616 }; 617 }; 618 619 gpi_dma1: dma-controller@a00000 { 620 #dma-cells = <3>; 621 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 622 reg = <0 0x00a00000 0 0x60000>; 623 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 636 dma-channels = <13>; 637 dma-channel-mask = <0xfa>; 638 iommus = <&apps_smmu 0x6d6 0x0>; 639 status = "disabled"; 640 }; 641 642 qupv3_id_1: geniqup@ac0000 { 643 compatible = "qcom,geni-se-qup"; 644 reg = <0 0x00ac0000 0 0x6000>; 645 clock-names = "m-ahb", "s-ahb"; 646 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 647 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 648 iommus = <&apps_smmu 0x6c3 0x0>; 649 #address-cells = <2>; 650 #size-cells = <2>; 651 ranges; 652 status = "disabled"; 653 654 i2c8: i2c@a80000 { 655 compatible = "qcom,geni-i2c"; 656 reg = <0 0x00a80000 0 0x4000>; 657 clock-names = "se"; 658 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&qup_i2c8_default>; 661 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 power-domains = <&rpmhpd SDM670_CX>; 665 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 666 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 667 dma-names = "tx", "rx"; 668 status = "disabled"; 669 }; 670 671 i2c9: i2c@a84000 { 672 compatible = "qcom,geni-i2c"; 673 reg = <0 0x00a84000 0 0x4000>; 674 clock-names = "se"; 675 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&qup_i2c9_default>; 678 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 power-domains = <&rpmhpd SDM670_CX>; 682 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 683 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 684 dma-names = "tx", "rx"; 685 status = "disabled"; 686 }; 687 688 i2c10: i2c@a88000 { 689 compatible = "qcom,geni-i2c"; 690 reg = <0 0x00a88000 0 0x4000>; 691 clock-names = "se"; 692 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 693 pinctrl-names = "default"; 694 pinctrl-0 = <&qup_i2c10_default>; 695 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 power-domains = <&rpmhpd SDM670_CX>; 699 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 700 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 701 dma-names = "tx", "rx"; 702 status = "disabled"; 703 }; 704 705 i2c11: i2c@a8c000 { 706 compatible = "qcom,geni-i2c"; 707 reg = <0 0x00a8c000 0 0x4000>; 708 clock-names = "se"; 709 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&qup_i2c11_default>; 712 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 power-domains = <&rpmhpd SDM670_CX>; 716 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 717 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 718 dma-names = "tx", "rx"; 719 status = "disabled"; 720 }; 721 722 i2c12: i2c@a90000 { 723 compatible = "qcom,geni-i2c"; 724 reg = <0 0x00a90000 0 0x4000>; 725 clock-names = "se"; 726 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&qup_i2c12_default>; 729 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 power-domains = <&rpmhpd SDM670_CX>; 733 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 734 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 735 dma-names = "tx", "rx"; 736 status = "disabled"; 737 }; 738 739 i2c13: i2c@a94000 { 740 compatible = "qcom,geni-i2c"; 741 reg = <0 0x00a94000 0 0x4000>; 742 clock-names = "se"; 743 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&qup_i2c13_default>; 746 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 power-domains = <&rpmhpd SDM670_CX>; 750 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 751 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 752 dma-names = "tx", "rx"; 753 status = "disabled"; 754 }; 755 756 i2c14: i2c@a98000 { 757 compatible = "qcom,geni-i2c"; 758 reg = <0 0x00a98000 0 0x4000>; 759 clock-names = "se"; 760 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 761 pinctrl-names = "default"; 762 pinctrl-0 = <&qup_i2c14_default>; 763 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 power-domains = <&rpmhpd SDM670_CX>; 767 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 768 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 769 dma-names = "tx", "rx"; 770 status = "disabled"; 771 }; 772 773 i2c15: i2c@a9c000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00a9c000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c15_default>; 780 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 power-domains = <&rpmhpd SDM670_CX>; 784 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 785 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 786 dma-names = "tx", "rx"; 787 status = "disabled"; 788 }; 789 }; 790 791 mem_noc: interconnect@1380000 { 792 compatible = "qcom,sdm670-mem-noc"; 793 reg = <0 0x01380000 0 0x27200>; 794 #interconnect-cells = <2>; 795 qcom,bcm-voters = <&apps_bcm_voter>; 796 }; 797 798 dc_noc: interconnect@14e0000 { 799 compatible = "qcom,sdm670-dc-noc"; 800 reg = <0 0x014e0000 0 0x400>; 801 #interconnect-cells = <2>; 802 qcom,bcm-voters = <&apps_bcm_voter>; 803 }; 804 805 config_noc: interconnect@1500000 { 806 compatible = "qcom,sdm670-config-noc"; 807 reg = <0 0x01500000 0 0x5080>; 808 #interconnect-cells = <2>; 809 qcom,bcm-voters = <&apps_bcm_voter>; 810 }; 811 812 system_noc: interconnect@1620000 { 813 compatible = "qcom,sdm670-system-noc"; 814 reg = <0 0x01620000 0 0x18080>; 815 #interconnect-cells = <2>; 816 qcom,bcm-voters = <&apps_bcm_voter>; 817 }; 818 819 aggre1_noc: interconnect@16e0000 { 820 compatible = "qcom,sdm670-aggre1-noc"; 821 reg = <0 0x016e0000 0 0x15080>; 822 #interconnect-cells = <2>; 823 qcom,bcm-voters = <&apps_bcm_voter>; 824 }; 825 826 aggre2_noc: interconnect@1700000 { 827 compatible = "qcom,sdm670-aggre2-noc"; 828 reg = <0 0x01700000 0 0x1f300>; 829 #interconnect-cells = <2>; 830 qcom,bcm-voters = <&apps_bcm_voter>; 831 }; 832 833 mmss_noc: interconnect@1740000 { 834 compatible = "qcom,sdm670-mmss-noc"; 835 reg = <0 0x01740000 0 0x1c100>; 836 #interconnect-cells = <2>; 837 qcom,bcm-voters = <&apps_bcm_voter>; 838 }; 839 840 tlmm: pinctrl@3400000 { 841 compatible = "qcom,sdm670-tlmm"; 842 reg = <0 0x03400000 0 0xc00000>; 843 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 844 gpio-controller; 845 #gpio-cells = <2>; 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 gpio-ranges = <&tlmm 0 0 151>; 849 850 qup_i2c0_default: qup-i2c0-default-state { 851 pins = "gpio0", "gpio1"; 852 function = "qup0"; 853 }; 854 855 qup_i2c1_default: qup-i2c1-default-state { 856 pins = "gpio17", "gpio18"; 857 function = "qup1"; 858 }; 859 860 qup_i2c2_default: qup-i2c2-default-state { 861 pins = "gpio27", "gpio28"; 862 function = "qup2"; 863 }; 864 865 qup_i2c3_default: qup-i2c3-default-state { 866 pins = "gpio41", "gpio42"; 867 function = "qup3"; 868 }; 869 870 qup_i2c4_default: qup-i2c4-default-state { 871 pins = "gpio89", "gpio90"; 872 function = "qup4"; 873 }; 874 875 qup_i2c5_default: qup-i2c5-default-state { 876 pins = "gpio85", "gpio86"; 877 function = "qup5"; 878 }; 879 880 qup_i2c6_default: qup-i2c6-default-state { 881 pins = "gpio45", "gpio46"; 882 function = "qup6"; 883 }; 884 885 qup_i2c7_default: qup-i2c7-default-state { 886 pins = "gpio93", "gpio94"; 887 function = "qup7"; 888 }; 889 890 qup_i2c8_default: qup-i2c8-default-state { 891 pins = "gpio65", "gpio66"; 892 function = "qup8"; 893 }; 894 895 qup_i2c9_default: qup-i2c9-default-state { 896 pins = "gpio6", "gpio7"; 897 function = "qup9"; 898 }; 899 900 qup_i2c10_default: qup-i2c10-default-state { 901 pins = "gpio55", "gpio56"; 902 function = "qup10"; 903 }; 904 905 qup_i2c11_default: qup-i2c11-default-state { 906 pins = "gpio31", "gpio32"; 907 function = "qup11"; 908 }; 909 910 qup_i2c12_default: qup-i2c12-default-state { 911 pins = "gpio49", "gpio50"; 912 function = "qup12"; 913 }; 914 915 qup_i2c13_default: qup-i2c13-default-state { 916 pins = "gpio105", "gpio106"; 917 function = "qup13"; 918 }; 919 920 qup_i2c14_default: qup-i2c14-default-state { 921 pins = "gpio33", "gpio34"; 922 function = "qup14"; 923 }; 924 925 qup_i2c15_default: qup-i2c15-default-state { 926 pins = "gpio81", "gpio82"; 927 function = "qup15"; 928 }; 929 930 sdc1_state_on: sdc1-on-state { 931 clk-pins { 932 pins = "sdc1_clk"; 933 bias-disable; 934 drive-strength = <16>; 935 }; 936 937 cmd-pins { 938 pins = "sdc1_cmd"; 939 bias-pull-up; 940 drive-strength = <10>; 941 }; 942 943 data-pins { 944 pins = "sdc1_data"; 945 bias-pull-up; 946 drive-strength = <10>; 947 }; 948 949 rclk-pins { 950 pins = "sdc1_rclk"; 951 bias-pull-down; 952 }; 953 }; 954 955 sdc1_state_off: sdc1-off-state { 956 clk-pins { 957 pins = "sdc1_clk"; 958 bias-disable; 959 drive-strength = <2>; 960 }; 961 962 cmd-pins { 963 pins = "sdc1_cmd"; 964 bias-pull-up; 965 drive-strength = <2>; 966 }; 967 968 data-pins { 969 pins = "sdc1_data"; 970 bias-pull-up; 971 drive-strength = <2>; 972 }; 973 974 rclk-pins { 975 pins = "sdc1_rclk"; 976 bias-pull-down; 977 }; 978 }; 979 }; 980 981 usb_1_hsphy: phy@88e2000 { 982 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 983 reg = <0 0x088e2000 0 0x400>; 984 #phy-cells = <0>; 985 986 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 987 <&rpmhcc RPMH_CXO_CLK>; 988 clock-names = "cfg_ahb", "ref"; 989 990 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 991 992 nvmem-cells = <&qusb2_hstx_trim>; 993 994 status = "disabled"; 995 }; 996 997 usb_1: usb@a6f8800 { 998 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 999 reg = <0 0x0a6f8800 0 0x400>; 1000 #address-cells = <2>; 1001 #size-cells = <2>; 1002 ranges; 1003 dma-ranges; 1004 1005 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1006 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1007 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1008 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1009 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1010 clock-names = "cfg_noc", 1011 "core", 1012 "iface", 1013 "sleep", 1014 "mock_utmi"; 1015 1016 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1017 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1018 assigned-clock-rates = <19200000>, <150000000>; 1019 1020 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1025 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1026 1027 power-domains = <&gcc USB30_PRIM_GDSC>; 1028 1029 resets = <&gcc GCC_USB30_PRIM_BCR>; 1030 1031 status = "disabled"; 1032 1033 usb_1_dwc3: usb@a600000 { 1034 compatible = "snps,dwc3"; 1035 reg = <0 0x0a600000 0 0xcd00>; 1036 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1037 iommus = <&apps_smmu 0x740 0>; 1038 snps,dis_u2_susphy_quirk; 1039 snps,dis_enblslpm_quirk; 1040 phys = <&usb_1_hsphy>; 1041 phy-names = "usb2-phy"; 1042 }; 1043 }; 1044 1045 spmi_bus: spmi@c440000 { 1046 compatible = "qcom,spmi-pmic-arb"; 1047 reg = <0 0x0c440000 0 0x1100>, 1048 <0 0x0c600000 0 0x2000000>, 1049 <0 0x0e600000 0 0x100000>, 1050 <0 0x0e700000 0 0xa0000>, 1051 <0 0x0c40a000 0 0x26000>; 1052 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1053 interrupt-names = "periph_irq"; 1054 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1055 qcom,ee = <0>; 1056 qcom,channel = <0>; 1057 #address-cells = <2>; 1058 #size-cells = <0>; 1059 interrupt-controller; 1060 #interrupt-cells = <4>; 1061 }; 1062 1063 apps_smmu: iommu@15000000 { 1064 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1065 reg = <0 0x15000000 0 0x80000>; 1066 #iommu-cells = <2>; 1067 #global-interrupts = <1>; 1068 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1133 }; 1134 1135 gladiator_noc: interconnect@17900000 { 1136 compatible = "qcom,sdm670-gladiator-noc"; 1137 reg = <0 0x17900000 0 0xd080>; 1138 #interconnect-cells = <2>; 1139 qcom,bcm-voters = <&apps_bcm_voter>; 1140 }; 1141 1142 apps_rsc: rsc@179c0000 { 1143 compatible = "qcom,rpmh-rsc"; 1144 reg = <0 0x179c0000 0 0x10000>, 1145 <0 0x179d0000 0 0x10000>, 1146 <0 0x179e0000 0 0x10000>; 1147 reg-names = "drv-0", "drv-1", "drv-2"; 1148 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1151 label = "apps_rsc"; 1152 qcom,tcs-offset = <0xd00>; 1153 qcom,drv-id = <2>; 1154 qcom,tcs-config = <ACTIVE_TCS 2>, 1155 <SLEEP_TCS 3>, 1156 <WAKE_TCS 3>, 1157 <CONTROL_TCS 1>; 1158 1159 apps_bcm_voter: bcm-voter { 1160 compatible = "qcom,bcm-voter"; 1161 }; 1162 1163 rpmhcc: clock-controller { 1164 compatible = "qcom,sdm670-rpmh-clk"; 1165 #clock-cells = <1>; 1166 clock-names = "xo"; 1167 clocks = <&xo_board>; 1168 }; 1169 1170 rpmhpd: power-controller { 1171 compatible = "qcom,sdm670-rpmhpd"; 1172 #power-domain-cells = <1>; 1173 operating-points-v2 = <&rpmhpd_opp_table>; 1174 1175 rpmhpd_opp_table: opp-table { 1176 compatible = "operating-points-v2"; 1177 1178 rpmhpd_opp_ret: opp1 { 1179 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1180 }; 1181 1182 rpmhpd_opp_min_svs: opp2 { 1183 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1184 }; 1185 1186 rpmhpd_opp_low_svs: opp3 { 1187 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1188 }; 1189 1190 rpmhpd_opp_svs: opp4 { 1191 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1192 }; 1193 1194 rpmhpd_opp_svs_l1: opp5 { 1195 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1196 }; 1197 1198 rpmhpd_opp_nom: opp6 { 1199 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1200 }; 1201 1202 rpmhpd_opp_nom_l1: opp7 { 1203 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1204 }; 1205 1206 rpmhpd_opp_nom_l2: opp8 { 1207 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1208 }; 1209 1210 rpmhpd_opp_turbo: opp9 { 1211 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1212 }; 1213 1214 rpmhpd_opp_turbo_l1: opp10 { 1215 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1216 }; 1217 }; 1218 }; 1219 }; 1220 1221 intc: interrupt-controller@17a00000 { 1222 compatible = "arm,gic-v3"; 1223 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 1224 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 1225 interrupt-controller; 1226 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1227 #interrupt-cells = <3>; 1228 }; 1229 }; 1230}; 1231