1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX75 SoC device tree source 4 * 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sdx75-gcc.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,sdx75.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom,rpmhpd.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 18/ { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 interrupt-parent = <&intc>; 22 23 chosen: chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 clock-frequency = <76800000>; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32000>; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a55"; 46 reg = <0x0 0x0>; 47 clocks = <&cpufreq_hw 0>; 48 enable-method = "psci"; 49 power-domains = <&CPU_PD0>; 50 power-domain-names = "psci"; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 next-level-cache = <&L2_0>; 55 56 L2_0: l2-cache { 57 compatible = "cache"; 58 cache-level = <2>; 59 cache-unified; 60 next-level-cache = <&L3_0>; 61 L3_0: l3-cache { 62 compatible = "cache"; 63 cache-level = <3>; 64 cache-unified; 65 }; 66 }; 67 }; 68 69 CPU1: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a55"; 72 reg = <0x0 0x100>; 73 clocks = <&cpufreq_hw 0>; 74 enable-method = "psci"; 75 power-domains = <&CPU_PD1>; 76 power-domain-names = "psci"; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 next-level-cache = <&L2_100>; 81 82 L2_100: l2-cache { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 next-level-cache = <&L3_0>; 87 }; 88 }; 89 90 CPU2: cpu@200 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a55"; 93 reg = <0x0 0x200>; 94 clocks = <&cpufreq_hw 0>; 95 enable-method = "psci"; 96 power-domains = <&CPU_PD2>; 97 power-domain-names = "psci"; 98 qcom,freq-domain = <&cpufreq_hw 0>; 99 capacity-dmips-mhz = <1024>; 100 dynamic-power-coefficient = <100>; 101 next-level-cache = <&L2_200>; 102 103 L2_200: l2-cache { 104 compatible = "cache"; 105 cache-level = <2>; 106 cache-unified; 107 next-level-cache = <&L3_0>; 108 }; 109 }; 110 111 CPU3: cpu@300 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x0 0x300>; 115 clocks = <&cpufreq_hw 0>; 116 enable-method = "psci"; 117 power-domains = <&CPU_PD3>; 118 power-domain-names = "psci"; 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 capacity-dmips-mhz = <1024>; 121 dynamic-power-coefficient = <100>; 122 next-level-cache = <&L2_300>; 123 124 L2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 cpu-map { 133 cluster0 { 134 core0 { 135 cpu = <&CPU0>; 136 }; 137 138 core1 { 139 cpu = <&CPU1>; 140 }; 141 142 core2 { 143 cpu = <&CPU2>; 144 }; 145 146 core3 { 147 cpu = <&CPU3>; 148 }; 149 }; 150 }; 151 152 idle-states { 153 entry-method = "psci"; 154 155 CPU_OFF: cpu-sleep-0 { 156 compatible = "arm,idle-state"; 157 entry-latency-us = <235>; 158 exit-latency-us = <428>; 159 min-residency-us = <1774>; 160 arm,psci-suspend-param = <0x40000003>; 161 local-timer-stop; 162 }; 163 164 CPU_RAIL_OFF: cpu-rail-sleep-1 { 165 compatible = "arm,idle-state"; 166 entry-latency-us = <800>; 167 exit-latency-us = <750>; 168 min-residency-us = <4090>; 169 arm,psci-suspend-param = <0x40000004>; 170 local-timer-stop; 171 }; 172 173 }; 174 175 domain-idle-states { 176 CLUSTER_SLEEP_0: cluster-sleep-0 { 177 compatible = "domain-idle-state"; 178 arm,psci-suspend-param = <0x41000044>; 179 entry-latency-us = <1050>; 180 exit-latency-us = <2500>; 181 min-residency-us = <5309>; 182 }; 183 184 CLUSTER_SLEEP_1: cluster-sleep-1 { 185 compatible = "domain-idle-state"; 186 arm,psci-suspend-param = <0x41001344>; 187 entry-latency-us = <2761>; 188 exit-latency-us = <3964>; 189 min-residency-us = <8467>; 190 }; 191 192 CLUSTER_SLEEP_2: cluster-sleep-2 { 193 compatible = "domain-idle-state"; 194 arm,psci-suspend-param = <0x4100b344>; 195 entry-latency-us = <2793>; 196 exit-latency-us = <4023>; 197 min-residency-us = <9826>; 198 }; 199 }; 200 }; 201 202 firmware { 203 scm: scm { 204 compatible = "qcom,scm-sdx75", "qcom,scm"; 205 }; 206 }; 207 208 clk_virt: interconnect-0 { 209 compatible = "qcom,sdx75-clk-virt"; 210 #interconnect-cells = <2>; 211 qcom,bcm-voters = <&apps_bcm_voter>; 212 clocks = <&rpmhcc RPMH_QPIC_CLK>; 213 }; 214 215 mc_virt: interconnect-1 { 216 compatible = "qcom,sdx75-mc-virt"; 217 #interconnect-cells = <2>; 218 qcom,bcm-voters = <&apps_bcm_voter>; 219 }; 220 221 memory@80000000 { 222 device_type = "memory"; 223 reg = <0x0 0x80000000 0x0 0x0>; 224 }; 225 226 pmu { 227 compatible = "arm,armv8-pmuv3"; 228 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 229 }; 230 231 psci { 232 compatible = "arm,psci-1.0"; 233 method = "smc"; 234 235 CPU_PD0: power-domain-cpu0 { 236 #power-domain-cells = <0>; 237 power-domains = <&CLUSTER_PD>; 238 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 239 }; 240 241 CPU_PD1: power-domain-cpu1 { 242 #power-domain-cells = <0>; 243 power-domains = <&CLUSTER_PD>; 244 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 245 }; 246 247 CPU_PD2: power-domain-cpu2 { 248 #power-domain-cells = <0>; 249 power-domains = <&CLUSTER_PD>; 250 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 251 }; 252 253 CPU_PD3: power-domain-cpu3 { 254 #power-domain-cells = <0>; 255 power-domains = <&CLUSTER_PD>; 256 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>; 257 }; 258 259 CLUSTER_PD: power-domain-cpu-cluster0 { 260 #power-domain-cells = <0>; 261 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>; 262 }; 263 }; 264 265 reserved-memory { 266 #address-cells = <2>; 267 #size-cells = <2>; 268 ranges; 269 270 gunyah_hyp_mem: gunyah-hyp@80000000 { 271 reg = <0x0 0x80000000 0x0 0x800000>; 272 no-map; 273 }; 274 275 hyp_elf_package_mem: hyp-elf-package@80800000 { 276 reg = <0x0 0x80800000 0x0 0x200000>; 277 no-map; 278 }; 279 280 access_control_db_mem: access-control-db@81380000 { 281 reg = <0x0 0x81380000 0x0 0x80000>; 282 no-map; 283 }; 284 285 qteetz_mem: qteetz@814e0000 { 286 reg = <0x0 0x814e0000 0x0 0x2a0000>; 287 no-map; 288 }; 289 290 trusted_apps_mem: trusted-apps@81780000 { 291 reg = <0x0 0x81780000 0x0 0xa00000>; 292 no-map; 293 }; 294 295 xbl_ramdump_mem: xbl-ramdump@87a00000 { 296 reg = <0x0 0x87a00000 0x0 0x1c0000>; 297 no-map; 298 }; 299 300 cpucp_fw_mem: cpucp-fw@87c00000 { 301 reg = <0x0 0x87c00000 0x0 0x100000>; 302 no-map; 303 }; 304 305 xbl_dtlog_mem: xbl-dtlog@87d00000 { 306 reg = <0x0 0x87d00000 0x0 0x40000>; 307 no-map; 308 }; 309 310 xbl_sc_mem: xbl-sc@87d40000 { 311 reg = <0x0 0x87d40000 0x0 0x40000>; 312 no-map; 313 }; 314 315 modem_efs_shared_mem: modem-efs-shared@87d80000 { 316 reg = <0x0 0x87d80000 0x0 0x10000>; 317 no-map; 318 }; 319 320 aop_image_mem: aop-image@87e00000 { 321 reg = <0x0 0x87e00000 0x0 0x20000>; 322 no-map; 323 }; 324 325 smem_mem: smem@87e20000 { 326 reg = <0x0 0x87e20000 0x0 0xc0000>; 327 no-map; 328 }; 329 330 aop_cmd_db_mem: aop-cmd-db@87ee0000 { 331 compatible = "qcom,cmd-db"; 332 reg = <0x0 0x87ee0000 0x0 0x20000>; 333 no-map; 334 }; 335 336 aop_config_mem: aop-config@87f00000 { 337 reg = <0x0 0x87f00000 0x0 0x20000>; 338 no-map; 339 }; 340 341 ipa_fw_mem: ipa-fw@87f20000 { 342 reg = <0x0 0x87f20000 0x0 0x10000>; 343 no-map; 344 }; 345 346 secdata_mem: secdata@87f30000 { 347 reg = <0x0 0x87f30000 0x0 0x1000>; 348 no-map; 349 }; 350 351 tme_crashdump_mem: tme-crashdump@87f31000 { 352 reg = <0x0 0x87f31000 0x0 0x40000>; 353 no-map; 354 }; 355 356 tme_log_mem: tme-log@87f71000 { 357 reg = <0x0 0x87f71000 0x0 0x4000>; 358 no-map; 359 }; 360 361 uefi_log_mem: uefi-log@87f75000 { 362 reg = <0x0 0x87f75000 0x0 0x10000>; 363 no-map; 364 }; 365 366 qdss_mem: qdss@88800000 { 367 reg = <0x0 0x88800000 0x0 0x300000>; 368 no-map; 369 }; 370 371 audio_heap_mem: audio-heap@88b00000 { 372 compatible = "shared-dma-pool"; 373 reg = <0x0 0x88b00000 0x0 0x400000>; 374 no-map; 375 }; 376 377 mpss_dsmharq_mem: mpss-dsmharq@88f00000 { 378 reg = <0x0 0x88f00000 0x0 0x5080000>; 379 no-map; 380 }; 381 382 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 { 383 reg = <0x0 0x8df80000 0x0 0x80000>; 384 no-map; 385 }; 386 387 mpssadsp_mem: mpssadsp@8e000000 { 388 reg = <0x0 0x8e000000 0x0 0xf400000>; 389 no-map; 390 }; 391 392 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 { 393 reg = <0x0 0xbdb00000 0x0 0x2000000>; 394 no-map; 395 }; 396 397 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 { 398 reg = <0x0 0xbfb00000 0x0 0x100000>; 399 no-map; 400 }; 401 402 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 { 403 reg = <0x0 0xbfc00000 0x0 0x400000>; 404 no-map; 405 }; 406 }; 407 408 smem: qcom,smem { 409 compatible = "qcom,smem"; 410 memory-region = <&smem_mem>; 411 hwlocks = <&tcsr_mutex 3>; 412 }; 413 414 soc: soc { 415 compatible = "simple-bus"; 416 #address-cells = <2>; 417 #size-cells = <2>; 418 ranges = <0 0 0 0 0x10 0>; 419 dma-ranges = <0 0 0 0 0x10 0>; 420 421 gcc: clock-controller@80000 { 422 compatible = "qcom,sdx75-gcc"; 423 reg = <0x0 0x0080000 0x0 0x1f7400>; 424 clocks = <&rpmhcc RPMH_CXO_CLK>, 425 <&sleep_clk>, 426 <0>, 427 <0>, 428 <0>, 429 <0>, 430 <0>, 431 <0>, 432 <0>, 433 <0>, 434 <0>, 435 <0>, 436 <0>, 437 <0>, 438 <0>; 439 #clock-cells = <1>; 440 #reset-cells = <1>; 441 #power-domain-cells = <1>; 442 }; 443 444 qupv3_id_0: geniqup@9c0000 { 445 compatible = "qcom,geni-se-qup"; 446 reg = <0x0 0x009c0000 0x0 0x2000>; 447 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 448 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 449 clock-names = "m-ahb", 450 "s-ahb"; 451 iommus = <&apps_smmu 0xe3 0x0>; 452 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 453 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 454 interconnect-names = "qup-core"; 455 #address-cells = <2>; 456 #size-cells = <2>; 457 ranges; 458 status = "disabled"; 459 460 uart1: serial@984000 { 461 compatible = "qcom,geni-debug-uart"; 462 reg = <0x0 0x00984000 0x0 0x4000>; 463 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 464 clock-names = "se"; 465 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 466 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 467 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 468 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 469 interconnect-names = "qup-core", 470 "qup-config"; 471 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 472 pinctrl-0 = <&qupv3_se1_2uart_active>; 473 pinctrl-1 = <&qupv3_se1_2uart_sleep>; 474 pinctrl-names = "default", 475 "sleep"; 476 status = "disabled"; 477 }; 478 }; 479 480 usb_hsphy: phy@ff4000 { 481 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; 482 reg = <0x0 0x00ff4000 0x0 0x154>; 483 #phy-cells = <0>; 484 485 clocks = <&rpmhcc RPMH_CXO_CLK>; 486 clock-names = "ref"; 487 488 resets = <&gcc GCC_QUSB2PHY_BCR>; 489 490 status = "disabled"; 491 }; 492 493 usb_qmpphy: phy@ff6000 { 494 compatible = "qcom,sdx75-qmp-usb3-uni-phy"; 495 reg = <0x0 0x00ff6000 0x0 0x2000>; 496 497 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 498 <&gcc GCC_USB2_CLKREF_EN>, 499 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 500 <&gcc GCC_USB3_PHY_PIPE_CLK>; 501 clock-names = "aux", 502 "ref", 503 "cfg_ahb", 504 "pipe"; 505 506 power-domains = <&gcc GCC_USB3_PHY_GDSC>; 507 508 resets = <&gcc GCC_USB3_PHY_BCR>, 509 <&gcc GCC_USB3PHY_PHY_BCR>; 510 reset-names = "phy", 511 "phy_phy"; 512 513 #clock-cells = <0>; 514 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 515 516 #phy-cells = <0>; 517 518 status = "disabled"; 519 }; 520 521 system_noc: interconnect@1640000 { 522 compatible = "qcom,sdx75-system-noc"; 523 reg = <0x0 0x01640000 0x0 0x4b400>; 524 #interconnect-cells = <2>; 525 qcom,bcm-voters = <&apps_bcm_voter>; 526 }; 527 528 pcie_anoc: interconnect@16c0000 { 529 compatible = "qcom,sdx75-pcie-anoc"; 530 reg = <0x0 0x016c0000 0x0 0x14200>; 531 #interconnect-cells = <2>; 532 qcom,bcm-voters = <&apps_bcm_voter>; 533 }; 534 535 tcsr_mutex: hwlock@1f40000 { 536 compatible = "qcom,tcsr-mutex"; 537 reg = <0x0 0x01f40000 0x0 0x40000>; 538 #hwlock-cells = <1>; 539 }; 540 541 usb: usb@a6f8800 { 542 compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; 543 reg = <0x0 0x0a6f8800 0x0 0x400>; 544 #address-cells = <2>; 545 #size-cells = <2>; 546 ranges; 547 548 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 549 <&gcc GCC_USB30_MASTER_CLK>, 550 <&gcc GCC_USB30_MSTR_AXI_CLK>, 551 <&gcc GCC_USB30_SLEEP_CLK>, 552 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 553 clock-names = "cfg_noc", 554 "core", 555 "iface", 556 "sleep", 557 "mock_utmi"; 558 559 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 560 <&gcc GCC_USB30_MASTER_CLK>; 561 assigned-clock-rates = <19200000>, <200000000>; 562 563 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 564 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 565 <&pdc 9 IRQ_TYPE_EDGE_RISING>, 566 <&pdc 10 IRQ_TYPE_EDGE_RISING>; 567 interrupt-names = "hs_phy_irq", 568 "ss_phy_irq", 569 "dm_hs_phy_irq", 570 "dp_hs_phy_irq"; 571 572 power-domains = <&gcc GCC_USB30_GDSC>; 573 574 resets = <&gcc GCC_USB30_BCR>; 575 576 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 577 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 579 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>; 580 interconnect-names = "usb-ddr", 581 "apps-usb"; 582 583 status = "disabled"; 584 585 usb_dwc3: usb@a600000 { 586 compatible = "snps,dwc3"; 587 reg = <0x0 0x0a600000 0x0 0xcd00>; 588 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 589 iommus = <&apps_smmu 0x80 0x0>; 590 snps,dis_u2_susphy_quirk; 591 snps,dis_enblslpm_quirk; 592 phys = <&usb_hsphy>, 593 <&usb_qmpphy>; 594 phy-names = "usb2-phy", 595 "usb3-phy"; 596 597 ports { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 601 port@0 { 602 reg = <0>; 603 604 usb_1_dwc3_hs: endpoint { 605 }; 606 }; 607 608 port@1 { 609 reg = <1>; 610 611 usb_1_dwc3_ss: endpoint { 612 }; 613 }; 614 }; 615 }; 616 }; 617 618 pdc: interrupt-controller@b220000 { 619 compatible = "qcom,sdx75-pdc", "qcom,pdc"; 620 reg = <0x0 0xb220000 0x0 0x30000>, 621 <0x0 0x174000f0 0x0 0x64>; 622 qcom,pdc-ranges = <0 147 52>, 623 <52 266 32>, 624 <84 500 59>; 625 #interrupt-cells = <2>; 626 interrupt-parent = <&intc>; 627 interrupt-controller; 628 }; 629 630 spmi_bus: spmi@c400000 { 631 compatible = "qcom,spmi-pmic-arb"; 632 reg = <0x0 0x0c400000 0x0 0x3000>, 633 <0x0 0x0c500000 0x0 0x400000>, 634 <0x0 0x0c440000 0x0 0x80000>, 635 <0x0 0x0c4c0000 0x0 0x10000>, 636 <0x0 0x0c42d000 0x0 0x4000>; 637 reg-names = "core", 638 "chnls", 639 "obsrvr", 640 "intr", 641 "cnfg"; 642 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 643 interrupt-names = "periph_irq"; 644 qcom,ee = <0>; 645 qcom,channel = <0>; 646 qcom,bus-id = <0>; 647 #address-cells = <2>; 648 #size-cells = <0>; 649 interrupt-controller; 650 #interrupt-cells = <4>; 651 }; 652 653 tlmm: pinctrl@f000000 { 654 compatible = "qcom,sdx75-tlmm"; 655 reg = <0x0 0x0f000000 0x0 0x400000>; 656 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 657 gpio-controller; 658 #gpio-cells = <2>; 659 gpio-ranges = <&tlmm 0 0 133>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 wakeup-parent = <&pdc>; 663 664 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { 665 tx-pins { 666 pins = "gpio12"; 667 function = "qup_se1_l2_mira"; 668 drive-strength = <2>; 669 bias-disable; 670 }; 671 672 rx-pins { 673 pins = "gpio13"; 674 function = "qup_se1_l3_mira"; 675 drive-strength = <2>; 676 bias-disable; 677 }; 678 }; 679 680 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state { 681 pins = "gpio12", "gpio13"; 682 function = "gpio"; 683 drive-strength = <2>; 684 bias-pull-down; 685 }; 686 }; 687 688 apps_smmu: iommu@15000000 { 689 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 690 reg = <0x0 0x15000000 0x0 0x40000>; 691 #iommu-cells = <2>; 692 #global-interrupts = <2>; 693 dma-coherent; 694 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 727 }; 728 729 intc: interrupt-controller@17200000 { 730 compatible = "arm,gic-v3"; 731 #interrupt-cells = <3>; 732 interrupt-controller; 733 #redistributor-regions = <1>; 734 redistributor-stride = <0x0 0x20000>; 735 reg = <0x0 0x17200000 0x0 0x10000>, 736 <0x0 0x17260000 0x0 0x80000>; 737 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 738 }; 739 740 timer@17420000 { 741 compatible = "arm,armv7-timer-mem"; 742 reg = <0x0 0x17420000 0x0 0x1000>; 743 #address-cells = <1>; 744 #size-cells = <1>; 745 ranges = <0 0 0 0x20000000>; 746 747 frame@17421000 { 748 reg = <0x17421000 0x1000>, 749 <0x17422000 0x1000>; 750 frame-number = <0>; 751 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 753 }; 754 755 frame@17423000 { 756 reg = <0x17423000 0x1000>; 757 frame-number = <1>; 758 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 759 status = "disabled"; 760 }; 761 762 frame@17425000 { 763 reg = <0x17425000 0x1000>; 764 frame-number = <2>; 765 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 766 status = "disabled"; 767 }; 768 769 frame@17427000 { 770 reg = <0x17427000 0x1000>; 771 frame-number = <3>; 772 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 773 status = "disabled"; 774 }; 775 776 frame@17429000 { 777 reg = <0x17429000 0x1000>; 778 frame-number = <4>; 779 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 780 status = "disabled"; 781 }; 782 783 frame@1742b000 { 784 reg = <0x1742b000 0x1000>; 785 frame-number = <5>; 786 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 787 status = "disabled"; 788 }; 789 790 frame@1742d000 { 791 reg = <0x1742d000 0x1000>; 792 frame-number = <6>; 793 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 794 status = "disabled"; 795 }; 796 }; 797 798 apps_rsc: rsc@17a00000 { 799 label = "apps_rsc"; 800 compatible = "qcom,rpmh-rsc"; 801 reg = <0x0 0x17a00000 0x0 0x10000>, 802 <0x0 0x17a10000 0x0 0x10000>, 803 <0x0 0x17a20000 0x0 0x10000>; 804 reg-names = "drv-0", "drv-1", "drv-2"; 805 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 808 809 power-domains = <&CLUSTER_PD>; 810 qcom,tcs-offset = <0xd00>; 811 qcom,drv-id = <2>; 812 qcom,tcs-config = <ACTIVE_TCS 3>, 813 <SLEEP_TCS 2>, 814 <WAKE_TCS 2>, 815 <CONTROL_TCS 0>; 816 817 apps_bcm_voter: bcm-voter { 818 compatible = "qcom,bcm-voter"; 819 }; 820 821 rpmhcc: clock-controller { 822 compatible = "qcom,sdx75-rpmh-clk"; 823 clocks = <&xo_board>; 824 clock-names = "xo"; 825 #clock-cells = <1>; 826 }; 827 828 rpmhpd: power-controller { 829 compatible = "qcom,sdx75-rpmhpd"; 830 #power-domain-cells = <1>; 831 operating-points-v2 = <&rpmhpd_opp_table>; 832 833 rpmhpd_opp_table: opp-table { 834 compatible = "operating-points-v2"; 835 836 rpmhpd_opp_ret: opp-16 { 837 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 838 }; 839 840 rpmhpd_opp_min_svs: opp-48 { 841 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 842 }; 843 844 rpmhpd_opp_low_svs: opp-64 { 845 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 846 }; 847 848 rpmhpd_opp_svs: opp-128 { 849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 850 }; 851 852 rpmhpd_opp_svs_l1: opp-192 { 853 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 854 }; 855 856 rpmhpd_opp_nom: opp-256 { 857 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 858 }; 859 860 rpmhpd_opp_nom_l1: opp-320 { 861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 862 }; 863 864 rpmhpd_opp_nom_l2: opp-336 { 865 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 866 }; 867 868 rpmhpd_opp_turbo: opp-384 { 869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 870 }; 871 872 rpmhpd_opp_turbo_l1: opp-416 { 873 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 874 }; 875 }; 876 }; 877 }; 878 879 cpufreq_hw: cpufreq@17d91000 { 880 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss"; 881 reg = <0x0 0x17d91000 0x0 0x1000>; 882 reg-names = "freq-domain0"; 883 clocks = <&rpmhcc RPMH_CXO_CLK>, 884 <&gcc GPLL0>; 885 clock-names = "xo", 886 "alternate"; 887 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "dcvsh-irq-0"; 889 #freq-domain-cells = <1>; 890 #clock-cells = <1>; 891 }; 892 893 dc_noc: interconnect@190e0000 { 894 compatible = "qcom,sdx75-dc-noc"; 895 reg = <0x0 0x190e0000 0x0 0x8200>; 896 #interconnect-cells = <2>; 897 qcom,bcm-voters = <&apps_bcm_voter>; 898 }; 899 900 gem_noc: interconnect@19100000 { 901 compatible = "qcom,sdx75-gem-noc"; 902 reg = <0x0 0x19100000 0x0 0x34080>; 903 #interconnect-cells = <2>; 904 qcom,bcm-voters = <&apps_bcm_voter>; 905 }; 906 }; 907 908 timer { 909 compatible = "arm,armv8-timer"; 910 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 911 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 912 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 913 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 914 }; 915}; 916