1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6350.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/mailbox/qcom-ipcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <76800000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32764>; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo560"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 capacity-dmips-mhz = <1024>; 44 dynamic-power-coefficient = <100>; 45 next-level-cache = <&L2_0>; 46 qcom,freq-domain = <&cpufreq_hw 0>; 47 #cooling-cells = <2>; 48 L2_0: l2-cache { 49 compatible = "cache"; 50 next-level-cache = <&L3_0>; 51 L3_0: l3-cache { 52 compatible = "cache"; 53 }; 54 }; 55 }; 56 57 CPU1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "qcom,kryo560"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 capacity-dmips-mhz = <1024>; 63 dynamic-power-coefficient = <100>; 64 next-level-cache = <&L2_100>; 65 qcom,freq-domain = <&cpufreq_hw 0>; 66 #cooling-cells = <2>; 67 L2_100: l2-cache { 68 compatible = "cache"; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo560"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 dynamic-power-coefficient = <100>; 80 next-level-cache = <&L2_200>; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 L2_200: l2-cache { 84 compatible = "cache"; 85 next-level-cache = <&L3_0>; 86 }; 87 }; 88 89 CPU3: cpu@300 { 90 device_type = "cpu"; 91 compatible = "qcom,kryo560"; 92 reg = <0x0 0x300>; 93 enable-method = "psci"; 94 capacity-dmips-mhz = <1024>; 95 dynamic-power-coefficient = <100>; 96 next-level-cache = <&L2_300>; 97 qcom,freq-domain = <&cpufreq_hw 0>; 98 #cooling-cells = <2>; 99 L2_300: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 }; 103 }; 104 105 CPU4: cpu@400 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo560"; 108 reg = <0x0 0x400>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1024>; 111 dynamic-power-coefficient = <100>; 112 next-level-cache = <&L2_400>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 #cooling-cells = <2>; 115 L2_400: l2-cache { 116 compatible = "cache"; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU5: cpu@500 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo560"; 124 reg = <0x0 0x500>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 dynamic-power-coefficient = <100>; 128 next-level-cache = <&L2_500>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 #cooling-cells = <2>; 131 L2_500: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 136 }; 137 138 CPU6: cpu@600 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo560"; 141 reg = <0x0 0x600>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1894>; 144 dynamic-power-coefficient = <703>; 145 next-level-cache = <&L2_600>; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 #cooling-cells = <2>; 148 L2_600: l2-cache { 149 compatible = "cache"; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU7: cpu@700 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo560"; 157 reg = <0x0 0x700>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1894>; 160 dynamic-power-coefficient = <703>; 161 next-level-cache = <&L2_700>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 L2_700: l2-cache { 165 compatible = "cache"; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&CPU0>; 174 }; 175 176 core1 { 177 cpu = <&CPU1>; 178 }; 179 180 core2 { 181 cpu = <&CPU2>; 182 }; 183 184 core3 { 185 cpu = <&CPU3>; 186 }; 187 188 core4 { 189 cpu = <&CPU4>; 190 }; 191 192 core5 { 193 cpu = <&CPU5>; 194 }; 195 196 core6 { 197 cpu = <&CPU6>; 198 }; 199 200 core7 { 201 cpu = <&CPU7>; 202 }; 203 }; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-sm6350", "qcom,scm"; 210 #reset-cells = <1>; 211 }; 212 }; 213 214 memory@80000000 { 215 device_type = "memory"; 216 /* We expect the bootloader to fill in the size */ 217 reg = <0x0 0x80000000 0x0 0x0>; 218 }; 219 220 pmu { 221 compatible = "arm,armv8-pmuv3"; 222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 223 }; 224 225 psci { 226 compatible = "arm,psci-1.0"; 227 method = "smc"; 228 }; 229 230 reserved_memory: reserved-memory { 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 235 hyp_mem: memory@80000000 { 236 reg = <0 0x80000000 0 0x600000>; 237 no-map; 238 }; 239 240 xbl_aop_mem: memory@80700000 { 241 reg = <0 0x80700000 0 0x160000>; 242 no-map; 243 }; 244 245 cmd_db: memory@80860000 { 246 compatible = "qcom,cmd-db"; 247 reg = <0 0x80860000 0 0x20000>; 248 no-map; 249 }; 250 251 sec_apps_mem: memory@808ff000 { 252 reg = <0 0x808ff000 0 0x1000>; 253 no-map; 254 }; 255 256 smem_mem: memory@80900000 { 257 reg = <0 0x80900000 0 0x200000>; 258 no-map; 259 }; 260 261 cdsp_sec_mem: memory@80b00000 { 262 reg = <0 0x80b00000 0 0x1e00000>; 263 no-map; 264 }; 265 266 pil_camera_mem: memory@86000000 { 267 reg = <0 0x86000000 0 0x500000>; 268 no-map; 269 }; 270 271 pil_npu_mem: memory@86500000 { 272 reg = <0 0x86500000 0 0x500000>; 273 no-map; 274 }; 275 276 pil_video_mem: memory@86a00000 { 277 reg = <0 0x86a00000 0 0x500000>; 278 no-map; 279 }; 280 281 pil_cdsp_mem: memory@86f00000 { 282 reg = <0 0x86f00000 0 0x1e00000>; 283 no-map; 284 }; 285 286 pil_adsp_mem: memory@88d00000 { 287 reg = <0 0x88d00000 0 0x2800000>; 288 no-map; 289 }; 290 291 wlan_fw_mem: memory@8b500000 { 292 reg = <0 0x8b500000 0 0x200000>; 293 no-map; 294 }; 295 296 pil_ipa_fw_mem: memory@8b700000 { 297 reg = <0 0x8b700000 0 0x10000>; 298 no-map; 299 }; 300 301 pil_ipa_gsi_mem: memory@8b710000 { 302 reg = <0 0x8b710000 0 0x5400>; 303 no-map; 304 }; 305 306 pil_gpu_mem: memory@8b715400 { 307 reg = <0 0x8b715400 0 0x2000>; 308 no-map; 309 }; 310 311 pil_modem_mem: memory@8b800000 { 312 reg = <0 0x8b800000 0 0xf800000>; 313 no-map; 314 }; 315 316 cont_splash_memory: memory@a0000000 { 317 reg = <0 0xa0000000 0 0x2300000>; 318 no-map; 319 }; 320 321 dfps_data_memory: memory@a2300000 { 322 reg = <0 0xa2300000 0 0x100000>; 323 no-map; 324 }; 325 326 removed_region: memory@c0000000 { 327 reg = <0 0xc0000000 0 0x3900000>; 328 no-map; 329 }; 330 331 debug_region: memory@ffb00000 { 332 reg = <0 0xffb00000 0 0xc0000>; 333 no-map; 334 }; 335 336 last_log_region: memory@ffbc0000 { 337 reg = <0 0xffbc0000 0 0x40000>; 338 no-map; 339 }; 340 341 ramoops: ramoops@ffc00000 { 342 compatible = "removed-dma-pool", "ramoops"; 343 reg = <0 0xffc00000 0 0x00100000>; 344 record-size = <0x1000>; 345 console-size = <0x40000>; 346 ftrace-size = <0x0>; 347 msg-size = <0x20000 0x20000>; 348 cc-size = <0x0>; 349 no-map; 350 }; 351 352 cmdline_region: memory@ffd00000 { 353 reg = <0 0xffd00000 0 0x1000>; 354 no-map; 355 }; 356 }; 357 358 smem { 359 compatible = "qcom,smem"; 360 memory-region = <&smem_mem>; 361 hwlocks = <&tcsr_mutex 3>; 362 }; 363 364 smp2p-adsp { 365 compatible = "qcom,smp2p"; 366 qcom,smem = <443>, <429>; 367 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 368 IPCC_MPROC_SIGNAL_SMP2P 369 IRQ_TYPE_EDGE_RISING>; 370 mboxes = <&ipcc IPCC_CLIENT_LPASS 371 IPCC_MPROC_SIGNAL_SMP2P>; 372 373 qcom,local-pid = <0>; 374 qcom,remote-pid = <2>; 375 376 smp2p_adsp_out: master-kernel { 377 qcom,entry-name = "master-kernel"; 378 #qcom,smem-state-cells = <1>; 379 }; 380 381 smp2p_adsp_in: slave-kernel { 382 qcom,entry-name = "slave-kernel"; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 }; 387 388 smp2p-cdsp { 389 compatible = "qcom,smp2p"; 390 qcom,smem = <94>, <432>; 391 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 392 IPCC_MPROC_SIGNAL_SMP2P 393 IRQ_TYPE_EDGE_RISING>; 394 mboxes = <&ipcc IPCC_CLIENT_CDSP 395 IPCC_MPROC_SIGNAL_SMP2P>; 396 397 qcom,local-pid = <0>; 398 qcom,remote-pid = <5>; 399 400 smp2p_cdsp_out: master-kernel { 401 qcom,entry-name = "master-kernel"; 402 #qcom,smem-state-cells = <1>; 403 }; 404 405 smp2p_cdsp_in: slave-kernel { 406 qcom,entry-name = "slave-kernel"; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 }; 410 }; 411 412 smp2p-mpss { 413 compatible = "qcom,smp2p"; 414 qcom,smem = <435>, <428>; 415 416 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 417 IPCC_MPROC_SIGNAL_SMP2P 418 IRQ_TYPE_EDGE_RISING>; 419 mboxes = <&ipcc IPCC_CLIENT_MPSS 420 IPCC_MPROC_SIGNAL_SMP2P>; 421 422 qcom,local-pid = <0>; 423 qcom,remote-pid = <1>; 424 425 modem_smp2p_out: master-kernel { 426 qcom,entry-name = "master-kernel"; 427 #qcom,smem-state-cells = <1>; 428 }; 429 430 modem_smp2p_in: slave-kernel { 431 qcom,entry-name = "slave-kernel"; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges = <0 0 0 0 0x10 0>; 442 dma-ranges = <0 0 0 0 0x10 0>; 443 compatible = "simple-bus"; 444 445 gcc: clock-controller@100000 { 446 compatible = "qcom,gcc-sm6350"; 447 reg = <0 0x00100000 0 0x1f0000>; 448 #clock-cells = <1>; 449 #reset-cells = <1>; 450 #power-domain-cells = <1>; 451 clock-names = "bi_tcxo", 452 "bi_tcxo_ao", 453 "sleep_clk"; 454 clocks = <&rpmhcc RPMH_CXO_CLK>, 455 <&rpmhcc RPMH_CXO_CLK_A>, 456 <&sleep_clk>; 457 }; 458 459 ipcc: mailbox@408000 { 460 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 461 reg = <0 0x00408000 0 0x1000>; 462 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-controller; 464 #interrupt-cells = <3>; 465 #mbox-cells = <2>; 466 }; 467 468 rng: rng@793000 { 469 compatible = "qcom,prng-ee"; 470 reg = <0 0x00793000 0 0x1000>; 471 clocks = <&gcc GCC_PRNG_AHB_CLK>; 472 clock-names = "core"; 473 }; 474 475 sdhc_1: sdhci@7c4000 { 476 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 477 reg = <0 0x007c4000 0 0x1000>, 478 <0 0x007c5000 0 0x1000>, 479 <0 0x007c8000 0 0x8000>; 480 reg-names = "hc", "cqhci", "ice"; 481 482 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "hc_irq", "pwr_irq"; 485 486 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 487 <&gcc GCC_SDCC1_APPS_CLK>, 488 <&rpmhcc RPMH_CXO_CLK>; 489 clock-names = "iface", "core", "xo"; 490 qcom,dll-config = <0x000f642c>; 491 qcom,ddr-config = <0x80040868>; 492 power-domains = <&rpmhpd 0>; 493 operating-points-v2 = <&sdhc1_opp_table>; 494 bus-width = <8>; 495 non-removable; 496 supports-cqe; 497 498 status = "disabled"; 499 500 sdhc1_opp_table: sdhc1-opp-table { 501 compatible = "operating-points-v2"; 502 503 opp-19200000 { 504 opp-hz = /bits/ 64 <19200000>; 505 required-opps = <&rpmhpd_opp_min_svs>; 506 }; 507 508 opp-100000000 { 509 opp-hz = /bits/ 64 <100000000>; 510 required-opps = <&rpmhpd_opp_low_svs>; 511 }; 512 513 opp-384000000 { 514 opp-hz = /bits/ 64 <384000000>; 515 required-opps = <&rpmhpd_opp_svs_l1>; 516 }; 517 }; 518 }; 519 520 qupv3_id_1: geniqup@9c0000 { 521 compatible = "qcom,geni-se-qup"; 522 reg = <0x0 0x9c0000 0x0 0x2000>; 523 clock-names = "m-ahb", "s-ahb"; 524 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 525 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 526 #address-cells = <2>; 527 #size-cells = <2>; 528 iommus = <&apps_smmu 0x4c3 0x0>; 529 ranges; 530 status = "disabled"; 531 532 uart2: serial@98c000 { 533 compatible = "qcom,geni-debug-uart"; 534 reg = <0 0x98c000 0 0x4000>; 535 clock-names = "se"; 536 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&qup_uart2_default>; 539 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 540 status = "disabled"; 541 }; 542 }; 543 544 tcsr_mutex: hwlock@1f40000 { 545 compatible = "qcom,tcsr-mutex"; 546 reg = <0x0 0x01f40000 0x0 0x40000>; 547 #hwlock-cells = <1>; 548 }; 549 550 adsp: remoteproc@3000000 { 551 compatible = "qcom,sm6350-adsp-pas"; 552 reg = <0 0x03000000 0 0x100>; 553 554 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 555 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 556 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 557 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 558 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 559 interrupt-names = "wdog", "fatal", "ready", 560 "handover", "stop-ack"; 561 562 clocks = <&rpmhcc RPMH_CXO_CLK>; 563 clock-names = "xo"; 564 565 power-domains = <&rpmhpd SM6350_LCX>, 566 <&rpmhpd SM6350_LMX>; 567 power-domain-names = "lcx", "lmx"; 568 569 memory-region = <&pil_adsp_mem>; 570 571 qcom,qmp = <&aoss_qmp>; 572 573 qcom,smem-states = <&smp2p_adsp_out 0>; 574 qcom,smem-state-names = "stop"; 575 576 status = "disabled"; 577 578 glink-edge { 579 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 580 IPCC_MPROC_SIGNAL_GLINK_QMP 581 IRQ_TYPE_EDGE_RISING>; 582 mboxes = <&ipcc IPCC_CLIENT_LPASS 583 IPCC_MPROC_SIGNAL_GLINK_QMP>; 584 585 label = "lpass"; 586 qcom,remote-pid = <2>; 587 588 fastrpc { 589 compatible = "qcom,fastrpc"; 590 qcom,glink-channels = "fastrpcglink-apps-dsp"; 591 label = "adsp"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 595 compute-cb@3 { 596 compatible = "qcom,fastrpc-compute-cb"; 597 reg = <3>; 598 iommus = <&apps_smmu 0x1003 0x0>; 599 }; 600 601 compute-cb@4 { 602 compatible = "qcom,fastrpc-compute-cb"; 603 reg = <4>; 604 iommus = <&apps_smmu 0x1004 0x0>; 605 }; 606 607 compute-cb@5 { 608 compatible = "qcom,fastrpc-compute-cb"; 609 reg = <5>; 610 iommus = <&apps_smmu 0x1005 0x0>; 611 qcom,nsessions = <5>; 612 }; 613 }; 614 }; 615 }; 616 617 mpss: remoteproc@4080000 { 618 compatible = "qcom,sm6350-mpss-pas"; 619 reg = <0x0 0x04080000 0x0 0x4040>; 620 621 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 622 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 623 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 624 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 625 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 626 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 627 interrupt-names = "wdog", "fatal", "ready", "handover", 628 "stop-ack", "shutdown-ack"; 629 630 clocks = <&rpmhcc RPMH_CXO_CLK>; 631 clock-names = "xo"; 632 633 power-domains = <&rpmhpd SM6350_CX>, 634 <&rpmhpd SM6350_MSS>; 635 power-domain-names = "cx", "mss"; 636 637 memory-region = <&pil_modem_mem>; 638 639 qcom,qmp = <&aoss_qmp>; 640 641 qcom,smem-states = <&modem_smp2p_out 0>; 642 qcom,smem-state-names = "stop"; 643 644 status = "disabled"; 645 646 glink-edge { 647 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 648 IPCC_MPROC_SIGNAL_GLINK_QMP 649 IRQ_TYPE_EDGE_RISING>; 650 mboxes = <&ipcc IPCC_CLIENT_MPSS 651 IPCC_MPROC_SIGNAL_GLINK_QMP>; 652 label = "modem"; 653 qcom,remote-pid = <1>; 654 }; 655 }; 656 657 cdsp: remoteproc@8300000 { 658 compatible = "qcom,sm6350-cdsp-pas"; 659 reg = <0 0x08300000 0 0x10000>; 660 661 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 662 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 663 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 664 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 665 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 666 interrupt-names = "wdog", "fatal", "ready", 667 "handover", "stop-ack"; 668 669 clocks = <&rpmhcc RPMH_CXO_CLK>; 670 clock-names = "xo"; 671 672 power-domains = <&rpmhpd SM6350_CX>, 673 <&rpmhpd SM6350_MX>; 674 power-domain-names = "cx", "mx"; 675 676 memory-region = <&pil_cdsp_mem>; 677 678 qcom,qmp = <&aoss_qmp>; 679 680 qcom,smem-states = <&smp2p_cdsp_out 0>; 681 qcom,smem-state-names = "stop"; 682 683 status = "disabled"; 684 685 glink-edge { 686 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 687 IPCC_MPROC_SIGNAL_GLINK_QMP 688 IRQ_TYPE_EDGE_RISING>; 689 mboxes = <&ipcc IPCC_CLIENT_CDSP 690 IPCC_MPROC_SIGNAL_GLINK_QMP>; 691 692 label = "cdsp"; 693 qcom,remote-pid = <5>; 694 695 fastrpc { 696 compatible = "qcom,fastrpc"; 697 qcom,glink-channels = "fastrpcglink-apps-dsp"; 698 label = "cdsp"; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 702 compute-cb@1 { 703 compatible = "qcom,fastrpc-compute-cb"; 704 reg = <1>; 705 iommus = <&apps_smmu 0x1401 0x20>; 706 }; 707 708 compute-cb@2 { 709 compatible = "qcom,fastrpc-compute-cb"; 710 reg = <2>; 711 iommus = <&apps_smmu 0x1402 0x20>; 712 }; 713 714 compute-cb@3 { 715 compatible = "qcom,fastrpc-compute-cb"; 716 reg = <3>; 717 iommus = <&apps_smmu 0x1403 0x20>; 718 }; 719 720 compute-cb@4 { 721 compatible = "qcom,fastrpc-compute-cb"; 722 reg = <4>; 723 iommus = <&apps_smmu 0x1404 0x20>; 724 }; 725 726 compute-cb@5 { 727 compatible = "qcom,fastrpc-compute-cb"; 728 reg = <5>; 729 iommus = <&apps_smmu 0x1405 0x20>; 730 }; 731 732 compute-cb@6 { 733 compatible = "qcom,fastrpc-compute-cb"; 734 reg = <6>; 735 iommus = <&apps_smmu 0x1406 0x20>; 736 }; 737 738 compute-cb@7 { 739 compatible = "qcom,fastrpc-compute-cb"; 740 reg = <7>; 741 iommus = <&apps_smmu 0x1407 0x20>; 742 }; 743 744 compute-cb@8 { 745 compatible = "qcom,fastrpc-compute-cb"; 746 reg = <8>; 747 iommus = <&apps_smmu 0x1408 0x20>; 748 }; 749 750 /* note: secure cb9 in downstream */ 751 }; 752 }; 753 }; 754 755 sdhc_2: sdhci@8804000 { 756 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 757 reg = <0 0x08804000 0 0x1000>; 758 759 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "hc_irq", "pwr_irq"; 762 763 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 764 <&gcc GCC_SDCC2_APPS_CLK>, 765 <&rpmhcc RPMH_CXO_CLK>; 766 clock-names = "iface", "core", "xo"; 767 qcom,dll-config = <0x0007642c>; 768 qcom,ddr-config = <0x80040868>; 769 power-domains = <&rpmhpd 0>; 770 operating-points-v2 = <&sdhc2_opp_table>; 771 bus-width = <4>; 772 773 status = "disabled"; 774 775 sdhc2_opp_table: sdhc2-opp-table { 776 compatible = "operating-points-v2"; 777 778 opp-100000000 { 779 opp-hz = /bits/ 64 <100000000>; 780 required-opps = <&rpmhpd_opp_svs_l1>; 781 }; 782 783 opp-202000000 { 784 opp-hz = /bits/ 64 <202000000>; 785 required-opps = <&rpmhpd_opp_nom>; 786 }; 787 }; 788 }; 789 790 usb_1_hsphy: phy@88e3000 { 791 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 792 reg = <0 0x088e3000 0 0x400>; 793 status = "disabled"; 794 #phy-cells = <0>; 795 796 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 797 clock-names = "cfg_ahb", "ref"; 798 799 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 800 }; 801 802 usb_1_qmpphy: phy@88e9000 { 803 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 804 reg = <0 0x088e9000 0 0x200>, 805 <0 0x088e8000 0 0x40>, 806 <0 0x088ea000 0 0x200>; 807 status = "disabled"; 808 #address-cells = <2>; 809 #size-cells = <2>; 810 ranges; 811 812 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 813 <&xo_board>, 814 <&rpmhcc RPMH_QLINK_CLK>, 815 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 816 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 817 818 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 819 <&gcc GCC_USB3_PHY_PRIM_BCR>; 820 reset-names = "phy", "common"; 821 822 usb_1_ssphy: usb3-phy@88e9200 { 823 reg = <0 0x088e9200 0 0x200>, 824 <0 0x088e9400 0 0x200>, 825 <0 0x088e9c00 0 0x400>, 826 <0 0x088e9600 0 0x200>, 827 <0 0x088e9800 0 0x200>, 828 <0 0x088e9a00 0 0x100>; 829 #clock-cells = <0>; 830 #phy-cells = <0>; 831 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 832 clock-names = "pipe0"; 833 clock-output-names = "usb3_phy_pipe_clk_src"; 834 }; 835 836 dp_phy: dp-phy@88ea200 { 837 reg = <0 0x088ea200 0 0x200>, 838 <0 0x088ea400 0 0x200>, 839 <0 0x088eac00 0 0x400>, 840 <0 0x088ea600 0 0x200>, 841 <0 0x088ea800 0 0x200>, 842 <0 0x088eaa00 0 0x100>; 843 #phy-cells = <0>; 844 #clock-cells = <1>; 845 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 846 clock-names = "pipe0"; 847 clock-output-names = "usb3_phy_pipe_clk_src"; 848 }; 849 }; 850 851 system-cache-controller@9200000 { 852 compatible = "qcom,sm6350-llcc"; 853 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 854 reg-names = "llcc_base", "llcc_broadcast_base"; 855 }; 856 857 usb_1: usb@a6f8800 { 858 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 859 reg = <0 0x0a6f8800 0 0x400>; 860 status = "disabled"; 861 #address-cells = <2>; 862 #size-cells = <2>; 863 ranges; 864 865 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 866 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 867 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 868 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 869 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 870 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 871 "sleep"; 872 873 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 874 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 875 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 876 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 877 878 interrupt-names = "hs_phy_irq", "ss_phy_irq", 879 "dm_hs_phy_irq", "dp_hs_phy_irq"; 880 881 power-domains = <&gcc USB30_PRIM_GDSC>; 882 883 resets = <&gcc GCC_USB30_PRIM_BCR>; 884 885 usb_1_dwc3: usb@a600000 { 886 compatible = "snps,dwc3"; 887 reg = <0 0x0a600000 0 0xcd00>; 888 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 889 iommus = <&apps_smmu 0x540 0x0>; 890 snps,dis_u2_susphy_quirk; 891 snps,dis_enblslpm_quirk; 892 snps,has-lpm-erratum; 893 snps,hird-threshold = /bits/ 8 <0x10>; 894 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 895 phy-names = "usb2-phy", "usb3-phy"; 896 }; 897 }; 898 899 pdc: interrupt-controller@b220000 { 900 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 901 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 902 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 903 <125 63 1>, <126 655 12>, <138 139 15>; 904 #interrupt-cells = <2>; 905 interrupt-parent = <&intc>; 906 interrupt-controller; 907 }; 908 909 tsens0: thermal-sensor@c263000 { 910 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 911 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 912 <0 0x0c222000 0 0x8>; /* SROT */ 913 #qcom,sensors = <16>; 914 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 915 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 916 interrupt-names = "uplow", "critical"; 917 #thermal-sensor-cells = <1>; 918 }; 919 920 tsens1: thermal-sensor@c265000 { 921 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 922 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 923 <0 0x0c223000 0 0x8>; /* SROT */ 924 #qcom,sensors = <16>; 925 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 926 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 927 interrupt-names = "uplow", "critical"; 928 #thermal-sensor-cells = <1>; 929 }; 930 931 aoss_qmp: power-controller@c300000 { 932 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 933 reg = <0 0x0c300000 0 0x1000>; 934 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 935 IRQ_TYPE_EDGE_RISING>; 936 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 937 938 #clock-cells = <0>; 939 }; 940 941 spmi_bus: spmi@c440000 { 942 compatible = "qcom,spmi-pmic-arb"; 943 reg = <0 0xc440000 0 0x1100>, 944 <0 0xc600000 0 0x2000000>, 945 <0 0xe600000 0 0x100000>, 946 <0 0xe700000 0 0xa0000>, 947 <0 0xc40a000 0 0x26000>; 948 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 949 interrupt-names = "periph_irq"; 950 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 951 qcom,ee = <0>; 952 qcom,channel = <0>; 953 #address-cells = <2>; 954 #size-cells = <0>; 955 interrupt-controller; 956 #interrupt-cells = <4>; 957 }; 958 959 tlmm: pinctrl@f100000 { 960 compatible = "qcom,sm6350-tlmm"; 961 reg = <0 0x0f100000 0 0x300000>; 962 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 971 gpio-controller; 972 #gpio-cells = <2>; 973 interrupt-controller; 974 #interrupt-cells = <2>; 975 gpio-ranges = <&tlmm 0 0 157>; 976 977 qup_uart2_default: qup-uart2-default { 978 pins = "gpio25", "gpio26"; 979 function = "qup13_f2"; 980 drive-strength = <2>; 981 bias-disable; 982 }; 983 }; 984 985 apps_smmu: iommu@15000000 { 986 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 987 reg = <0 0x15000000 0 0x100000>; 988 #iommu-cells = <2>; 989 #global-interrupts = <1>; 990 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1071 }; 1072 1073 intc: interrupt-controller@17a00000 { 1074 compatible = "arm,gic-v3"; 1075 #interrupt-cells = <3>; 1076 interrupt-controller; 1077 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1078 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1079 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1080 }; 1081 1082 watchdog@17c10000 { 1083 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1084 reg = <0 0x17c10000 0 0x1000>; 1085 clocks = <&sleep_clk>; 1086 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1087 }; 1088 1089 timer@17c20000 { 1090 compatible = "arm,armv7-timer-mem"; 1091 reg = <0x0 0x17c20000 0x0 0x1000>; 1092 clock-frequency = <19200000>; 1093 #address-cells = <2>; 1094 #size-cells = <2>; 1095 ranges; 1096 1097 frame@17c21000 { 1098 frame-number = <0>; 1099 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1101 reg = <0x0 0x17c21000 0x0 0x1000>, 1102 <0x0 0x17c22000 0x0 0x1000>; 1103 }; 1104 1105 frame@17c23000 { 1106 frame-number = <1>; 1107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1108 reg = <0x0 0x17c23000 0x0 0x1000>; 1109 status = "disabled"; 1110 }; 1111 1112 frame@17c25000 { 1113 frame-number = <2>; 1114 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1115 reg = <0x0 0x17c25000 0x0 0x1000>; 1116 status = "disabled"; 1117 }; 1118 1119 frame@17c27000 { 1120 frame-number = <3>; 1121 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1122 reg = <0x0 0x17c27000 0x0 0x1000>; 1123 status = "disabled"; 1124 }; 1125 1126 frame@17c29000 { 1127 frame-number = <4>; 1128 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1129 reg = <0x0 0x17c29000 0x0 0x1000>; 1130 status = "disabled"; 1131 }; 1132 1133 frame@17c2b000 { 1134 frame-number = <5>; 1135 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1136 reg = <0x0 0x17c2b000 0x0 0x1000>; 1137 status = "disabled"; 1138 }; 1139 1140 frame@17c2d000 { 1141 frame-number = <6>; 1142 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1143 reg = <0x0 0x17c2d000 0x0 0x1000>; 1144 status = "disabled"; 1145 }; 1146 }; 1147 1148 apps_rsc: rsc@18200000 { 1149 compatible = "qcom,rpmh-rsc"; 1150 label = "apps_rsc"; 1151 reg = <0x0 0x18200000 0x0 0x10000>, 1152 <0x0 0x18210000 0x0 0x10000>, 1153 <0x0 0x18220000 0x0 0x10000>; 1154 reg-names = "drv-0", "drv-1", "drv-2"; 1155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1158 qcom,tcs-offset = <0xd00>; 1159 qcom,drv-id = <2>; 1160 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1161 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1162 1163 rpmhcc: clock-controller { 1164 compatible = "qcom,sm6350-rpmh-clk"; 1165 #clock-cells = <1>; 1166 clock-names = "xo"; 1167 clocks = <&xo_board>; 1168 }; 1169 1170 rpmhpd: power-controller { 1171 compatible = "qcom,sm6350-rpmhpd"; 1172 #power-domain-cells = <1>; 1173 operating-points-v2 = <&rpmhpd_opp_table>; 1174 1175 rpmhpd_opp_table: opp-table { 1176 compatible = "operating-points-v2"; 1177 1178 rpmhpd_opp_ret: opp1 { 1179 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1180 }; 1181 1182 rpmhpd_opp_min_svs: opp2 { 1183 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1184 }; 1185 1186 rpmhpd_opp_low_svs: opp3 { 1187 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1188 }; 1189 1190 rpmhpd_opp_svs: opp4 { 1191 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1192 }; 1193 1194 rpmhpd_opp_svs_l1: opp5 { 1195 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1196 }; 1197 1198 rpmhpd_opp_nom: opp6 { 1199 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1200 }; 1201 1202 rpmhpd_opp_nom_l1: opp7 { 1203 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1204 }; 1205 1206 rpmhpd_opp_nom_l2: opp8 { 1207 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1208 }; 1209 1210 rpmhpd_opp_turbo: opp9 { 1211 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1212 }; 1213 1214 rpmhpd_opp_turbo_l1: opp10 { 1215 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1216 }; 1217 }; 1218 }; 1219 1220 apps_bcm_voter: bcm_voter { 1221 compatible = "qcom,bcm-voter"; 1222 }; 1223 }; 1224 1225 cpufreq_hw: cpufreq@18323000 { 1226 compatible = "qcom,cpufreq-hw"; 1227 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 1228 reg-names = "freq-domain0", "freq-domain1"; 1229 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1230 clock-names = "xo", "alternate"; 1231 1232 #freq-domain-cells = <1>; 1233 }; 1234 }; 1235 1236 timer { 1237 compatible = "arm,armv8-timer"; 1238 clock-frequency = <19200000>; 1239 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1240 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1241 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1242 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1243 }; 1244}; 1245