1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3M (R8A77970) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77970-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/power/r8a77970-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77970"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 }; 26 27 /* External CAN clock - to be overridden by boards that provide it */ 28 can_clk: can { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 a53_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0>; 42 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 43 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 44 next-level-cache = <&L2_CA53>; 45 enable-method = "psci"; 46 }; 47 48 a53_1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <1>; 52 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 53 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 54 next-level-cache = <&L2_CA53>; 55 enable-method = "psci"; 56 }; 57 58 L2_CA53: cache-controller { 59 compatible = "cache"; 60 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 61 cache-unified; 62 cache-level = <2>; 63 }; 64 }; 65 66 extal_clk: extal { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 /* This value must be overridden by the board */ 70 clock-frequency = <0>; 71 }; 72 73 extalr_clk: extalr { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 /* This value must be overridden by the board */ 77 clock-frequency = <0>; 78 }; 79 80 pmu_a53 { 81 compatible = "arm,cortex-a53-pmu"; 82 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 83 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&a53_0>, <&a53_1>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0", "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 /* External SCIF clock - to be overridden by boards that provide it */ 93 scif_clk: scif { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <0>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 rwdt: watchdog@e6020000 { 108 compatible = "renesas,r8a77970-wdt", 109 "renesas,rcar-gen3-wdt"; 110 reg = <0 0xe6020000 0 0x0c>; 111 clocks = <&cpg CPG_MOD 402>; 112 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 113 resets = <&cpg 402>; 114 status = "disabled"; 115 }; 116 117 gpio0: gpio@e6050000 { 118 compatible = "renesas,gpio-r8a77970", 119 "renesas,rcar-gen3-gpio"; 120 reg = <0 0xe6050000 0 0x50>; 121 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pfc 0 0 22>; 125 #interrupt-cells = <2>; 126 interrupt-controller; 127 clocks = <&cpg CPG_MOD 912>; 128 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 129 resets = <&cpg 912>; 130 }; 131 132 gpio1: gpio@e6051000 { 133 compatible = "renesas,gpio-r8a77970", 134 "renesas,rcar-gen3-gpio"; 135 reg = <0 0xe6051000 0 0x50>; 136 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 137 #gpio-cells = <2>; 138 gpio-controller; 139 gpio-ranges = <&pfc 0 32 28>; 140 #interrupt-cells = <2>; 141 interrupt-controller; 142 clocks = <&cpg CPG_MOD 911>; 143 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 144 resets = <&cpg 911>; 145 }; 146 147 gpio2: gpio@e6052000 { 148 compatible = "renesas,gpio-r8a77970", 149 "renesas,rcar-gen3-gpio"; 150 reg = <0 0xe6052000 0 0x50>; 151 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 64 17>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&cpg CPG_MOD 910>; 158 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 159 resets = <&cpg 910>; 160 }; 161 162 gpio3: gpio@e6053000 { 163 compatible = "renesas,gpio-r8a77970", 164 "renesas,rcar-gen3-gpio"; 165 reg = <0 0xe6053000 0 0x50>; 166 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 gpio-ranges = <&pfc 0 96 17>; 170 #interrupt-cells = <2>; 171 interrupt-controller; 172 clocks = <&cpg CPG_MOD 909>; 173 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 174 resets = <&cpg 909>; 175 }; 176 177 gpio4: gpio@e6054000 { 178 compatible = "renesas,gpio-r8a77970", 179 "renesas,rcar-gen3-gpio"; 180 reg = <0 0xe6054000 0 0x50>; 181 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 182 #gpio-cells = <2>; 183 gpio-controller; 184 gpio-ranges = <&pfc 0 128 6>; 185 #interrupt-cells = <2>; 186 interrupt-controller; 187 clocks = <&cpg CPG_MOD 908>; 188 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 189 resets = <&cpg 908>; 190 }; 191 192 gpio5: gpio@e6055000 { 193 compatible = "renesas,gpio-r8a77970", 194 "renesas,rcar-gen3-gpio"; 195 reg = <0 0xe6055000 0 0x50>; 196 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 197 #gpio-cells = <2>; 198 gpio-controller; 199 gpio-ranges = <&pfc 0 160 15>; 200 #interrupt-cells = <2>; 201 interrupt-controller; 202 clocks = <&cpg CPG_MOD 907>; 203 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 204 resets = <&cpg 907>; 205 }; 206 207 pfc: pin-controller@e6060000 { 208 compatible = "renesas,pfc-r8a77970"; 209 reg = <0 0xe6060000 0 0x504>; 210 }; 211 212 cmt0: timer@e60f0000 { 213 compatible = "renesas,r8a77970-cmt0", 214 "renesas,rcar-gen3-cmt0"; 215 reg = <0 0xe60f0000 0 0x1004>; 216 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cpg CPG_MOD 303>; 219 clock-names = "fck"; 220 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 221 resets = <&cpg 303>; 222 status = "disabled"; 223 }; 224 225 cmt1: timer@e6130000 { 226 compatible = "renesas,r8a77970-cmt1", 227 "renesas,rcar-gen3-cmt1"; 228 reg = <0 0xe6130000 0 0x1004>; 229 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cpg CPG_MOD 302>; 238 clock-names = "fck"; 239 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 240 resets = <&cpg 302>; 241 status = "disabled"; 242 }; 243 244 cmt2: timer@e6140000 { 245 compatible = "renesas,r8a77970-cmt1", 246 "renesas,rcar-gen3-cmt1"; 247 reg = <0 0xe6140000 0 0x1004>; 248 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cpg CPG_MOD 301>; 257 clock-names = "fck"; 258 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 259 resets = <&cpg 301>; 260 status = "disabled"; 261 }; 262 263 cmt3: timer@e6148000 { 264 compatible = "renesas,r8a77970-cmt1", 265 "renesas,rcar-gen3-cmt1"; 266 reg = <0 0xe6148000 0 0x1004>; 267 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&cpg CPG_MOD 300>; 276 clock-names = "fck"; 277 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 278 resets = <&cpg 300>; 279 status = "disabled"; 280 }; 281 282 cpg: clock-controller@e6150000 { 283 compatible = "renesas,r8a77970-cpg-mssr"; 284 reg = <0 0xe6150000 0 0x1000>; 285 clocks = <&extal_clk>, <&extalr_clk>; 286 clock-names = "extal", "extalr"; 287 #clock-cells = <2>; 288 #power-domain-cells = <0>; 289 #reset-cells = <1>; 290 }; 291 292 rst: reset-controller@e6160000 { 293 compatible = "renesas,r8a77970-rst"; 294 reg = <0 0xe6160000 0 0x200>; 295 }; 296 297 sysc: system-controller@e6180000 { 298 compatible = "renesas,r8a77970-sysc"; 299 reg = <0 0xe6180000 0 0x440>; 300 #power-domain-cells = <1>; 301 }; 302 303 thermal: thermal@e6190000 { 304 compatible = "renesas,thermal-r8a77970"; 305 reg = <0 0xe6190000 0 0x10>, 306 <0 0xe6190100 0 0x120>; 307 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&cpg CPG_MOD 522>; 311 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 312 resets = <&cpg 522>; 313 #thermal-sensor-cells = <0>; 314 }; 315 316 intc_ex: interrupt-controller@e61c0000 { 317 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 318 #interrupt-cells = <2>; 319 interrupt-controller; 320 reg = <0 0xe61c0000 0 0x200>; 321 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&cpg CPG_MOD 407>; 328 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 329 resets = <&cpg 407>; 330 }; 331 332 tmu0: timer@e61e0000 { 333 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 334 reg = <0 0xe61e0000 0 0x30>; 335 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cpg CPG_MOD 125>; 339 clock-names = "fck"; 340 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 341 resets = <&cpg 125>; 342 status = "disabled"; 343 }; 344 345 tmu1: timer@e6fc0000 { 346 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 347 reg = <0 0xe6fc0000 0 0x30>; 348 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cpg CPG_MOD 124>; 352 clock-names = "fck"; 353 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 354 resets = <&cpg 124>; 355 status = "disabled"; 356 }; 357 358 tmu2: timer@e6fd0000 { 359 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 360 reg = <0 0xe6fd0000 0 0x30>; 361 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cpg CPG_MOD 123>; 365 clock-names = "fck"; 366 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 367 resets = <&cpg 123>; 368 status = "disabled"; 369 }; 370 371 tmu3: timer@e6fe0000 { 372 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 373 reg = <0 0xe6fe0000 0 0x30>; 374 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&cpg CPG_MOD 122>; 378 clock-names = "fck"; 379 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 380 resets = <&cpg 122>; 381 status = "disabled"; 382 }; 383 384 tmu4: timer@ffc00000 { 385 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 386 reg = <0 0xffc00000 0 0x30>; 387 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 121>; 391 clock-names = "fck"; 392 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 393 resets = <&cpg 121>; 394 status = "disabled"; 395 }; 396 397 i2c0: i2c@e6500000 { 398 compatible = "renesas,i2c-r8a77970", 399 "renesas,rcar-gen3-i2c"; 400 reg = <0 0xe6500000 0 0x40>; 401 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&cpg CPG_MOD 931>; 403 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 404 resets = <&cpg 931>; 405 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 406 <&dmac2 0x91>, <&dmac2 0x90>; 407 dma-names = "tx", "rx", "tx", "rx"; 408 i2c-scl-internal-delay-ns = <6>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c1: i2c@e6508000 { 415 compatible = "renesas,i2c-r8a77970", 416 "renesas,rcar-gen3-i2c"; 417 reg = <0 0xe6508000 0 0x40>; 418 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&cpg CPG_MOD 930>; 420 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 421 resets = <&cpg 930>; 422 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 423 <&dmac2 0x93>, <&dmac2 0x92>; 424 dma-names = "tx", "rx", "tx", "rx"; 425 i2c-scl-internal-delay-ns = <6>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c2: i2c@e6510000 { 432 compatible = "renesas,i2c-r8a77970", 433 "renesas,rcar-gen3-i2c"; 434 reg = <0 0xe6510000 0 0x40>; 435 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&cpg CPG_MOD 929>; 437 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 438 resets = <&cpg 929>; 439 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 440 <&dmac2 0x95>, <&dmac2 0x94>; 441 dma-names = "tx", "rx", "tx", "rx"; 442 i2c-scl-internal-delay-ns = <6>; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 i2c3: i2c@e66d0000 { 449 compatible = "renesas,i2c-r8a77970", 450 "renesas,rcar-gen3-i2c"; 451 reg = <0 0xe66d0000 0 0x40>; 452 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cpg CPG_MOD 928>; 454 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 455 resets = <&cpg 928>; 456 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 457 <&dmac2 0x97>, <&dmac2 0x96>; 458 dma-names = "tx", "rx", "tx", "rx"; 459 i2c-scl-internal-delay-ns = <6>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 status = "disabled"; 463 }; 464 465 i2c4: i2c@e66d8000 { 466 compatible = "renesas,i2c-r8a77970", 467 "renesas,rcar-gen3-i2c"; 468 reg = <0 0xe66d8000 0 0x40>; 469 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&cpg CPG_MOD 927>; 471 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 472 resets = <&cpg 927>; 473 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 474 <&dmac2 0x99>, <&dmac2 0x98>; 475 dma-names = "tx", "rx", "tx", "rx"; 476 i2c-scl-internal-delay-ns = <6>; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 status = "disabled"; 480 }; 481 482 hscif0: serial@e6540000 { 483 compatible = "renesas,hscif-r8a77970", 484 "renesas,rcar-gen3-hscif", 485 "renesas,hscif"; 486 reg = <0 0xe6540000 0 96>; 487 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cpg CPG_MOD 520>, 489 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 490 <&scif_clk>; 491 clock-names = "fck", "brg_int", "scif_clk"; 492 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 493 <&dmac2 0x31>, <&dmac2 0x30>; 494 dma-names = "tx", "rx", "tx", "rx"; 495 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 496 resets = <&cpg 520>; 497 status = "disabled"; 498 }; 499 500 hscif1: serial@e6550000 { 501 compatible = "renesas,hscif-r8a77970", 502 "renesas,rcar-gen3-hscif", 503 "renesas,hscif"; 504 reg = <0 0xe6550000 0 96>; 505 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&cpg CPG_MOD 519>, 507 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 508 <&scif_clk>; 509 clock-names = "fck", "brg_int", "scif_clk"; 510 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 511 <&dmac2 0x33>, <&dmac2 0x32>; 512 dma-names = "tx", "rx", "tx", "rx"; 513 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 514 resets = <&cpg 519>; 515 status = "disabled"; 516 }; 517 518 hscif2: serial@e6560000 { 519 compatible = "renesas,hscif-r8a77970", 520 "renesas,rcar-gen3-hscif", 521 "renesas,hscif"; 522 reg = <0 0xe6560000 0 96>; 523 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&cpg CPG_MOD 518>, 525 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 526 <&scif_clk>; 527 clock-names = "fck", "brg_int", "scif_clk"; 528 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 529 <&dmac2 0x35>, <&dmac2 0x34>; 530 dma-names = "tx", "rx", "tx", "rx"; 531 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 532 resets = <&cpg 518>; 533 status = "disabled"; 534 }; 535 536 hscif3: serial@e66a0000 { 537 compatible = "renesas,hscif-r8a77970", 538 "renesas,rcar-gen3-hscif", "renesas,hscif"; 539 reg = <0 0xe66a0000 0 96>; 540 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cpg CPG_MOD 517>, 542 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 543 <&scif_clk>; 544 clock-names = "fck", "brg_int", "scif_clk"; 545 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 546 <&dmac2 0x37>, <&dmac2 0x36>; 547 dma-names = "tx", "rx", "tx", "rx"; 548 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 549 resets = <&cpg 517>; 550 status = "disabled"; 551 }; 552 553 canfd: can@e66c0000 { 554 compatible = "renesas,r8a77970-canfd", 555 "renesas,rcar-gen3-canfd"; 556 reg = <0 0xe66c0000 0 0x8000>; 557 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cpg CPG_MOD 914>, 560 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 561 <&can_clk>; 562 clock-names = "fck", "canfd", "can_clk"; 563 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 564 assigned-clock-rates = <40000000>; 565 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 566 resets = <&cpg 914>; 567 status = "disabled"; 568 569 channel0 { 570 status = "disabled"; 571 }; 572 573 channel1 { 574 status = "disabled"; 575 }; 576 }; 577 578 avb: ethernet@e6800000 { 579 compatible = "renesas,etheravb-r8a77970", 580 "renesas,etheravb-rcar-gen3"; 581 reg = <0 0xe6800000 0 0x800>; 582 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "ch0", "ch1", "ch2", "ch3", 608 "ch4", "ch5", "ch6", "ch7", 609 "ch8", "ch9", "ch10", "ch11", 610 "ch12", "ch13", "ch14", "ch15", 611 "ch16", "ch17", "ch18", "ch19", 612 "ch20", "ch21", "ch22", "ch23", 613 "ch24"; 614 clocks = <&cpg CPG_MOD 812>; 615 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 616 resets = <&cpg 812>; 617 phy-mode = "rgmii"; 618 iommus = <&ipmmu_rt 3>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 624 pwm0: pwm@e6e30000 { 625 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 626 reg = <0 0xe6e30000 0 8>; 627 #pwm-cells = <2>; 628 clocks = <&cpg CPG_MOD 523>; 629 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 630 resets = <&cpg 523>; 631 status = "disabled"; 632 }; 633 634 pwm1: pwm@e6e31000 { 635 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 636 reg = <0 0xe6e31000 0 8>; 637 #pwm-cells = <2>; 638 clocks = <&cpg CPG_MOD 523>; 639 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 640 resets = <&cpg 523>; 641 status = "disabled"; 642 }; 643 644 pwm2: pwm@e6e32000 { 645 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 646 reg = <0 0xe6e32000 0 8>; 647 #pwm-cells = <2>; 648 clocks = <&cpg CPG_MOD 523>; 649 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 650 resets = <&cpg 523>; 651 status = "disabled"; 652 }; 653 654 pwm3: pwm@e6e33000 { 655 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 656 reg = <0 0xe6e33000 0 8>; 657 #pwm-cells = <2>; 658 clocks = <&cpg CPG_MOD 523>; 659 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 660 resets = <&cpg 523>; 661 status = "disabled"; 662 }; 663 664 pwm4: pwm@e6e34000 { 665 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 666 reg = <0 0xe6e34000 0 8>; 667 #pwm-cells = <2>; 668 clocks = <&cpg CPG_MOD 523>; 669 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 670 resets = <&cpg 523>; 671 status = "disabled"; 672 }; 673 674 scif0: serial@e6e60000 { 675 compatible = "renesas,scif-r8a77970", 676 "renesas,rcar-gen3-scif", 677 "renesas,scif"; 678 reg = <0 0xe6e60000 0 64>; 679 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cpg CPG_MOD 207>, 681 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 682 <&scif_clk>; 683 clock-names = "fck", "brg_int", "scif_clk"; 684 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 685 <&dmac2 0x51>, <&dmac2 0x50>; 686 dma-names = "tx", "rx", "tx", "rx"; 687 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 688 resets = <&cpg 207>; 689 status = "disabled"; 690 }; 691 692 scif1: serial@e6e68000 { 693 compatible = "renesas,scif-r8a77970", 694 "renesas,rcar-gen3-scif", 695 "renesas,scif"; 696 reg = <0 0xe6e68000 0 64>; 697 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&cpg CPG_MOD 206>, 699 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 700 <&scif_clk>; 701 clock-names = "fck", "brg_int", "scif_clk"; 702 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 703 <&dmac2 0x53>, <&dmac2 0x52>; 704 dma-names = "tx", "rx", "tx", "rx"; 705 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 706 resets = <&cpg 206>; 707 status = "disabled"; 708 }; 709 710 scif3: serial@e6c50000 { 711 compatible = "renesas,scif-r8a77970", 712 "renesas,rcar-gen3-scif", 713 "renesas,scif"; 714 reg = <0 0xe6c50000 0 64>; 715 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cpg CPG_MOD 204>, 717 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 718 <&scif_clk>; 719 clock-names = "fck", "brg_int", "scif_clk"; 720 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 721 <&dmac2 0x57>, <&dmac2 0x56>; 722 dma-names = "tx", "rx", "tx", "rx"; 723 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 724 resets = <&cpg 204>; 725 status = "disabled"; 726 }; 727 728 scif4: serial@e6c40000 { 729 compatible = "renesas,scif-r8a77970", 730 "renesas,rcar-gen3-scif", "renesas,scif"; 731 reg = <0 0xe6c40000 0 64>; 732 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&cpg CPG_MOD 203>, 734 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 735 <&scif_clk>; 736 clock-names = "fck", "brg_int", "scif_clk"; 737 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 738 <&dmac2 0x59>, <&dmac2 0x58>; 739 dma-names = "tx", "rx", "tx", "rx"; 740 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 741 resets = <&cpg 203>; 742 status = "disabled"; 743 }; 744 745 tpu: pwm@e6e80000 { 746 compatible = "renesas,tpu-r8a77970", "renesas,tpu"; 747 reg = <0 0xe6e80000 0 0x148>; 748 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cpg CPG_MOD 304>; 750 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 751 resets = <&cpg 304>; 752 #pwm-cells = <3>; 753 status = "disabled"; 754 }; 755 756 msiof0: spi@e6e90000 { 757 compatible = "renesas,msiof-r8a77970", 758 "renesas,rcar-gen3-msiof"; 759 reg = <0 0xe6e90000 0 0x64>; 760 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cpg CPG_MOD 211>; 762 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 763 resets = <&cpg 211>; 764 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 765 <&dmac2 0x41>, <&dmac2 0x40>; 766 dma-names = "tx", "rx", "tx", "rx"; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 status = "disabled"; 770 }; 771 772 msiof1: spi@e6ea0000 { 773 compatible = "renesas,msiof-r8a77970", 774 "renesas,rcar-gen3-msiof"; 775 reg = <0 0xe6ea0000 0 0x0064>; 776 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 777 clocks = <&cpg CPG_MOD 210>; 778 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 779 resets = <&cpg 210>; 780 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 781 <&dmac2 0x43>, <&dmac2 0x42>; 782 dma-names = "tx", "rx", "tx", "rx"; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 status = "disabled"; 786 }; 787 788 msiof2: spi@e6c00000 { 789 compatible = "renesas,msiof-r8a77970", 790 "renesas,rcar-gen3-msiof"; 791 reg = <0 0xe6c00000 0 0x0064>; 792 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&cpg CPG_MOD 209>; 794 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 795 resets = <&cpg 209>; 796 dmas = <&dmac1 0x45>, <&dmac1 0x44>, 797 <&dmac2 0x45>, <&dmac2 0x44>; 798 dma-names = "tx", "rx", "tx", "rx"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 status = "disabled"; 802 }; 803 804 msiof3: spi@e6c10000 { 805 compatible = "renesas,msiof-r8a77970", 806 "renesas,rcar-gen3-msiof"; 807 reg = <0 0xe6c10000 0 0x0064>; 808 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cpg CPG_MOD 208>; 810 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 811 resets = <&cpg 208>; 812 dmas = <&dmac1 0x47>, <&dmac1 0x46>, 813 <&dmac2 0x47>, <&dmac2 0x46>; 814 dma-names = "tx", "rx", "tx", "rx"; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 status = "disabled"; 818 }; 819 820 vin0: video@e6ef0000 { 821 compatible = "renesas,vin-r8a77970"; 822 reg = <0 0xe6ef0000 0 0x1000>; 823 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 811>; 825 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 826 resets = <&cpg 811>; 827 renesas,id = <0>; 828 status = "disabled"; 829 830 ports { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 834 port@1 { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 838 reg = <1>; 839 840 vin0csi40: endpoint@2 { 841 reg = <2>; 842 remote-endpoint = <&csi40vin0>; 843 }; 844 }; 845 }; 846 }; 847 848 vin1: video@e6ef1000 { 849 compatible = "renesas,vin-r8a77970"; 850 reg = <0 0xe6ef1000 0 0x1000>; 851 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&cpg CPG_MOD 810>; 853 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 854 resets = <&cpg 810>; 855 renesas,id = <1>; 856 status = "disabled"; 857 858 ports { 859 #address-cells = <1>; 860 #size-cells = <0>; 861 862 port@1 { 863 #address-cells = <1>; 864 #size-cells = <0>; 865 866 reg = <1>; 867 868 vin1csi40: endpoint@2 { 869 reg = <2>; 870 remote-endpoint = <&csi40vin1>; 871 }; 872 }; 873 }; 874 }; 875 876 vin2: video@e6ef2000 { 877 compatible = "renesas,vin-r8a77970"; 878 reg = <0 0xe6ef2000 0 0x1000>; 879 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cpg CPG_MOD 809>; 881 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 882 resets = <&cpg 809>; 883 renesas,id = <2>; 884 status = "disabled"; 885 886 ports { 887 #address-cells = <1>; 888 #size-cells = <0>; 889 890 port@1 { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 894 reg = <1>; 895 896 vin2csi40: endpoint@2 { 897 reg = <2>; 898 remote-endpoint = <&csi40vin2>; 899 }; 900 }; 901 }; 902 }; 903 904 vin3: video@e6ef3000 { 905 compatible = "renesas,vin-r8a77970"; 906 reg = <0 0xe6ef3000 0 0x1000>; 907 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&cpg CPG_MOD 808>; 909 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 910 resets = <&cpg 808>; 911 renesas,id = <3>; 912 status = "disabled"; 913 914 ports { 915 #address-cells = <1>; 916 #size-cells = <0>; 917 918 port@1 { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 reg = <1>; 923 924 vin3csi40: endpoint@2 { 925 reg = <2>; 926 remote-endpoint = <&csi40vin3>; 927 }; 928 }; 929 }; 930 }; 931 932 dmac1: dma-controller@e7300000 { 933 compatible = "renesas,dmac-r8a77970", 934 "renesas,rcar-dmac"; 935 reg = <0 0xe7300000 0 0x10000>; 936 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 945 interrupt-names = "error", 946 "ch0", "ch1", "ch2", "ch3", 947 "ch4", "ch5", "ch6", "ch7"; 948 clocks = <&cpg CPG_MOD 218>; 949 clock-names = "fck"; 950 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 951 resets = <&cpg 218>; 952 #dma-cells = <1>; 953 dma-channels = <8>; 954 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 955 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 956 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 957 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 958 }; 959 960 dmac2: dma-controller@e7310000 { 961 compatible = "renesas,dmac-r8a77970", 962 "renesas,rcar-dmac"; 963 reg = <0 0xe7310000 0 0x10000>; 964 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 973 interrupt-names = "error", 974 "ch0", "ch1", "ch2", "ch3", 975 "ch4", "ch5", "ch6", "ch7"; 976 clocks = <&cpg CPG_MOD 217>; 977 clock-names = "fck"; 978 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 979 resets = <&cpg 217>; 980 #dma-cells = <1>; 981 dma-channels = <8>; 982 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 983 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 984 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 985 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 986 }; 987 988 ipmmu_ds1: mmu@e7740000 { 989 compatible = "renesas,ipmmu-r8a77970"; 990 reg = <0 0xe7740000 0 0x1000>; 991 renesas,ipmmu-main = <&ipmmu_mm 0>; 992 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 993 #iommu-cells = <1>; 994 }; 995 996 ipmmu_ir: mmu@ff8b0000 { 997 compatible = "renesas,ipmmu-r8a77970"; 998 reg = <0 0xff8b0000 0 0x1000>; 999 renesas,ipmmu-main = <&ipmmu_mm 3>; 1000 power-domains = <&sysc R8A77970_PD_A3IR>; 1001 #iommu-cells = <1>; 1002 }; 1003 1004 ipmmu_mm: mmu@e67b0000 { 1005 compatible = "renesas,ipmmu-r8a77970"; 1006 reg = <0 0xe67b0000 0 0x1000>; 1007 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1009 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1010 #iommu-cells = <1>; 1011 }; 1012 1013 ipmmu_rt: mmu@ffc80000 { 1014 compatible = "renesas,ipmmu-r8a77970"; 1015 reg = <0 0xffc80000 0 0x1000>; 1016 renesas,ipmmu-main = <&ipmmu_mm 7>; 1017 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1018 #iommu-cells = <1>; 1019 }; 1020 1021 ipmmu_vi0: mmu@febd0000 { 1022 compatible = "renesas,ipmmu-r8a77970"; 1023 reg = <0 0xfebd0000 0 0x1000>; 1024 renesas,ipmmu-main = <&ipmmu_mm 9>; 1025 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1026 #iommu-cells = <1>; 1027 }; 1028 1029 mmc0: mmc@ee140000 { 1030 compatible = "renesas,sdhi-r8a77970", 1031 "renesas,rcar-gen3-sdhi"; 1032 reg = <0 0xee140000 0 0x2000>; 1033 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cpg CPG_MOD 314>; 1035 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1036 resets = <&cpg 314>; 1037 max-frequency = <200000000>; 1038 iommus = <&ipmmu_ds1 32>; 1039 status = "disabled"; 1040 }; 1041 1042 gic: interrupt-controller@f1010000 { 1043 compatible = "arm,gic-400"; 1044 #interrupt-cells = <3>; 1045 #address-cells = <0>; 1046 interrupt-controller; 1047 reg = <0 0xf1010000 0 0x1000>, 1048 <0 0xf1020000 0 0x20000>, 1049 <0 0xf1040000 0 0x20000>, 1050 <0 0xf1060000 0 0x20000>; 1051 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 1052 IRQ_TYPE_LEVEL_HIGH)>; 1053 clocks = <&cpg CPG_MOD 408>; 1054 clock-names = "clk"; 1055 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1056 resets = <&cpg 408>; 1057 }; 1058 1059 vspd0: vsp@fea20000 { 1060 compatible = "renesas,vsp2"; 1061 reg = <0 0xfea20000 0 0x5000>; 1062 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&cpg CPG_MOD 623>; 1064 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1065 resets = <&cpg 623>; 1066 renesas,fcp = <&fcpvd0>; 1067 }; 1068 1069 fcpvd0: fcp@fea27000 { 1070 compatible = "renesas,fcpv"; 1071 reg = <0 0xfea27000 0 0x200>; 1072 clocks = <&cpg CPG_MOD 603>; 1073 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1074 resets = <&cpg 603>; 1075 }; 1076 1077 csi40: csi2@feaa0000 { 1078 compatible = "renesas,r8a77970-csi2"; 1079 reg = <0 0xfeaa0000 0 0x10000>; 1080 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&cpg CPG_MOD 716>; 1082 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1083 resets = <&cpg 716>; 1084 status = "disabled"; 1085 1086 ports { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 port@1 { 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 1094 reg = <1>; 1095 1096 csi40vin0: endpoint@0 { 1097 reg = <0>; 1098 remote-endpoint = <&vin0csi40>; 1099 }; 1100 csi40vin1: endpoint@1 { 1101 reg = <1>; 1102 remote-endpoint = <&vin1csi40>; 1103 }; 1104 csi40vin2: endpoint@2 { 1105 reg = <2>; 1106 remote-endpoint = <&vin2csi40>; 1107 }; 1108 csi40vin3: endpoint@3 { 1109 reg = <3>; 1110 remote-endpoint = <&vin3csi40>; 1111 }; 1112 }; 1113 }; 1114 }; 1115 1116 du: display@feb00000 { 1117 compatible = "renesas,du-r8a77970"; 1118 reg = <0 0xfeb00000 0 0x80000>; 1119 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&cpg CPG_MOD 724>; 1121 clock-names = "du.0"; 1122 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1123 resets = <&cpg 724>; 1124 vsps = <&vspd0 0>; 1125 status = "disabled"; 1126 1127 ports { 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 1131 port@0 { 1132 reg = <0>; 1133 du_out_rgb: endpoint { 1134 }; 1135 }; 1136 1137 port@1 { 1138 reg = <1>; 1139 du_out_lvds0: endpoint { 1140 remote-endpoint = <&lvds0_in>; 1141 }; 1142 }; 1143 }; 1144 }; 1145 1146 lvds0: lvds-encoder@feb90000 { 1147 compatible = "renesas,r8a77970-lvds"; 1148 reg = <0 0xfeb90000 0 0x14>; 1149 clocks = <&cpg CPG_MOD 727>; 1150 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1151 resets = <&cpg 727>; 1152 status = "disabled"; 1153 1154 ports { 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 1158 port@0 { 1159 reg = <0>; 1160 lvds0_in: endpoint { 1161 remote-endpoint = 1162 <&du_out_lvds0>; 1163 }; 1164 }; 1165 port@1 { 1166 reg = <1>; 1167 lvds0_out: endpoint { 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 prr: chipid@fff00044 { 1174 compatible = "renesas,prr"; 1175 reg = <0 0xfff00044 0 4>; 1176 }; 1177 }; 1178 1179 thermal-zones { 1180 cpu-thermal { 1181 polling-delay-passive = <250>; 1182 polling-delay = <1000>; 1183 thermal-sensors = <&thermal>; 1184 1185 cooling-maps { 1186 }; 1187 1188 trips { 1189 cpu-crit { 1190 temperature = <120000>; 1191 hysteresis = <2000>; 1192 type = "critical"; 1193 }; 1194 }; 1195 }; 1196 }; 1197 1198 timer { 1199 compatible = "arm,armv8-timer"; 1200 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1201 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1202 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1203 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1204 }; 1205}; 1206