1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Condor board
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
7 */
8
9/dts-v1/;
10#include "r8a77980.dtsi"
11
12/ {
13	model = "Renesas Condor board based on r8a77980";
14	compatible = "renesas,condor", "renesas,r8a77980";
15
16	aliases {
17		serial0 = &scif0;
18		ethernet0 = &gether;
19	};
20
21	chosen {
22		stdout-path = "serial0:115200n8";
23	};
24
25	memory@48000000 {
26		device_type = "memory";
27		/* first 128MB is reserved for secure area. */
28		reg = <0 0x48000000 0 0x78000000>;
29	};
30
31	d3_3v: regulator-0 {
32		compatible = "regulator-fixed";
33		regulator-name = "D3.3V";
34		regulator-min-microvolt = <3300000>;
35		regulator-max-microvolt = <3300000>;
36		regulator-boot-on;
37		regulator-always-on;
38	};
39
40	vddq_vin01: regulator-1 {
41		compatible = "regulator-fixed";
42		regulator-name = "VDDQ_VIN01";
43		regulator-min-microvolt = <1800000>;
44		regulator-max-microvolt = <1800000>;
45		regulator-boot-on;
46		regulator-always-on;
47	};
48
49	d1_8v: regulator-2 {
50		compatible = "regulator-fixed";
51		regulator-name = "D1.8V";
52		regulator-min-microvolt = <1800000>;
53		regulator-max-microvolt = <1800000>;
54		regulator-boot-on;
55		regulator-always-on;
56	};
57
58	hdmi-out {
59		compatible = "hdmi-connector";
60		type = "a";
61
62		port {
63			hdmi_con: endpoint {
64				remote-endpoint = <&adv7511_out>;
65			};
66		};
67	};
68
69	lvds-decoder {
70		compatible = "thine,thc63lvd1024";
71		vcc-supply = <&d3_3v>;
72
73		ports {
74			#address-cells = <1>;
75			#size-cells = <0>;
76
77			port@0 {
78				reg = <0>;
79				thc63lvd1024_in: endpoint {
80					remote-endpoint = <&lvds0_out>;
81				};
82			};
83
84			port@2 {
85				reg = <2>;
86				thc63lvd1024_out: endpoint {
87					remote-endpoint = <&adv7511_in>;
88				};
89			};
90		};
91	};
92
93	x1_clk: x1-clock {
94		compatible = "fixed-clock";
95		#clock-cells = <0>;
96		clock-frequency = <148500000>;
97	};
98};
99
100&canfd {
101	pinctrl-0 = <&canfd0_pins>;
102	pinctrl-names = "default";
103	status = "okay";
104
105	channel0 {
106		status = "okay";
107	};
108};
109
110&du {
111	clocks = <&cpg CPG_MOD 724>,
112		 <&x1_clk>;
113	clock-names = "du.0", "dclkin.0";
114	status = "okay";
115};
116
117&extal_clk {
118	clock-frequency = <16666666>;
119};
120
121&extalr_clk {
122	clock-frequency = <32768>;
123};
124
125&gether {
126	pinctrl-0 = <&gether_pins>;
127	pinctrl-names = "default";
128
129	phy-mode = "rgmii-id";
130	phy-handle = <&phy0>;
131	renesas,no-ether-link;
132	status = "okay";
133
134	phy0: ethernet-phy@0 {
135		rxc-skew-ps = <1500>;
136		reg = <0>;
137		interrupt-parent = <&gpio4>;
138		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
139	};
140};
141
142&i2c0 {
143	pinctrl-0 = <&i2c0_pins>;
144	pinctrl-names = "default";
145
146	status = "okay";
147	clock-frequency = <400000>;
148
149	io_expander0: gpio@20 {
150		compatible = "onnn,pca9654";
151		reg = <0x20>;
152		gpio-controller;
153		#gpio-cells = <2>;
154	};
155
156	io_expander1: gpio@21 {
157		compatible = "onnn,pca9654";
158		reg = <0x21>;
159		gpio-controller;
160		#gpio-cells = <2>;
161	};
162
163	hdmi@39 {
164		compatible = "adi,adv7511w";
165		reg = <0x39>;
166		interrupt-parent = <&gpio1>;
167		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
168		avdd-supply = <&d1_8v>;
169		dvdd-supply = <&d1_8v>;
170		pvdd-supply = <&d1_8v>;
171		bgvdd-supply = <&d1_8v>;
172		dvdd-3v-supply = <&d3_3v>;
173
174		adi,input-depth = <8>;
175		adi,input-colorspace = "rgb";
176		adi,input-clock = "1x";
177		adi,input-style = <1>;
178		adi,input-justification = "evenly";
179
180		ports {
181			#address-cells = <1>;
182			#size-cells = <0>;
183
184			port@0 {
185				reg = <0>;
186				adv7511_in: endpoint {
187					remote-endpoint = <&thc63lvd1024_out>;
188				};
189			};
190
191			port@1 {
192				reg = <1>;
193				adv7511_out: endpoint {
194					remote-endpoint = <&hdmi_con>;
195				};
196			};
197		};
198	};
199};
200
201&lvds0 {
202	status = "okay";
203
204	ports {
205		port@1 {
206			lvds0_out: endpoint {
207				remote-endpoint = <&thc63lvd1024_in>;
208			};
209		};
210	};
211};
212
213&mmc0 {
214	pinctrl-0 = <&mmc_pins>;
215	pinctrl-1 = <&mmc_pins_uhs>;
216	pinctrl-names = "default", "state_uhs";
217
218	vmmc-supply = <&d3_3v>;
219	vqmmc-supply = <&vddq_vin01>;
220	mmc-hs200-1_8v;
221	bus-width = <8>;
222	non-removable;
223	status = "okay";
224};
225
226&pciec {
227	status = "okay";
228};
229
230&pcie_bus_clk {
231	clock-frequency = <100000000>;
232};
233
234&pcie_phy {
235	status = "okay";
236};
237
238&pfc {
239	canfd0_pins: canfd0 {
240		groups = "canfd0_data_a";
241		function = "canfd0";
242	};
243
244	gether_pins: gether {
245		groups = "gether_mdio_a", "gether_rgmii",
246			 "gether_txcrefclk", "gether_txcrefclk_mega";
247		function = "gether";
248	};
249
250	i2c0_pins: i2c0 {
251		groups = "i2c0";
252		function = "i2c0";
253	};
254
255	mmc_pins: mmc {
256		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
257		function = "mmc";
258		power-source = <3300>;
259	};
260
261	mmc_pins_uhs: mmc_uhs {
262		groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
263		function = "mmc";
264		power-source = <1800>;
265	};
266
267	scif0_pins: scif0 {
268		groups = "scif0_data";
269		function = "scif0";
270	};
271
272	scif_clk_pins: scif_clk {
273		groups = "scif_clk_b";
274		function = "scif_clk";
275	};
276};
277
278&rwdt {
279	timeout-sec = <60>;
280	status = "okay";
281};
282
283&scif0 {
284	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
285	pinctrl-names = "default";
286
287	status = "okay";
288};
289
290&scif_clk {
291	clock-frequency = <14745600>;
292};
293