1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: opp-table-0 { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 }; 214 }; 215 216 gpu_thermal: gpu-thermal { 217 polling-delay-passive = <100>; /* milliseconds */ 218 polling-delay = <1000>; /* milliseconds */ 219 thermal-sensors = <&tsadc 1>; 220 221 trips { 222 gpu_threshold: gpu-threshold { 223 temperature = <70000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 gpu_target: gpu-target { 229 temperature = <85000>; 230 hysteresis = <2000>; 231 type = "passive"; 232 }; 233 234 gpu_crit: gpu-crit { 235 temperature = <115000>; 236 hysteresis = <2000>; 237 type = "critical"; 238 }; 239 }; 240 241 cooling-maps { 242 map0 { 243 trip = <&gpu_target>; 244 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 245 }; 246 }; 247 }; 248 }; 249 250 xin24m: xin24m { 251 compatible = "fixed-clock"; 252 #clock-cells = <0>; 253 clock-frequency = <24000000>; 254 clock-output-names = "xin24m"; 255 }; 256 257 pmu: power-management@ff000000 { 258 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 259 reg = <0x0 0xff000000 0x0 0x1000>; 260 261 power: power-controller { 262 compatible = "rockchip,px30-power-controller"; 263 #power-domain-cells = <1>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 267 /* These power domains are grouped by VD_LOGIC */ 268 power-domain@PX30_PD_USB { 269 reg = <PX30_PD_USB>; 270 clocks = <&cru HCLK_HOST>, 271 <&cru HCLK_OTG>, 272 <&cru SCLK_OTG_ADP>; 273 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 274 #power-domain-cells = <0>; 275 }; 276 power-domain@PX30_PD_SDCARD { 277 reg = <PX30_PD_SDCARD>; 278 clocks = <&cru HCLK_SDMMC>, 279 <&cru SCLK_SDMMC>; 280 pm_qos = <&qos_sdmmc>; 281 #power-domain-cells = <0>; 282 }; 283 power-domain@PX30_PD_GMAC { 284 reg = <PX30_PD_GMAC>; 285 clocks = <&cru ACLK_GMAC>, 286 <&cru PCLK_GMAC>, 287 <&cru SCLK_MAC_REF>, 288 <&cru SCLK_GMAC_RX_TX>; 289 pm_qos = <&qos_gmac>; 290 #power-domain-cells = <0>; 291 }; 292 power-domain@PX30_PD_MMC_NAND { 293 reg = <PX30_PD_MMC_NAND>; 294 clocks = <&cru HCLK_NANDC>, 295 <&cru HCLK_EMMC>, 296 <&cru HCLK_SDIO>, 297 <&cru HCLK_SFC>, 298 <&cru SCLK_EMMC>, 299 <&cru SCLK_NANDC>, 300 <&cru SCLK_SDIO>, 301 <&cru SCLK_SFC>; 302 pm_qos = <&qos_emmc>, <&qos_nand>, 303 <&qos_sdio>, <&qos_sfc>; 304 #power-domain-cells = <0>; 305 }; 306 power-domain@PX30_PD_VPU { 307 reg = <PX30_PD_VPU>; 308 clocks = <&cru ACLK_VPU>, 309 <&cru HCLK_VPU>, 310 <&cru SCLK_CORE_VPU>; 311 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 312 #power-domain-cells = <0>; 313 }; 314 power-domain@PX30_PD_VO { 315 reg = <PX30_PD_VO>; 316 clocks = <&cru ACLK_RGA>, 317 <&cru ACLK_VOPB>, 318 <&cru ACLK_VOPL>, 319 <&cru DCLK_VOPB>, 320 <&cru DCLK_VOPL>, 321 <&cru HCLK_RGA>, 322 <&cru HCLK_VOPB>, 323 <&cru HCLK_VOPL>, 324 <&cru PCLK_MIPI_DSI>, 325 <&cru SCLK_RGA_CORE>, 326 <&cru SCLK_VOPB_PWM>; 327 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 328 <&qos_vop_m0>, <&qos_vop_m1>; 329 #power-domain-cells = <0>; 330 }; 331 power-domain@PX30_PD_VI { 332 reg = <PX30_PD_VI>; 333 clocks = <&cru ACLK_CIF>, 334 <&cru ACLK_ISP>, 335 <&cru HCLK_CIF>, 336 <&cru HCLK_ISP>, 337 <&cru SCLK_ISP>; 338 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 339 <&qos_isp_wr>, <&qos_isp_m1>, 340 <&qos_vip>; 341 #power-domain-cells = <0>; 342 }; 343 power-domain@PX30_PD_GPU { 344 reg = <PX30_PD_GPU>; 345 clocks = <&cru SCLK_GPU>; 346 pm_qos = <&qos_gpu>; 347 #power-domain-cells = <0>; 348 }; 349 }; 350 }; 351 352 pmugrf: syscon@ff010000 { 353 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 354 reg = <0x0 0xff010000 0x0 0x1000>; 355 #address-cells = <1>; 356 #size-cells = <1>; 357 358 pmu_io_domains: io-domains { 359 compatible = "rockchip,px30-pmu-io-voltage-domain"; 360 status = "disabled"; 361 }; 362 363 reboot-mode { 364 compatible = "syscon-reboot-mode"; 365 offset = <0x200>; 366 mode-bootloader = <BOOT_BL_DOWNLOAD>; 367 mode-fastboot = <BOOT_FASTBOOT>; 368 mode-loader = <BOOT_BL_DOWNLOAD>; 369 mode-normal = <BOOT_NORMAL>; 370 mode-recovery = <BOOT_RECOVERY>; 371 }; 372 }; 373 374 uart0: serial@ff030000 { 375 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 376 reg = <0x0 0xff030000 0x0 0x100>; 377 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 379 clock-names = "baudclk", "apb_pclk"; 380 dmas = <&dmac 0>, <&dmac 1>; 381 dma-names = "tx", "rx"; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 386 status = "disabled"; 387 }; 388 389 i2s0_8ch: i2s@ff060000 { 390 compatible = "rockchip,px30-i2s-tdm"; 391 reg = <0x0 0xff060000 0x0 0x1000>; 392 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; 394 clock-names = "mclk_tx", "mclk_rx", "hclk"; 395 dmas = <&dmac 16>, <&dmac 17>; 396 dma-names = "tx", "rx"; 397 rockchip,grf = <&grf>; 398 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; 399 reset-names = "tx-m", "rx-m"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx 402 &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx 403 &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 404 &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 405 &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 406 &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; 407 #sound-dai-cells = <0>; 408 status = "disabled"; 409 }; 410 411 i2s1_2ch: i2s@ff070000 { 412 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 413 reg = <0x0 0xff070000 0x0 0x1000>; 414 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 416 clock-names = "i2s_clk", "i2s_hclk"; 417 dmas = <&dmac 18>, <&dmac 19>; 418 dma-names = "tx", "rx"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 421 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 422 #sound-dai-cells = <0>; 423 status = "disabled"; 424 }; 425 426 i2s2_2ch: i2s@ff080000 { 427 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 428 reg = <0x0 0xff080000 0x0 0x1000>; 429 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 431 clock-names = "i2s_clk", "i2s_hclk"; 432 dmas = <&dmac 20>, <&dmac 21>; 433 dma-names = "tx", "rx"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 436 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 437 #sound-dai-cells = <0>; 438 status = "disabled"; 439 }; 440 441 gic: interrupt-controller@ff131000 { 442 compatible = "arm,gic-400"; 443 #interrupt-cells = <3>; 444 #address-cells = <0>; 445 interrupt-controller; 446 reg = <0x0 0xff131000 0 0x1000>, 447 <0x0 0xff132000 0 0x2000>, 448 <0x0 0xff134000 0 0x2000>, 449 <0x0 0xff136000 0 0x2000>; 450 interrupts = <GIC_PPI 9 451 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 452 }; 453 454 grf: syscon@ff140000 { 455 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 456 reg = <0x0 0xff140000 0x0 0x1000>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 460 io_domains: io-domains { 461 compatible = "rockchip,px30-io-voltage-domain"; 462 status = "disabled"; 463 }; 464 465 lvds: lvds { 466 compatible = "rockchip,px30-lvds"; 467 phys = <&dsi_dphy>; 468 phy-names = "dphy"; 469 rockchip,grf = <&grf>; 470 rockchip,output = "lvds"; 471 status = "disabled"; 472 473 ports { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 477 port@0 { 478 reg = <0>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 482 lvds_vopb_in: endpoint@0 { 483 reg = <0>; 484 remote-endpoint = <&vopb_out_lvds>; 485 }; 486 487 lvds_vopl_in: endpoint@1 { 488 reg = <1>; 489 remote-endpoint = <&vopl_out_lvds>; 490 }; 491 }; 492 }; 493 }; 494 }; 495 496 uart1: serial@ff158000 { 497 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 498 reg = <0x0 0xff158000 0x0 0x100>; 499 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 501 clock-names = "baudclk", "apb_pclk"; 502 dmas = <&dmac 2>, <&dmac 3>; 503 dma-names = "tx", "rx"; 504 reg-shift = <2>; 505 reg-io-width = <4>; 506 pinctrl-names = "default"; 507 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 508 status = "disabled"; 509 }; 510 511 uart2: serial@ff160000 { 512 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 513 reg = <0x0 0xff160000 0x0 0x100>; 514 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 516 clock-names = "baudclk", "apb_pclk"; 517 dmas = <&dmac 4>, <&dmac 5>; 518 dma-names = "tx", "rx"; 519 reg-shift = <2>; 520 reg-io-width = <4>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&uart2m0_xfer>; 523 status = "disabled"; 524 }; 525 526 uart3: serial@ff168000 { 527 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 528 reg = <0x0 0xff168000 0x0 0x100>; 529 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 531 clock-names = "baudclk", "apb_pclk"; 532 dmas = <&dmac 6>, <&dmac 7>; 533 dma-names = "tx", "rx"; 534 reg-shift = <2>; 535 reg-io-width = <4>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 538 status = "disabled"; 539 }; 540 541 uart4: serial@ff170000 { 542 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 543 reg = <0x0 0xff170000 0x0 0x100>; 544 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 546 clock-names = "baudclk", "apb_pclk"; 547 dmas = <&dmac 8>, <&dmac 9>; 548 dma-names = "tx", "rx"; 549 reg-shift = <2>; 550 reg-io-width = <4>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 553 status = "disabled"; 554 }; 555 556 uart5: serial@ff178000 { 557 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 558 reg = <0x0 0xff178000 0x0 0x100>; 559 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 561 clock-names = "baudclk", "apb_pclk"; 562 dmas = <&dmac 10>, <&dmac 11>; 563 dma-names = "tx", "rx"; 564 reg-shift = <2>; 565 reg-io-width = <4>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 568 status = "disabled"; 569 }; 570 571 i2c0: i2c@ff180000 { 572 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 573 reg = <0x0 0xff180000 0x0 0x1000>; 574 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 575 clock-names = "i2c", "pclk"; 576 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&i2c0_xfer>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 i2c1: i2c@ff190000 { 585 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 586 reg = <0x0 0xff190000 0x0 0x1000>; 587 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 588 clock-names = "i2c", "pclk"; 589 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&i2c1_xfer>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 }; 596 597 i2c2: i2c@ff1a0000 { 598 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 599 reg = <0x0 0xff1a0000 0x0 0x1000>; 600 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 601 clock-names = "i2c", "pclk"; 602 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&i2c2_xfer>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 i2c3: i2c@ff1b0000 { 611 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 612 reg = <0x0 0xff1b0000 0x0 0x1000>; 613 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 614 clock-names = "i2c", "pclk"; 615 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&i2c3_xfer>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 spi0: spi@ff1d0000 { 624 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 625 reg = <0x0 0xff1d0000 0x0 0x1000>; 626 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 628 clock-names = "spiclk", "apb_pclk"; 629 dmas = <&dmac 12>, <&dmac 13>; 630 dma-names = "tx", "rx"; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 spi1: spi@ff1d8000 { 639 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 640 reg = <0x0 0xff1d8000 0x0 0x1000>; 641 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 643 clock-names = "spiclk", "apb_pclk"; 644 dmas = <&dmac 14>, <&dmac 15>; 645 dma-names = "tx", "rx"; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 status = "disabled"; 651 }; 652 653 wdt: watchdog@ff1e0000 { 654 compatible = "rockchip,px30-wdt", "snps,dw-wdt"; 655 reg = <0x0 0xff1e0000 0x0 0x100>; 656 clocks = <&cru PCLK_WDT_NS>; 657 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 658 status = "disabled"; 659 }; 660 661 pwm0: pwm@ff200000 { 662 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 663 reg = <0x0 0xff200000 0x0 0x10>; 664 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 665 clock-names = "pwm", "pclk"; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&pwm0_pin>; 668 #pwm-cells = <3>; 669 status = "disabled"; 670 }; 671 672 pwm1: pwm@ff200010 { 673 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 674 reg = <0x0 0xff200010 0x0 0x10>; 675 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 676 clock-names = "pwm", "pclk"; 677 pinctrl-names = "default"; 678 pinctrl-0 = <&pwm1_pin>; 679 #pwm-cells = <3>; 680 status = "disabled"; 681 }; 682 683 pwm2: pwm@ff200020 { 684 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 685 reg = <0x0 0xff200020 0x0 0x10>; 686 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 687 clock-names = "pwm", "pclk"; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&pwm2_pin>; 690 #pwm-cells = <3>; 691 status = "disabled"; 692 }; 693 694 pwm3: pwm@ff200030 { 695 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 696 reg = <0x0 0xff200030 0x0 0x10>; 697 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 698 clock-names = "pwm", "pclk"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&pwm3_pin>; 701 #pwm-cells = <3>; 702 status = "disabled"; 703 }; 704 705 pwm4: pwm@ff208000 { 706 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 707 reg = <0x0 0xff208000 0x0 0x10>; 708 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 709 clock-names = "pwm", "pclk"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&pwm4_pin>; 712 #pwm-cells = <3>; 713 status = "disabled"; 714 }; 715 716 pwm5: pwm@ff208010 { 717 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 718 reg = <0x0 0xff208010 0x0 0x10>; 719 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 720 clock-names = "pwm", "pclk"; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&pwm5_pin>; 723 #pwm-cells = <3>; 724 status = "disabled"; 725 }; 726 727 pwm6: pwm@ff208020 { 728 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 729 reg = <0x0 0xff208020 0x0 0x10>; 730 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 731 clock-names = "pwm", "pclk"; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pwm6_pin>; 734 #pwm-cells = <3>; 735 status = "disabled"; 736 }; 737 738 pwm7: pwm@ff208030 { 739 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 740 reg = <0x0 0xff208030 0x0 0x10>; 741 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 742 clock-names = "pwm", "pclk"; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&pwm7_pin>; 745 #pwm-cells = <3>; 746 status = "disabled"; 747 }; 748 749 rktimer: timer@ff210000 { 750 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 751 reg = <0x0 0xff210000 0x0 0x1000>; 752 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 754 clock-names = "pclk", "timer"; 755 }; 756 757 dmac: dma-controller@ff240000 { 758 compatible = "arm,pl330", "arm,primecell"; 759 reg = <0x0 0xff240000 0x0 0x4000>; 760 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 762 arm,pl330-periph-burst; 763 clocks = <&cru ACLK_DMAC>; 764 clock-names = "apb_pclk"; 765 #dma-cells = <1>; 766 }; 767 768 tsadc: tsadc@ff280000 { 769 compatible = "rockchip,px30-tsadc"; 770 reg = <0x0 0xff280000 0x0 0x100>; 771 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 772 assigned-clocks = <&cru SCLK_TSADC>; 773 assigned-clock-rates = <50000>; 774 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 775 clock-names = "tsadc", "apb_pclk"; 776 resets = <&cru SRST_TSADC>; 777 reset-names = "tsadc-apb"; 778 rockchip,grf = <&grf>; 779 rockchip,hw-tshut-temp = <120000>; 780 pinctrl-names = "init", "default", "sleep"; 781 pinctrl-0 = <&tsadc_otp_pin>; 782 pinctrl-1 = <&tsadc_otp_out>; 783 pinctrl-2 = <&tsadc_otp_pin>; 784 #thermal-sensor-cells = <1>; 785 status = "disabled"; 786 }; 787 788 saradc: saradc@ff288000 { 789 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 790 reg = <0x0 0xff288000 0x0 0x100>; 791 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 792 #io-channel-cells = <1>; 793 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 794 clock-names = "saradc", "apb_pclk"; 795 resets = <&cru SRST_SARADC_P>; 796 reset-names = "saradc-apb"; 797 status = "disabled"; 798 }; 799 800 otp: nvmem@ff290000 { 801 compatible = "rockchip,px30-otp"; 802 reg = <0x0 0xff290000 0x0 0x4000>; 803 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 804 <&cru PCLK_OTP_PHY>; 805 clock-names = "otp", "apb_pclk", "phy"; 806 resets = <&cru SRST_OTP_PHY>; 807 reset-names = "phy"; 808 #address-cells = <1>; 809 #size-cells = <1>; 810 811 /* Data cells */ 812 cpu_id: id@7 { 813 reg = <0x07 0x10>; 814 }; 815 cpu_leakage: cpu-leakage@17 { 816 reg = <0x17 0x1>; 817 }; 818 performance: performance@1e { 819 reg = <0x1e 0x1>; 820 bits = <4 3>; 821 }; 822 }; 823 824 cru: clock-controller@ff2b0000 { 825 compatible = "rockchip,px30-cru"; 826 reg = <0x0 0xff2b0000 0x0 0x1000>; 827 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 828 clock-names = "xin24m", "gpll"; 829 rockchip,grf = <&grf>; 830 #clock-cells = <1>; 831 #reset-cells = <1>; 832 833 assigned-clocks = <&cru PLL_NPLL>, 834 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 835 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 836 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 837 838 assigned-clock-rates = <1188000000>, 839 <200000000>, <200000000>, 840 <150000000>, <150000000>, 841 <100000000>, <200000000>; 842 }; 843 844 pmucru: clock-controller@ff2bc000 { 845 compatible = "rockchip,px30-pmucru"; 846 reg = <0x0 0xff2bc000 0x0 0x1000>; 847 clocks = <&xin24m>; 848 clock-names = "xin24m"; 849 rockchip,grf = <&grf>; 850 #clock-cells = <1>; 851 #reset-cells = <1>; 852 853 assigned-clocks = 854 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 855 <&pmucru SCLK_WIFI_PMU>; 856 assigned-clock-rates = 857 <1200000000>, <100000000>, 858 <26000000>; 859 }; 860 861 usb2phy_grf: syscon@ff2c0000 { 862 compatible = "rockchip,px30-usb2phy-grf", "syscon", 863 "simple-mfd"; 864 reg = <0x0 0xff2c0000 0x0 0x10000>; 865 #address-cells = <1>; 866 #size-cells = <1>; 867 868 u2phy: usb2phy@100 { 869 compatible = "rockchip,px30-usb2phy"; 870 reg = <0x100 0x20>; 871 clocks = <&pmucru SCLK_USBPHY_REF>; 872 clock-names = "phyclk"; 873 #clock-cells = <0>; 874 assigned-clocks = <&cru USB480M>; 875 assigned-clock-parents = <&u2phy>; 876 clock-output-names = "usb480m_phy"; 877 status = "disabled"; 878 879 u2phy_host: host-port { 880 #phy-cells = <0>; 881 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 882 interrupt-names = "linestate"; 883 status = "disabled"; 884 }; 885 886 u2phy_otg: otg-port { 887 #phy-cells = <0>; 888 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "otg-bvalid", "otg-id", 892 "linestate"; 893 status = "disabled"; 894 }; 895 }; 896 }; 897 898 dsi_dphy: phy@ff2e0000 { 899 compatible = "rockchip,px30-dsi-dphy"; 900 reg = <0x0 0xff2e0000 0x0 0x10000>; 901 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 902 clock-names = "ref", "pclk"; 903 resets = <&cru SRST_MIPIDSIPHY_P>; 904 reset-names = "apb"; 905 #phy-cells = <0>; 906 power-domains = <&power PX30_PD_VO>; 907 status = "disabled"; 908 }; 909 910 csi_dphy: phy@ff2f0000 { 911 compatible = "rockchip,px30-csi-dphy"; 912 reg = <0x0 0xff2f0000 0x0 0x4000>; 913 clocks = <&cru PCLK_MIPICSIPHY>; 914 clock-names = "pclk"; 915 #phy-cells = <0>; 916 power-domains = <&power PX30_PD_VI>; 917 resets = <&cru SRST_MIPICSIPHY_P>; 918 reset-names = "apb"; 919 rockchip,grf = <&grf>; 920 status = "disabled"; 921 }; 922 923 usb20_otg: usb@ff300000 { 924 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 925 "snps,dwc2"; 926 reg = <0x0 0xff300000 0x0 0x40000>; 927 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&cru HCLK_OTG>; 929 clock-names = "otg"; 930 dr_mode = "otg"; 931 g-np-tx-fifo-size = <16>; 932 g-rx-fifo-size = <280>; 933 g-tx-fifo-size = <256 128 128 64 32 16>; 934 phys = <&u2phy_otg>; 935 phy-names = "usb2-phy"; 936 power-domains = <&power PX30_PD_USB>; 937 status = "disabled"; 938 }; 939 940 usb_host0_ehci: usb@ff340000 { 941 compatible = "generic-ehci"; 942 reg = <0x0 0xff340000 0x0 0x10000>; 943 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&cru HCLK_HOST>; 945 phys = <&u2phy_host>; 946 phy-names = "usb"; 947 power-domains = <&power PX30_PD_USB>; 948 status = "disabled"; 949 }; 950 951 usb_host0_ohci: usb@ff350000 { 952 compatible = "generic-ohci"; 953 reg = <0x0 0xff350000 0x0 0x10000>; 954 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&cru HCLK_HOST>; 956 phys = <&u2phy_host>; 957 phy-names = "usb"; 958 power-domains = <&power PX30_PD_USB>; 959 status = "disabled"; 960 }; 961 962 gmac: ethernet@ff360000 { 963 compatible = "rockchip,px30-gmac"; 964 reg = <0x0 0xff360000 0x0 0x10000>; 965 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 966 interrupt-names = "macirq"; 967 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 968 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 969 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 970 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 971 clock-names = "stmmaceth", "mac_clk_rx", 972 "mac_clk_tx", "clk_mac_ref", 973 "clk_mac_refout", "aclk_mac", 974 "pclk_mac", "clk_mac_speed"; 975 rockchip,grf = <&grf>; 976 phy-mode = "rmii"; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 979 power-domains = <&power PX30_PD_GMAC>; 980 resets = <&cru SRST_GMAC_A>; 981 reset-names = "stmmaceth"; 982 status = "disabled"; 983 }; 984 985 sdmmc: mmc@ff370000 { 986 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 987 reg = <0x0 0xff370000 0x0 0x4000>; 988 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 990 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 991 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 992 bus-width = <4>; 993 fifo-depth = <0x100>; 994 max-frequency = <150000000>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 997 power-domains = <&power PX30_PD_SDCARD>; 998 status = "disabled"; 999 }; 1000 1001 sdio: mmc@ff380000 { 1002 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1003 reg = <0x0 0xff380000 0x0 0x4000>; 1004 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 1006 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1007 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1008 bus-width = <4>; 1009 fifo-depth = <0x100>; 1010 max-frequency = <150000000>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 1013 power-domains = <&power PX30_PD_MMC_NAND>; 1014 status = "disabled"; 1015 }; 1016 1017 emmc: mmc@ff390000 { 1018 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 1019 reg = <0x0 0xff390000 0x0 0x4000>; 1020 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 1022 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 1023 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1024 bus-width = <8>; 1025 fifo-depth = <0x100>; 1026 max-frequency = <150000000>; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 1029 power-domains = <&power PX30_PD_MMC_NAND>; 1030 status = "disabled"; 1031 }; 1032 1033 sfc: spi@ff3a0000 { 1034 compatible = "rockchip,sfc"; 1035 reg = <0x0 0xff3a0000 0x0 0x4000>; 1036 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1038 clock-names = "clk_sfc", "hclk_sfc"; 1039 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 1040 pinctrl-names = "default"; 1041 power-domains = <&power PX30_PD_MMC_NAND>; 1042 status = "disabled"; 1043 }; 1044 1045 nfc: nand-controller@ff3b0000 { 1046 compatible = "rockchip,px30-nfc"; 1047 reg = <0x0 0xff3b0000 0x0 0x4000>; 1048 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 1050 clock-names = "ahb", "nfc"; 1051 assigned-clocks = <&cru SCLK_NANDC>; 1052 assigned-clock-rates = <150000000>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 1055 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 1056 power-domains = <&power PX30_PD_MMC_NAND>; 1057 status = "disabled"; 1058 }; 1059 1060 gpu_opp_table: opp-table-1 { 1061 compatible = "operating-points-v2"; 1062 1063 opp-200000000 { 1064 opp-hz = /bits/ 64 <200000000>; 1065 opp-microvolt = <950000>; 1066 }; 1067 opp-300000000 { 1068 opp-hz = /bits/ 64 <300000000>; 1069 opp-microvolt = <975000>; 1070 }; 1071 opp-400000000 { 1072 opp-hz = /bits/ 64 <400000000>; 1073 opp-microvolt = <1050000>; 1074 }; 1075 opp-480000000 { 1076 opp-hz = /bits/ 64 <480000000>; 1077 opp-microvolt = <1125000>; 1078 }; 1079 }; 1080 1081 gpu: gpu@ff400000 { 1082 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1083 reg = <0x0 0xff400000 0x0 0x4000>; 1084 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1087 interrupt-names = "job", "mmu", "gpu"; 1088 clocks = <&cru SCLK_GPU>; 1089 #cooling-cells = <2>; 1090 power-domains = <&power PX30_PD_GPU>; 1091 operating-points-v2 = <&gpu_opp_table>; 1092 status = "disabled"; 1093 }; 1094 1095 vpu: video-codec@ff442000 { 1096 compatible = "rockchip,px30-vpu"; 1097 reg = <0x0 0xff442000 0x0 0x800>; 1098 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1100 interrupt-names = "vepu", "vdpu"; 1101 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1102 clock-names = "aclk", "hclk"; 1103 iommus = <&vpu_mmu>; 1104 power-domains = <&power PX30_PD_VPU>; 1105 }; 1106 1107 vpu_mmu: iommu@ff442800 { 1108 compatible = "rockchip,iommu"; 1109 reg = <0x0 0xff442800 0x0 0x100>; 1110 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1112 clock-names = "aclk", "iface"; 1113 #iommu-cells = <0>; 1114 power-domains = <&power PX30_PD_VPU>; 1115 }; 1116 1117 dsi: dsi@ff450000 { 1118 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; 1119 reg = <0x0 0xff450000 0x0 0x10000>; 1120 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&cru PCLK_MIPI_DSI>; 1122 clock-names = "pclk"; 1123 phys = <&dsi_dphy>; 1124 phy-names = "dphy"; 1125 power-domains = <&power PX30_PD_VO>; 1126 resets = <&cru SRST_MIPIDSI_HOST_P>; 1127 reset-names = "apb"; 1128 rockchip,grf = <&grf>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 status = "disabled"; 1132 1133 ports { 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 1137 port@0 { 1138 reg = <0>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 1142 dsi_in_vopb: endpoint@0 { 1143 reg = <0>; 1144 remote-endpoint = <&vopb_out_dsi>; 1145 }; 1146 1147 dsi_in_vopl: endpoint@1 { 1148 reg = <1>; 1149 remote-endpoint = <&vopl_out_dsi>; 1150 }; 1151 }; 1152 }; 1153 }; 1154 1155 vopb: vop@ff460000 { 1156 compatible = "rockchip,px30-vop-big"; 1157 reg = <0x0 0xff460000 0x0 0xefc>; 1158 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1160 <&cru HCLK_VOPB>; 1161 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1162 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1163 reset-names = "axi", "ahb", "dclk"; 1164 iommus = <&vopb_mmu>; 1165 power-domains = <&power PX30_PD_VO>; 1166 status = "disabled"; 1167 1168 vopb_out: port { 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 vopb_out_dsi: endpoint@0 { 1173 reg = <0>; 1174 remote-endpoint = <&dsi_in_vopb>; 1175 }; 1176 1177 vopb_out_lvds: endpoint@1 { 1178 reg = <1>; 1179 remote-endpoint = <&lvds_vopb_in>; 1180 }; 1181 }; 1182 }; 1183 1184 vopb_mmu: iommu@ff460f00 { 1185 compatible = "rockchip,iommu"; 1186 reg = <0x0 0xff460f00 0x0 0x100>; 1187 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1189 clock-names = "aclk", "iface"; 1190 power-domains = <&power PX30_PD_VO>; 1191 #iommu-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 vopl: vop@ff470000 { 1196 compatible = "rockchip,px30-vop-lit"; 1197 reg = <0x0 0xff470000 0x0 0xefc>; 1198 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1200 <&cru HCLK_VOPL>; 1201 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1202 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1203 reset-names = "axi", "ahb", "dclk"; 1204 iommus = <&vopl_mmu>; 1205 power-domains = <&power PX30_PD_VO>; 1206 status = "disabled"; 1207 1208 vopl_out: port { 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 1212 vopl_out_dsi: endpoint@0 { 1213 reg = <0>; 1214 remote-endpoint = <&dsi_in_vopl>; 1215 }; 1216 1217 vopl_out_lvds: endpoint@1 { 1218 reg = <1>; 1219 remote-endpoint = <&lvds_vopl_in>; 1220 }; 1221 }; 1222 }; 1223 1224 vopl_mmu: iommu@ff470f00 { 1225 compatible = "rockchip,iommu"; 1226 reg = <0x0 0xff470f00 0x0 0x100>; 1227 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1229 clock-names = "aclk", "iface"; 1230 power-domains = <&power PX30_PD_VO>; 1231 #iommu-cells = <0>; 1232 status = "disabled"; 1233 }; 1234 1235 isp: isp@ff4a0000 { 1236 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ 1237 reg = <0x0 0xff4a0000 0x0 0x8000>; 1238 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1241 interrupt-names = "isp", "mi", "mipi"; 1242 clocks = <&cru SCLK_ISP>, 1243 <&cru ACLK_ISP>, 1244 <&cru HCLK_ISP>, 1245 <&cru PCLK_ISP>; 1246 clock-names = "isp", "aclk", "hclk", "pclk"; 1247 iommus = <&isp_mmu>; 1248 phys = <&csi_dphy>; 1249 phy-names = "dphy"; 1250 power-domains = <&power PX30_PD_VI>; 1251 status = "disabled"; 1252 1253 ports { 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 1257 port@0 { 1258 reg = <0>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 }; 1262 }; 1263 }; 1264 1265 isp_mmu: iommu@ff4a8000 { 1266 compatible = "rockchip,iommu"; 1267 reg = <0x0 0xff4a8000 0x0 0x100>; 1268 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1270 clock-names = "aclk", "iface"; 1271 power-domains = <&power PX30_PD_VI>; 1272 rockchip,disable-mmu-reset; 1273 #iommu-cells = <0>; 1274 }; 1275 1276 qos_gmac: qos@ff518000 { 1277 compatible = "rockchip,px30-qos", "syscon"; 1278 reg = <0x0 0xff518000 0x0 0x20>; 1279 }; 1280 1281 qos_gpu: qos@ff520000 { 1282 compatible = "rockchip,px30-qos", "syscon"; 1283 reg = <0x0 0xff520000 0x0 0x20>; 1284 }; 1285 1286 qos_sdmmc: qos@ff52c000 { 1287 compatible = "rockchip,px30-qos", "syscon"; 1288 reg = <0x0 0xff52c000 0x0 0x20>; 1289 }; 1290 1291 qos_emmc: qos@ff538000 { 1292 compatible = "rockchip,px30-qos", "syscon"; 1293 reg = <0x0 0xff538000 0x0 0x20>; 1294 }; 1295 1296 qos_nand: qos@ff538080 { 1297 compatible = "rockchip,px30-qos", "syscon"; 1298 reg = <0x0 0xff538080 0x0 0x20>; 1299 }; 1300 1301 qos_sdio: qos@ff538100 { 1302 compatible = "rockchip,px30-qos", "syscon"; 1303 reg = <0x0 0xff538100 0x0 0x20>; 1304 }; 1305 1306 qos_sfc: qos@ff538180 { 1307 compatible = "rockchip,px30-qos", "syscon"; 1308 reg = <0x0 0xff538180 0x0 0x20>; 1309 }; 1310 1311 qos_usb_host: qos@ff540000 { 1312 compatible = "rockchip,px30-qos", "syscon"; 1313 reg = <0x0 0xff540000 0x0 0x20>; 1314 }; 1315 1316 qos_usb_otg: qos@ff540080 { 1317 compatible = "rockchip,px30-qos", "syscon"; 1318 reg = <0x0 0xff540080 0x0 0x20>; 1319 }; 1320 1321 qos_isp_128: qos@ff548000 { 1322 compatible = "rockchip,px30-qos", "syscon"; 1323 reg = <0x0 0xff548000 0x0 0x20>; 1324 }; 1325 1326 qos_isp_rd: qos@ff548080 { 1327 compatible = "rockchip,px30-qos", "syscon"; 1328 reg = <0x0 0xff548080 0x0 0x20>; 1329 }; 1330 1331 qos_isp_wr: qos@ff548100 { 1332 compatible = "rockchip,px30-qos", "syscon"; 1333 reg = <0x0 0xff548100 0x0 0x20>; 1334 }; 1335 1336 qos_isp_m1: qos@ff548180 { 1337 compatible = "rockchip,px30-qos", "syscon"; 1338 reg = <0x0 0xff548180 0x0 0x20>; 1339 }; 1340 1341 qos_vip: qos@ff548200 { 1342 compatible = "rockchip,px30-qos", "syscon"; 1343 reg = <0x0 0xff548200 0x0 0x20>; 1344 }; 1345 1346 qos_rga_rd: qos@ff550000 { 1347 compatible = "rockchip,px30-qos", "syscon"; 1348 reg = <0x0 0xff550000 0x0 0x20>; 1349 }; 1350 1351 qos_rga_wr: qos@ff550080 { 1352 compatible = "rockchip,px30-qos", "syscon"; 1353 reg = <0x0 0xff550080 0x0 0x20>; 1354 }; 1355 1356 qos_vop_m0: qos@ff550100 { 1357 compatible = "rockchip,px30-qos", "syscon"; 1358 reg = <0x0 0xff550100 0x0 0x20>; 1359 }; 1360 1361 qos_vop_m1: qos@ff550180 { 1362 compatible = "rockchip,px30-qos", "syscon"; 1363 reg = <0x0 0xff550180 0x0 0x20>; 1364 }; 1365 1366 qos_vpu: qos@ff558000 { 1367 compatible = "rockchip,px30-qos", "syscon"; 1368 reg = <0x0 0xff558000 0x0 0x20>; 1369 }; 1370 1371 qos_vpu_r128: qos@ff558080 { 1372 compatible = "rockchip,px30-qos", "syscon"; 1373 reg = <0x0 0xff558080 0x0 0x20>; 1374 }; 1375 1376 pinctrl: pinctrl { 1377 compatible = "rockchip,px30-pinctrl"; 1378 rockchip,grf = <&grf>; 1379 rockchip,pmu = <&pmugrf>; 1380 #address-cells = <2>; 1381 #size-cells = <2>; 1382 ranges; 1383 1384 gpio0: gpio@ff040000 { 1385 compatible = "rockchip,gpio-bank"; 1386 reg = <0x0 0xff040000 0x0 0x100>; 1387 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&pmucru PCLK_GPIO0_PMU>; 1389 gpio-controller; 1390 #gpio-cells = <2>; 1391 1392 interrupt-controller; 1393 #interrupt-cells = <2>; 1394 }; 1395 1396 gpio1: gpio@ff250000 { 1397 compatible = "rockchip,gpio-bank"; 1398 reg = <0x0 0xff250000 0x0 0x100>; 1399 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1400 clocks = <&cru PCLK_GPIO1>; 1401 gpio-controller; 1402 #gpio-cells = <2>; 1403 1404 interrupt-controller; 1405 #interrupt-cells = <2>; 1406 }; 1407 1408 gpio2: gpio@ff260000 { 1409 compatible = "rockchip,gpio-bank"; 1410 reg = <0x0 0xff260000 0x0 0x100>; 1411 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1412 clocks = <&cru PCLK_GPIO2>; 1413 gpio-controller; 1414 #gpio-cells = <2>; 1415 1416 interrupt-controller; 1417 #interrupt-cells = <2>; 1418 }; 1419 1420 gpio3: gpio@ff270000 { 1421 compatible = "rockchip,gpio-bank"; 1422 reg = <0x0 0xff270000 0x0 0x100>; 1423 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1424 clocks = <&cru PCLK_GPIO3>; 1425 gpio-controller; 1426 #gpio-cells = <2>; 1427 1428 interrupt-controller; 1429 #interrupt-cells = <2>; 1430 }; 1431 1432 pcfg_pull_up: pcfg-pull-up { 1433 bias-pull-up; 1434 }; 1435 1436 pcfg_pull_down: pcfg-pull-down { 1437 bias-pull-down; 1438 }; 1439 1440 pcfg_pull_none: pcfg-pull-none { 1441 bias-disable; 1442 }; 1443 1444 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1445 bias-disable; 1446 drive-strength = <2>; 1447 }; 1448 1449 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1450 bias-pull-up; 1451 drive-strength = <2>; 1452 }; 1453 1454 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1455 bias-pull-up; 1456 drive-strength = <4>; 1457 }; 1458 1459 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1460 bias-disable; 1461 drive-strength = <4>; 1462 }; 1463 1464 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1465 bias-pull-down; 1466 drive-strength = <4>; 1467 }; 1468 1469 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1470 bias-disable; 1471 drive-strength = <8>; 1472 }; 1473 1474 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1475 bias-pull-up; 1476 drive-strength = <8>; 1477 }; 1478 1479 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1480 bias-disable; 1481 drive-strength = <12>; 1482 }; 1483 1484 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1485 bias-pull-up; 1486 drive-strength = <12>; 1487 }; 1488 1489 pcfg_pull_none_smt: pcfg-pull-none-smt { 1490 bias-disable; 1491 input-schmitt-enable; 1492 }; 1493 1494 pcfg_output_high: pcfg-output-high { 1495 output-high; 1496 }; 1497 1498 pcfg_output_low: pcfg-output-low { 1499 output-low; 1500 }; 1501 1502 pcfg_input_high: pcfg-input-high { 1503 bias-pull-up; 1504 input-enable; 1505 }; 1506 1507 pcfg_input: pcfg-input { 1508 input-enable; 1509 }; 1510 1511 i2c0 { 1512 i2c0_xfer: i2c0-xfer { 1513 rockchip,pins = 1514 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1515 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1516 }; 1517 }; 1518 1519 i2c1 { 1520 i2c1_xfer: i2c1-xfer { 1521 rockchip,pins = 1522 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1523 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1524 }; 1525 }; 1526 1527 i2c2 { 1528 i2c2_xfer: i2c2-xfer { 1529 rockchip,pins = 1530 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1531 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1532 }; 1533 }; 1534 1535 i2c3 { 1536 i2c3_xfer: i2c3-xfer { 1537 rockchip,pins = 1538 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1539 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1540 }; 1541 }; 1542 1543 tsadc { 1544 tsadc_otp_pin: tsadc-otp-pin { 1545 rockchip,pins = 1546 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1547 }; 1548 1549 tsadc_otp_out: tsadc-otp-out { 1550 rockchip,pins = 1551 <0 RK_PA6 1 &pcfg_pull_none>; 1552 }; 1553 }; 1554 1555 uart0 { 1556 uart0_xfer: uart0-xfer { 1557 rockchip,pins = 1558 <0 RK_PB2 1 &pcfg_pull_up>, 1559 <0 RK_PB3 1 &pcfg_pull_up>; 1560 }; 1561 1562 uart0_cts: uart0-cts { 1563 rockchip,pins = 1564 <0 RK_PB4 1 &pcfg_pull_none>; 1565 }; 1566 1567 uart0_rts: uart0-rts { 1568 rockchip,pins = 1569 <0 RK_PB5 1 &pcfg_pull_none>; 1570 }; 1571 }; 1572 1573 uart1 { 1574 uart1_xfer: uart1-xfer { 1575 rockchip,pins = 1576 <1 RK_PC1 1 &pcfg_pull_up>, 1577 <1 RK_PC0 1 &pcfg_pull_up>; 1578 }; 1579 1580 uart1_cts: uart1-cts { 1581 rockchip,pins = 1582 <1 RK_PC2 1 &pcfg_pull_none>; 1583 }; 1584 1585 uart1_rts: uart1-rts { 1586 rockchip,pins = 1587 <1 RK_PC3 1 &pcfg_pull_none>; 1588 }; 1589 }; 1590 1591 uart2-m0 { 1592 uart2m0_xfer: uart2m0-xfer { 1593 rockchip,pins = 1594 <1 RK_PD2 2 &pcfg_pull_up>, 1595 <1 RK_PD3 2 &pcfg_pull_up>; 1596 }; 1597 }; 1598 1599 uart2-m1 { 1600 uart2m1_xfer: uart2m1-xfer { 1601 rockchip,pins = 1602 <2 RK_PB4 2 &pcfg_pull_up>, 1603 <2 RK_PB6 2 &pcfg_pull_up>; 1604 }; 1605 }; 1606 1607 uart3-m0 { 1608 uart3m0_xfer: uart3m0-xfer { 1609 rockchip,pins = 1610 <0 RK_PC0 2 &pcfg_pull_up>, 1611 <0 RK_PC1 2 &pcfg_pull_up>; 1612 }; 1613 1614 uart3m0_cts: uart3m0-cts { 1615 rockchip,pins = 1616 <0 RK_PC2 2 &pcfg_pull_none>; 1617 }; 1618 1619 uart3m0_rts: uart3m0-rts { 1620 rockchip,pins = 1621 <0 RK_PC3 2 &pcfg_pull_none>; 1622 }; 1623 }; 1624 1625 uart3-m1 { 1626 uart3m1_xfer: uart3m1-xfer { 1627 rockchip,pins = 1628 <1 RK_PB6 2 &pcfg_pull_up>, 1629 <1 RK_PB7 2 &pcfg_pull_up>; 1630 }; 1631 1632 uart3m1_cts: uart3m1-cts { 1633 rockchip,pins = 1634 <1 RK_PB4 2 &pcfg_pull_none>; 1635 }; 1636 1637 uart3m1_rts: uart3m1-rts { 1638 rockchip,pins = 1639 <1 RK_PB5 2 &pcfg_pull_none>; 1640 }; 1641 }; 1642 1643 uart4 { 1644 uart4_xfer: uart4-xfer { 1645 rockchip,pins = 1646 <1 RK_PD4 2 &pcfg_pull_up>, 1647 <1 RK_PD5 2 &pcfg_pull_up>; 1648 }; 1649 1650 uart4_cts: uart4-cts { 1651 rockchip,pins = 1652 <1 RK_PD6 2 &pcfg_pull_none>; 1653 }; 1654 1655 uart4_rts: uart4-rts { 1656 rockchip,pins = 1657 <1 RK_PD7 2 &pcfg_pull_none>; 1658 }; 1659 }; 1660 1661 uart5 { 1662 uart5_xfer: uart5-xfer { 1663 rockchip,pins = 1664 <3 RK_PA2 4 &pcfg_pull_up>, 1665 <3 RK_PA1 4 &pcfg_pull_up>; 1666 }; 1667 1668 uart5_cts: uart5-cts { 1669 rockchip,pins = 1670 <3 RK_PA3 4 &pcfg_pull_none>; 1671 }; 1672 1673 uart5_rts: uart5-rts { 1674 rockchip,pins = 1675 <3 RK_PA5 4 &pcfg_pull_none>; 1676 }; 1677 }; 1678 1679 spi0 { 1680 spi0_clk: spi0-clk { 1681 rockchip,pins = 1682 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1683 }; 1684 1685 spi0_csn: spi0-csn { 1686 rockchip,pins = 1687 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1688 }; 1689 1690 spi0_miso: spi0-miso { 1691 rockchip,pins = 1692 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1693 }; 1694 1695 spi0_mosi: spi0-mosi { 1696 rockchip,pins = 1697 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1698 }; 1699 1700 spi0_clk_hs: spi0-clk-hs { 1701 rockchip,pins = 1702 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1703 }; 1704 1705 spi0_miso_hs: spi0-miso-hs { 1706 rockchip,pins = 1707 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1708 }; 1709 1710 spi0_mosi_hs: spi0-mosi-hs { 1711 rockchip,pins = 1712 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1713 }; 1714 }; 1715 1716 spi1 { 1717 spi1_clk: spi1-clk { 1718 rockchip,pins = 1719 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1720 }; 1721 1722 spi1_csn0: spi1-csn0 { 1723 rockchip,pins = 1724 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1725 }; 1726 1727 spi1_csn1: spi1-csn1 { 1728 rockchip,pins = 1729 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1730 }; 1731 1732 spi1_miso: spi1-miso { 1733 rockchip,pins = 1734 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1735 }; 1736 1737 spi1_mosi: spi1-mosi { 1738 rockchip,pins = 1739 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1740 }; 1741 1742 spi1_clk_hs: spi1-clk-hs { 1743 rockchip,pins = 1744 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1745 }; 1746 1747 spi1_miso_hs: spi1-miso-hs { 1748 rockchip,pins = 1749 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1750 }; 1751 1752 spi1_mosi_hs: spi1-mosi-hs { 1753 rockchip,pins = 1754 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1755 }; 1756 }; 1757 1758 pdm { 1759 pdm_clk0m0: pdm-clk0m0 { 1760 rockchip,pins = 1761 <3 RK_PC6 2 &pcfg_pull_none>; 1762 }; 1763 1764 pdm_clk0m1: pdm-clk0m1 { 1765 rockchip,pins = 1766 <2 RK_PC6 1 &pcfg_pull_none>; 1767 }; 1768 1769 pdm_clk1: pdm-clk1 { 1770 rockchip,pins = 1771 <3 RK_PC7 2 &pcfg_pull_none>; 1772 }; 1773 1774 pdm_sdi0m0: pdm-sdi0m0 { 1775 rockchip,pins = 1776 <3 RK_PD3 2 &pcfg_pull_none>; 1777 }; 1778 1779 pdm_sdi0m1: pdm-sdi0m1 { 1780 rockchip,pins = 1781 <2 RK_PC5 2 &pcfg_pull_none>; 1782 }; 1783 1784 pdm_sdi1: pdm-sdi1 { 1785 rockchip,pins = 1786 <3 RK_PD0 2 &pcfg_pull_none>; 1787 }; 1788 1789 pdm_sdi2: pdm-sdi2 { 1790 rockchip,pins = 1791 <3 RK_PD1 2 &pcfg_pull_none>; 1792 }; 1793 1794 pdm_sdi3: pdm-sdi3 { 1795 rockchip,pins = 1796 <3 RK_PD2 2 &pcfg_pull_none>; 1797 }; 1798 1799 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1800 rockchip,pins = 1801 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1802 }; 1803 1804 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1805 rockchip,pins = 1806 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1807 }; 1808 1809 pdm_clk1_sleep: pdm-clk1-sleep { 1810 rockchip,pins = 1811 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1812 }; 1813 1814 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1815 rockchip,pins = 1816 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1817 }; 1818 1819 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1820 rockchip,pins = 1821 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1822 }; 1823 1824 pdm_sdi1_sleep: pdm-sdi1-sleep { 1825 rockchip,pins = 1826 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1827 }; 1828 1829 pdm_sdi2_sleep: pdm-sdi2-sleep { 1830 rockchip,pins = 1831 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1832 }; 1833 1834 pdm_sdi3_sleep: pdm-sdi3-sleep { 1835 rockchip,pins = 1836 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1837 }; 1838 }; 1839 1840 i2s0 { 1841 i2s0_8ch_mclk: i2s0-8ch-mclk { 1842 rockchip,pins = 1843 <3 RK_PC1 2 &pcfg_pull_none>; 1844 }; 1845 1846 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1847 rockchip,pins = 1848 <3 RK_PC3 2 &pcfg_pull_none>; 1849 }; 1850 1851 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1852 rockchip,pins = 1853 <3 RK_PB4 2 &pcfg_pull_none>; 1854 }; 1855 1856 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1857 rockchip,pins = 1858 <3 RK_PC2 2 &pcfg_pull_none>; 1859 }; 1860 1861 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1862 rockchip,pins = 1863 <3 RK_PB5 2 &pcfg_pull_none>; 1864 }; 1865 1866 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1867 rockchip,pins = 1868 <3 RK_PC4 2 &pcfg_pull_none>; 1869 }; 1870 1871 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1872 rockchip,pins = 1873 <3 RK_PC0 2 &pcfg_pull_none>; 1874 }; 1875 1876 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1877 rockchip,pins = 1878 <3 RK_PB7 2 &pcfg_pull_none>; 1879 }; 1880 1881 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1882 rockchip,pins = 1883 <3 RK_PB6 2 &pcfg_pull_none>; 1884 }; 1885 1886 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1887 rockchip,pins = 1888 <3 RK_PC5 2 &pcfg_pull_none>; 1889 }; 1890 1891 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1892 rockchip,pins = 1893 <3 RK_PB3 2 &pcfg_pull_none>; 1894 }; 1895 1896 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1897 rockchip,pins = 1898 <3 RK_PB1 2 &pcfg_pull_none>; 1899 }; 1900 1901 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1902 rockchip,pins = 1903 <3 RK_PB0 2 &pcfg_pull_none>; 1904 }; 1905 }; 1906 1907 i2s1 { 1908 i2s1_2ch_mclk: i2s1-2ch-mclk { 1909 rockchip,pins = 1910 <2 RK_PC3 1 &pcfg_pull_none>; 1911 }; 1912 1913 i2s1_2ch_sclk: i2s1-2ch-sclk { 1914 rockchip,pins = 1915 <2 RK_PC2 1 &pcfg_pull_none>; 1916 }; 1917 1918 i2s1_2ch_lrck: i2s1-2ch-lrck { 1919 rockchip,pins = 1920 <2 RK_PC1 1 &pcfg_pull_none>; 1921 }; 1922 1923 i2s1_2ch_sdi: i2s1-2ch-sdi { 1924 rockchip,pins = 1925 <2 RK_PC5 1 &pcfg_pull_none>; 1926 }; 1927 1928 i2s1_2ch_sdo: i2s1-2ch-sdo { 1929 rockchip,pins = 1930 <2 RK_PC4 1 &pcfg_pull_none>; 1931 }; 1932 }; 1933 1934 i2s2 { 1935 i2s2_2ch_mclk: i2s2-2ch-mclk { 1936 rockchip,pins = 1937 <3 RK_PA1 2 &pcfg_pull_none>; 1938 }; 1939 1940 i2s2_2ch_sclk: i2s2-2ch-sclk { 1941 rockchip,pins = 1942 <3 RK_PA2 2 &pcfg_pull_none>; 1943 }; 1944 1945 i2s2_2ch_lrck: i2s2-2ch-lrck { 1946 rockchip,pins = 1947 <3 RK_PA3 2 &pcfg_pull_none>; 1948 }; 1949 1950 i2s2_2ch_sdi: i2s2-2ch-sdi { 1951 rockchip,pins = 1952 <3 RK_PA5 2 &pcfg_pull_none>; 1953 }; 1954 1955 i2s2_2ch_sdo: i2s2-2ch-sdo { 1956 rockchip,pins = 1957 <3 RK_PA7 2 &pcfg_pull_none>; 1958 }; 1959 }; 1960 1961 sdmmc { 1962 sdmmc_clk: sdmmc-clk { 1963 rockchip,pins = 1964 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1965 }; 1966 1967 sdmmc_cmd: sdmmc-cmd { 1968 rockchip,pins = 1969 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1970 }; 1971 1972 sdmmc_det: sdmmc-det { 1973 rockchip,pins = 1974 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1975 }; 1976 1977 sdmmc_bus1: sdmmc-bus1 { 1978 rockchip,pins = 1979 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1980 }; 1981 1982 sdmmc_bus4: sdmmc-bus4 { 1983 rockchip,pins = 1984 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1985 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1986 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1987 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1988 }; 1989 }; 1990 1991 sdio { 1992 sdio_clk: sdio-clk { 1993 rockchip,pins = 1994 <1 RK_PC5 1 &pcfg_pull_none>; 1995 }; 1996 1997 sdio_cmd: sdio-cmd { 1998 rockchip,pins = 1999 <1 RK_PC4 1 &pcfg_pull_up>; 2000 }; 2001 2002 sdio_bus4: sdio-bus4 { 2003 rockchip,pins = 2004 <1 RK_PC6 1 &pcfg_pull_up>, 2005 <1 RK_PC7 1 &pcfg_pull_up>, 2006 <1 RK_PD0 1 &pcfg_pull_up>, 2007 <1 RK_PD1 1 &pcfg_pull_up>; 2008 }; 2009 }; 2010 2011 emmc { 2012 emmc_clk: emmc-clk { 2013 rockchip,pins = 2014 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 2015 }; 2016 2017 emmc_cmd: emmc-cmd { 2018 rockchip,pins = 2019 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 2020 }; 2021 2022 emmc_rstnout: emmc-rstnout { 2023 rockchip,pins = 2024 <1 RK_PB3 2 &pcfg_pull_none>; 2025 }; 2026 2027 emmc_bus1: emmc-bus1 { 2028 rockchip,pins = 2029 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 2030 }; 2031 2032 emmc_bus4: emmc-bus4 { 2033 rockchip,pins = 2034 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2035 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2036 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2037 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 2038 }; 2039 2040 emmc_bus8: emmc-bus8 { 2041 rockchip,pins = 2042 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2043 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2044 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2045 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 2046 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 2047 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 2048 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 2049 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 2050 }; 2051 }; 2052 2053 flash { 2054 flash_cs0: flash-cs0 { 2055 rockchip,pins = 2056 <1 RK_PB0 1 &pcfg_pull_none>; 2057 }; 2058 2059 flash_rdy: flash-rdy { 2060 rockchip,pins = 2061 <1 RK_PB1 1 &pcfg_pull_none>; 2062 }; 2063 2064 flash_dqs: flash-dqs { 2065 rockchip,pins = 2066 <1 RK_PB2 1 &pcfg_pull_none>; 2067 }; 2068 2069 flash_ale: flash-ale { 2070 rockchip,pins = 2071 <1 RK_PB3 1 &pcfg_pull_none>; 2072 }; 2073 2074 flash_cle: flash-cle { 2075 rockchip,pins = 2076 <1 RK_PB4 1 &pcfg_pull_none>; 2077 }; 2078 2079 flash_wrn: flash-wrn { 2080 rockchip,pins = 2081 <1 RK_PB5 1 &pcfg_pull_none>; 2082 }; 2083 2084 flash_csl: flash-csl { 2085 rockchip,pins = 2086 <1 RK_PB6 1 &pcfg_pull_none>; 2087 }; 2088 2089 flash_rdn: flash-rdn { 2090 rockchip,pins = 2091 <1 RK_PB7 1 &pcfg_pull_none>; 2092 }; 2093 2094 flash_bus8: flash-bus8 { 2095 rockchip,pins = 2096 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 2097 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 2098 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 2099 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 2100 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 2101 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 2102 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 2103 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 2104 }; 2105 }; 2106 2107 sfc { 2108 sfc_bus4: sfc-bus4 { 2109 rockchip,pins = 2110 <1 RK_PA0 3 &pcfg_pull_none>, 2111 <1 RK_PA1 3 &pcfg_pull_none>, 2112 <1 RK_PA2 3 &pcfg_pull_none>, 2113 <1 RK_PA3 3 &pcfg_pull_none>; 2114 }; 2115 2116 sfc_bus2: sfc-bus2 { 2117 rockchip,pins = 2118 <1 RK_PA0 3 &pcfg_pull_none>, 2119 <1 RK_PA1 3 &pcfg_pull_none>; 2120 }; 2121 2122 sfc_cs0: sfc-cs0 { 2123 rockchip,pins = 2124 <1 RK_PA4 3 &pcfg_pull_none>; 2125 }; 2126 2127 sfc_clk: sfc-clk { 2128 rockchip,pins = 2129 <1 RK_PB1 3 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 lcdc { 2134 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 2135 rockchip,pins = 2136 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 2137 }; 2138 2139 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 2140 rockchip,pins = 2141 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 2142 }; 2143 2144 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 2145 rockchip,pins = 2146 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 2147 }; 2148 2149 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 2150 rockchip,pins = 2151 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 2152 }; 2153 2154 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 2155 rockchip,pins = 2156 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2157 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2158 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2159 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2160 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2161 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2162 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2163 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2164 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2165 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2166 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2167 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2168 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2169 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2170 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2171 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2172 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2173 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2174 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2175 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2176 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2177 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2178 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2179 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2180 }; 2181 2182 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2183 rockchip,pins = 2184 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2185 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2186 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2187 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2188 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2189 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2190 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2191 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2192 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2193 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2194 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2195 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2196 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2197 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2198 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2199 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2200 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2201 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2202 }; 2203 2204 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2205 rockchip,pins = 2206 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2207 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2208 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2209 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2210 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2211 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2212 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2213 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2214 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2215 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2216 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2217 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2218 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2219 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2220 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2221 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2222 }; 2223 2224 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2225 rockchip,pins = 2226 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2227 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2228 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2229 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2230 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2231 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2232 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2233 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2234 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2235 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2236 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2237 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2238 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2239 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2240 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2241 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2242 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2243 }; 2244 2245 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2246 rockchip,pins = 2247 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2248 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2249 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2250 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2251 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2252 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2253 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2254 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2255 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2256 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2257 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2258 }; 2259 2260 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2261 rockchip,pins = 2262 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2263 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2264 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2265 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2266 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2267 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2268 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2269 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2270 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2271 }; 2272 }; 2273 2274 pwm0 { 2275 pwm0_pin: pwm0-pin { 2276 rockchip,pins = 2277 <0 RK_PB7 1 &pcfg_pull_none>; 2278 }; 2279 }; 2280 2281 pwm1 { 2282 pwm1_pin: pwm1-pin { 2283 rockchip,pins = 2284 <0 RK_PC0 1 &pcfg_pull_none>; 2285 }; 2286 }; 2287 2288 pwm2 { 2289 pwm2_pin: pwm2-pin { 2290 rockchip,pins = 2291 <2 RK_PB5 1 &pcfg_pull_none>; 2292 }; 2293 }; 2294 2295 pwm3 { 2296 pwm3_pin: pwm3-pin { 2297 rockchip,pins = 2298 <0 RK_PC1 1 &pcfg_pull_none>; 2299 }; 2300 }; 2301 2302 pwm4 { 2303 pwm4_pin: pwm4-pin { 2304 rockchip,pins = 2305 <3 RK_PC2 3 &pcfg_pull_none>; 2306 }; 2307 }; 2308 2309 pwm5 { 2310 pwm5_pin: pwm5-pin { 2311 rockchip,pins = 2312 <3 RK_PC3 3 &pcfg_pull_none>; 2313 }; 2314 }; 2315 2316 pwm6 { 2317 pwm6_pin: pwm6-pin { 2318 rockchip,pins = 2319 <3 RK_PC4 3 &pcfg_pull_none>; 2320 }; 2321 }; 2322 2323 pwm7 { 2324 pwm7_pin: pwm7-pin { 2325 rockchip,pins = 2326 <3 RK_PC5 3 &pcfg_pull_none>; 2327 }; 2328 }; 2329 2330 gmac { 2331 rmii_pins: rmii-pins { 2332 rockchip,pins = 2333 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2334 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2335 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2336 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2337 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2338 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2339 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2340 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2341 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2342 }; 2343 2344 mac_refclk_12ma: mac-refclk-12ma { 2345 rockchip,pins = 2346 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2347 }; 2348 2349 mac_refclk: mac-refclk { 2350 rockchip,pins = 2351 <2 RK_PB2 2 &pcfg_pull_none>; 2352 }; 2353 }; 2354 2355 cif-m0 { 2356 cif_clkout_m0: cif-clkout-m0 { 2357 rockchip,pins = 2358 <2 RK_PB3 1 &pcfg_pull_none>; 2359 }; 2360 2361 dvp_d2d9_m0: dvp-d2d9-m0 { 2362 rockchip,pins = 2363 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2364 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2365 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2366 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2367 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2368 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2369 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2370 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2371 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2372 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2373 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2374 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2375 }; 2376 2377 dvp_d0d1_m0: dvp-d0d1-m0 { 2378 rockchip,pins = 2379 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2380 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2381 }; 2382 2383 dvp_d10d11_m0:d10-d11-m0 { 2384 rockchip,pins = 2385 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2386 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2387 }; 2388 }; 2389 2390 cif-m1 { 2391 cif_clkout_m1: cif-clkout-m1 { 2392 rockchip,pins = 2393 <3 RK_PD0 3 &pcfg_pull_none>; 2394 }; 2395 2396 dvp_d2d9_m1: dvp-d2d9-m1 { 2397 rockchip,pins = 2398 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2399 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2400 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2401 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2402 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2403 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2404 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2405 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2406 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2407 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2408 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2409 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2410 }; 2411 2412 dvp_d0d1_m1: dvp-d0d1-m1 { 2413 rockchip,pins = 2414 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2415 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2416 }; 2417 2418 dvp_d10d11_m1:d10-d11-m1 { 2419 rockchip,pins = 2420 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2421 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2422 }; 2423 }; 2424 2425 isp { 2426 isp_prelight: isp-prelight { 2427 rockchip,pins = 2428 <3 RK_PD1 4 &pcfg_pull_none>; 2429 }; 2430 }; 2431 }; 2432}; 2433