1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 dynamic-power-coefficient = <120>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cpu0_opp_table>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x1>; 54 clocks = <&cru ARMCLK>; 55 #cooling-cells = <2>; 56 dynamic-power-coefficient = <120>; 57 enable-method = "psci"; 58 next-level-cache = <&l2>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x2>; 66 clocks = <&cru ARMCLK>; 67 #cooling-cells = <2>; 68 dynamic-power-coefficient = <120>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x3>; 78 clocks = <&cru ARMCLK>; 79 #cooling-cells = <2>; 80 dynamic-power-coefficient = <120>; 81 enable-method = "psci"; 82 next-level-cache = <&l2>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 }; 85 86 l2: l2-cache0 { 87 compatible = "cache"; 88 }; 89 }; 90 91 cpu0_opp_table: opp_table0 { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 95 opp-408000000 { 96 opp-hz = /bits/ 64 <408000000>; 97 opp-microvolt = <950000>; 98 clock-latency-ns = <40000>; 99 opp-suspend; 100 }; 101 opp-600000000 { 102 opp-hz = /bits/ 64 <600000000>; 103 opp-microvolt = <950000>; 104 clock-latency-ns = <40000>; 105 }; 106 opp-816000000 { 107 opp-hz = /bits/ 64 <816000000>; 108 opp-microvolt = <1000000>; 109 clock-latency-ns = <40000>; 110 }; 111 opp-1008000000 { 112 opp-hz = /bits/ 64 <1008000000>; 113 opp-microvolt = <1100000>; 114 clock-latency-ns = <40000>; 115 }; 116 opp-1200000000 { 117 opp-hz = /bits/ 64 <1200000000>; 118 opp-microvolt = <1225000>; 119 clock-latency-ns = <40000>; 120 }; 121 opp-1296000000 { 122 opp-hz = /bits/ 64 <1296000000>; 123 opp-microvolt = <1300000>; 124 clock-latency-ns = <40000>; 125 }; 126 }; 127 128 amba { 129 compatible = "simple-bus"; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 dmac: dmac@ff1f0000 { 135 compatible = "arm,pl330", "arm,primecell"; 136 reg = <0x0 0xff1f0000 0x0 0x4000>; 137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&cru ACLK_DMAC>; 140 clock-names = "apb_pclk"; 141 #dma-cells = <1>; 142 }; 143 }; 144 145 analog_sound: analog-sound { 146 compatible = "simple-audio-card"; 147 simple-audio-card,format = "i2s"; 148 simple-audio-card,mclk-fs = <256>; 149 simple-audio-card,name = "Analog"; 150 status = "disabled"; 151 152 simple-audio-card,cpu { 153 sound-dai = <&i2s1>; 154 }; 155 156 simple-audio-card,codec { 157 sound-dai = <&codec>; 158 }; 159 }; 160 161 arm-pmu { 162 compatible = "arm,cortex-a53-pmu"; 163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 168 }; 169 170 display_subsystem: display-subsystem { 171 compatible = "rockchip,display-subsystem"; 172 ports = <&vop_out>; 173 }; 174 175 hdmi_sound: hdmi-sound { 176 compatible = "simple-audio-card"; 177 simple-audio-card,format = "i2s"; 178 simple-audio-card,mclk-fs = <128>; 179 simple-audio-card,name = "HDMI"; 180 status = "disabled"; 181 182 simple-audio-card,cpu { 183 sound-dai = <&i2s0>; 184 }; 185 186 simple-audio-card,codec { 187 sound-dai = <&hdmi>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0", "arm,psci-0.2"; 193 method = "smc"; 194 }; 195 196 timer { 197 compatible = "arm,armv8-timer"; 198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 #clock-cells = <0>; 207 clock-frequency = <24000000>; 208 clock-output-names = "xin24m"; 209 }; 210 211 i2s0: i2s@ff000000 { 212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 213 reg = <0x0 0xff000000 0x0 0x1000>; 214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 216 clock-names = "i2s_clk", "i2s_hclk"; 217 dmas = <&dmac 11>, <&dmac 12>; 218 dma-names = "tx", "rx"; 219 #sound-dai-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2s1: i2s@ff010000 { 224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 225 reg = <0x0 0xff010000 0x0 0x1000>; 226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 228 clock-names = "i2s_clk", "i2s_hclk"; 229 dmas = <&dmac 14>, <&dmac 15>; 230 dma-names = "tx", "rx"; 231 #sound-dai-cells = <0>; 232 status = "disabled"; 233 }; 234 235 i2s2: i2s@ff020000 { 236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 237 reg = <0x0 0xff020000 0x0 0x1000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 240 clock-names = "i2s_clk", "i2s_hclk"; 241 dmas = <&dmac 0>, <&dmac 1>; 242 dma-names = "tx", "rx"; 243 #sound-dai-cells = <0>; 244 status = "disabled"; 245 }; 246 247 spdif: spdif@ff030000 { 248 compatible = "rockchip,rk3328-spdif"; 249 reg = <0x0 0xff030000 0x0 0x1000>; 250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 252 clock-names = "mclk", "hclk"; 253 dmas = <&dmac 10>; 254 dma-names = "tx"; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&spdifm2_tx>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 }; 260 261 pdm: pdm@ff040000 { 262 compatible = "rockchip,pdm"; 263 reg = <0x0 0xff040000 0x0 0x1000>; 264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 265 clock-names = "pdm_clk", "pdm_hclk"; 266 dmas = <&dmac 16>; 267 dma-names = "rx"; 268 pinctrl-names = "default", "sleep"; 269 pinctrl-0 = <&pdmm0_clk 270 &pdmm0_sdi0 271 &pdmm0_sdi1 272 &pdmm0_sdi2 273 &pdmm0_sdi3>; 274 pinctrl-1 = <&pdmm0_clk_sleep 275 &pdmm0_sdi0_sleep 276 &pdmm0_sdi1_sleep 277 &pdmm0_sdi2_sleep 278 &pdmm0_sdi3_sleep>; 279 status = "disabled"; 280 }; 281 282 grf: syscon@ff100000 { 283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 284 reg = <0x0 0xff100000 0x0 0x1000>; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 288 io_domains: io-domains { 289 compatible = "rockchip,rk3328-io-voltage-domain"; 290 status = "disabled"; 291 }; 292 293 grf_gpio: grf-gpio { 294 compatible = "rockchip,rk3328-grf-gpio"; 295 gpio-controller; 296 #gpio-cells = <2>; 297 }; 298 299 power: power-controller { 300 compatible = "rockchip,rk3328-power-controller"; 301 #power-domain-cells = <1>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 pd_hevc@RK3328_PD_HEVC { 306 reg = <RK3328_PD_HEVC>; 307 }; 308 pd_video@RK3328_PD_VIDEO { 309 reg = <RK3328_PD_VIDEO>; 310 }; 311 pd_vpu@RK3328_PD_VPU { 312 reg = <RK3328_PD_VPU>; 313 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 314 }; 315 }; 316 317 reboot-mode { 318 compatible = "syscon-reboot-mode"; 319 offset = <0x5c8>; 320 mode-normal = <BOOT_NORMAL>; 321 mode-recovery = <BOOT_RECOVERY>; 322 mode-bootloader = <BOOT_FASTBOOT>; 323 mode-loader = <BOOT_BL_DOWNLOAD>; 324 }; 325 }; 326 327 uart0: serial@ff110000 { 328 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 329 reg = <0x0 0xff110000 0x0 0x100>; 330 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 332 clock-names = "baudclk", "apb_pclk"; 333 dmas = <&dmac 2>, <&dmac 3>; 334 dma-names = "tx", "rx"; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 337 reg-io-width = <4>; 338 reg-shift = <2>; 339 status = "disabled"; 340 }; 341 342 uart1: serial@ff120000 { 343 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 344 reg = <0x0 0xff120000 0x0 0x100>; 345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 347 clock-names = "baudclk", "apb_pclk"; 348 dmas = <&dmac 4>, <&dmac 5>; 349 dma-names = "tx", "rx"; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 352 reg-io-width = <4>; 353 reg-shift = <2>; 354 status = "disabled"; 355 }; 356 357 uart2: serial@ff130000 { 358 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 359 reg = <0x0 0xff130000 0x0 0x100>; 360 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 362 clock-names = "baudclk", "apb_pclk"; 363 dmas = <&dmac 6>, <&dmac 7>; 364 dma-names = "tx", "rx"; 365 pinctrl-names = "default"; 366 pinctrl-0 = <&uart2m1_xfer>; 367 reg-io-width = <4>; 368 reg-shift = <2>; 369 status = "disabled"; 370 }; 371 372 i2c0: i2c@ff150000 { 373 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 374 reg = <0x0 0xff150000 0x0 0x1000>; 375 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 379 clock-names = "i2c", "pclk"; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&i2c0_xfer>; 382 status = "disabled"; 383 }; 384 385 i2c1: i2c@ff160000 { 386 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 387 reg = <0x0 0xff160000 0x0 0x1000>; 388 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 392 clock-names = "i2c", "pclk"; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&i2c1_xfer>; 395 status = "disabled"; 396 }; 397 398 i2c2: i2c@ff170000 { 399 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 400 reg = <0x0 0xff170000 0x0 0x1000>; 401 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 405 clock-names = "i2c", "pclk"; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&i2c2_xfer>; 408 status = "disabled"; 409 }; 410 411 i2c3: i2c@ff180000 { 412 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 413 reg = <0x0 0xff180000 0x0 0x1000>; 414 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 418 clock-names = "i2c", "pclk"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&i2c3_xfer>; 421 status = "disabled"; 422 }; 423 424 spi0: spi@ff190000 { 425 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 426 reg = <0x0 0xff190000 0x0 0x1000>; 427 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 431 clock-names = "spiclk", "apb_pclk"; 432 dmas = <&dmac 8>, <&dmac 9>; 433 dma-names = "tx", "rx"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 436 status = "disabled"; 437 }; 438 439 wdt: watchdog@ff1a0000 { 440 compatible = "snps,dw-wdt"; 441 reg = <0x0 0xff1a0000 0x0 0x100>; 442 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&cru PCLK_WDT>; 444 }; 445 446 pwm0: pwm@ff1b0000 { 447 compatible = "rockchip,rk3328-pwm"; 448 reg = <0x0 0xff1b0000 0x0 0x10>; 449 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 450 clock-names = "pwm", "pclk"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&pwm0_pin>; 453 #pwm-cells = <3>; 454 status = "disabled"; 455 }; 456 457 pwm1: pwm@ff1b0010 { 458 compatible = "rockchip,rk3328-pwm"; 459 reg = <0x0 0xff1b0010 0x0 0x10>; 460 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 461 clock-names = "pwm", "pclk"; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pwm1_pin>; 464 #pwm-cells = <3>; 465 status = "disabled"; 466 }; 467 468 pwm2: pwm@ff1b0020 { 469 compatible = "rockchip,rk3328-pwm"; 470 reg = <0x0 0xff1b0020 0x0 0x10>; 471 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 472 clock-names = "pwm", "pclk"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&pwm2_pin>; 475 #pwm-cells = <3>; 476 status = "disabled"; 477 }; 478 479 pwm3: pwm@ff1b0030 { 480 compatible = "rockchip,rk3328-pwm"; 481 reg = <0x0 0xff1b0030 0x0 0x10>; 482 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 484 clock-names = "pwm", "pclk"; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&pwmir_pin>; 487 #pwm-cells = <3>; 488 status = "disabled"; 489 }; 490 491 thermal-zones { 492 soc_thermal: soc-thermal { 493 polling-delay-passive = <20>; 494 polling-delay = <1000>; 495 sustainable-power = <1000>; 496 497 thermal-sensors = <&tsadc 0>; 498 499 trips { 500 threshold: trip-point0 { 501 temperature = <70000>; 502 hysteresis = <2000>; 503 type = "passive"; 504 }; 505 target: trip-point1 { 506 temperature = <85000>; 507 hysteresis = <2000>; 508 type = "passive"; 509 }; 510 soc_crit: soc-crit { 511 temperature = <95000>; 512 hysteresis = <2000>; 513 type = "critical"; 514 }; 515 }; 516 517 cooling-maps { 518 map0 { 519 trip = <&target>; 520 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 521 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 522 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 523 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 524 contribution = <4096>; 525 }; 526 }; 527 }; 528 529 }; 530 531 tsadc: tsadc@ff250000 { 532 compatible = "rockchip,rk3328-tsadc"; 533 reg = <0x0 0xff250000 0x0 0x100>; 534 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 535 assigned-clocks = <&cru SCLK_TSADC>; 536 assigned-clock-rates = <50000>; 537 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 538 clock-names = "tsadc", "apb_pclk"; 539 pinctrl-names = "init", "default", "sleep"; 540 pinctrl-0 = <&otp_gpio>; 541 pinctrl-1 = <&otp_out>; 542 pinctrl-2 = <&otp_gpio>; 543 resets = <&cru SRST_TSADC>; 544 reset-names = "tsadc-apb"; 545 rockchip,grf = <&grf>; 546 rockchip,hw-tshut-temp = <100000>; 547 #thermal-sensor-cells = <1>; 548 status = "disabled"; 549 }; 550 551 efuse: efuse@ff260000 { 552 compatible = "rockchip,rk3328-efuse"; 553 reg = <0x0 0xff260000 0x0 0x50>; 554 #address-cells = <1>; 555 #size-cells = <1>; 556 clocks = <&cru SCLK_EFUSE>; 557 clock-names = "pclk_efuse"; 558 rockchip,efuse-size = <0x20>; 559 560 /* Data cells */ 561 efuse_id: id@7 { 562 reg = <0x07 0x10>; 563 }; 564 cpu_leakage: cpu-leakage@17 { 565 reg = <0x17 0x1>; 566 }; 567 logic_leakage: logic-leakage@19 { 568 reg = <0x19 0x1>; 569 }; 570 efuse_cpu_version: cpu-version@1a { 571 reg = <0x1a 0x1>; 572 bits = <3 3>; 573 }; 574 }; 575 576 saradc: adc@ff280000 { 577 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 578 reg = <0x0 0xff280000 0x0 0x100>; 579 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 580 #io-channel-cells = <1>; 581 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 582 clock-names = "saradc", "apb_pclk"; 583 resets = <&cru SRST_SARADC_P>; 584 reset-names = "saradc-apb"; 585 status = "disabled"; 586 }; 587 588 gpu: gpu@ff300000 { 589 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 590 reg = <0x0 0xff300000 0x0 0x40000>; 591 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-names = "gp", 599 "gpmmu", 600 "pp", 601 "pp0", 602 "ppmmu0", 603 "pp1", 604 "ppmmu1"; 605 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 606 clock-names = "bus", "core"; 607 resets = <&cru SRST_GPU_A>; 608 }; 609 610 h265e_mmu: iommu@ff330200 { 611 compatible = "rockchip,iommu"; 612 reg = <0x0 0xff330200 0 0x100>; 613 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 614 interrupt-names = "h265e_mmu"; 615 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 616 clock-names = "aclk", "iface"; 617 #iommu-cells = <0>; 618 status = "disabled"; 619 }; 620 621 vepu_mmu: iommu@ff340800 { 622 compatible = "rockchip,iommu"; 623 reg = <0x0 0xff340800 0x0 0x40>; 624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 625 interrupt-names = "vepu_mmu"; 626 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 627 clock-names = "aclk", "iface"; 628 #iommu-cells = <0>; 629 status = "disabled"; 630 }; 631 632 vpu: video-codec@ff350000 { 633 compatible = "rockchip,rk3328-vpu"; 634 reg = <0x0 0xff350000 0x0 0x800>; 635 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "vdpu"; 637 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 638 clock-names = "aclk", "hclk"; 639 iommus = <&vpu_mmu>; 640 power-domains = <&power RK3328_PD_VPU>; 641 }; 642 643 vpu_mmu: iommu@ff350800 { 644 compatible = "rockchip,iommu"; 645 reg = <0x0 0xff350800 0x0 0x40>; 646 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 647 interrupt-names = "vpu_mmu"; 648 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 649 clock-names = "aclk", "iface"; 650 #iommu-cells = <0>; 651 power-domains = <&power RK3328_PD_VPU>; 652 }; 653 654 rkvdec_mmu: iommu@ff360480 { 655 compatible = "rockchip,iommu"; 656 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 657 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 658 interrupt-names = "rkvdec_mmu"; 659 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 660 clock-names = "aclk", "iface"; 661 #iommu-cells = <0>; 662 status = "disabled"; 663 }; 664 665 vop: vop@ff370000 { 666 compatible = "rockchip,rk3328-vop"; 667 reg = <0x0 0xff370000 0x0 0x3efc>; 668 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 670 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 671 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 672 reset-names = "axi", "ahb", "dclk"; 673 iommus = <&vop_mmu>; 674 status = "disabled"; 675 676 vop_out: port { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 680 vop_out_hdmi: endpoint@0 { 681 reg = <0>; 682 remote-endpoint = <&hdmi_in_vop>; 683 }; 684 }; 685 }; 686 687 vop_mmu: iommu@ff373f00 { 688 compatible = "rockchip,iommu"; 689 reg = <0x0 0xff373f00 0x0 0x100>; 690 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 691 interrupt-names = "vop_mmu"; 692 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 693 clock-names = "aclk", "iface"; 694 #iommu-cells = <0>; 695 status = "disabled"; 696 }; 697 698 hdmi: hdmi@ff3c0000 { 699 compatible = "rockchip,rk3328-dw-hdmi"; 700 reg = <0x0 0xff3c0000 0x0 0x20000>; 701 reg-io-width = <4>; 702 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&cru PCLK_HDMI>, 705 <&cru SCLK_HDMI_SFC>, 706 <&cru SCLK_RTC32K>; 707 clock-names = "iahb", 708 "isfr", 709 "cec"; 710 phys = <&hdmiphy>; 711 phy-names = "hdmi"; 712 pinctrl-names = "default"; 713 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 714 rockchip,grf = <&grf>; 715 #sound-dai-cells = <0>; 716 status = "disabled"; 717 718 ports { 719 hdmi_in: port { 720 hdmi_in_vop: endpoint { 721 remote-endpoint = <&vop_out_hdmi>; 722 }; 723 }; 724 }; 725 }; 726 727 codec: codec@ff410000 { 728 compatible = "rockchip,rk3328-codec"; 729 reg = <0x0 0xff410000 0x0 0x1000>; 730 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 731 clock-names = "pclk", "mclk"; 732 rockchip,grf = <&grf>; 733 #sound-dai-cells = <0>; 734 status = "disabled"; 735 }; 736 737 hdmiphy: phy@ff430000 { 738 compatible = "rockchip,rk3328-hdmi-phy"; 739 reg = <0x0 0xff430000 0x0 0x10000>; 740 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 742 clock-names = "sysclk", "refoclk", "refpclk"; 743 clock-output-names = "hdmi_phy"; 744 #clock-cells = <0>; 745 nvmem-cells = <&efuse_cpu_version>; 746 nvmem-cell-names = "cpu-version"; 747 #phy-cells = <0>; 748 status = "disabled"; 749 }; 750 751 cru: clock-controller@ff440000 { 752 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 753 reg = <0x0 0xff440000 0x0 0x1000>; 754 rockchip,grf = <&grf>; 755 #clock-cells = <1>; 756 #reset-cells = <1>; 757 assigned-clocks = 758 /* 759 * CPLL should run at 1200, but that is to high for 760 * the initial dividers of most of its children. 761 * We need set cpll child clk div first, 762 * and then set the cpll frequency. 763 */ 764 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 765 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 766 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 767 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 768 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 769 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 770 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 771 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 772 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 773 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 774 <&cru SCLK_WIFI>, <&cru ARMCLK>, 775 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 776 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 777 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 778 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 779 <&cru SCLK_RTC32K>; 780 assigned-clock-parents = 781 <&cru HDMIPHY>, <&cru PLL_APLL>, 782 <&cru PLL_GPLL>, <&xin24m>, 783 <&xin24m>, <&xin24m>; 784 assigned-clock-rates = 785 <0>, <61440000>, 786 <0>, <24000000>, 787 <24000000>, <24000000>, 788 <15000000>, <15000000>, 789 <100000000>, <100000000>, 790 <100000000>, <100000000>, 791 <50000000>, <100000000>, 792 <100000000>, <100000000>, 793 <50000000>, <50000000>, 794 <50000000>, <50000000>, 795 <24000000>, <600000000>, 796 <491520000>, <1200000000>, 797 <150000000>, <75000000>, 798 <75000000>, <150000000>, 799 <75000000>, <75000000>, 800 <32768>; 801 }; 802 803 usb2phy_grf: syscon@ff450000 { 804 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 805 "simple-mfd"; 806 reg = <0x0 0xff450000 0x0 0x10000>; 807 #address-cells = <1>; 808 #size-cells = <1>; 809 810 u2phy: usb2-phy@100 { 811 compatible = "rockchip,rk3328-usb2phy"; 812 reg = <0x100 0x10>; 813 clocks = <&xin24m>; 814 clock-names = "phyclk"; 815 clock-output-names = "usb480m_phy"; 816 #clock-cells = <0>; 817 assigned-clocks = <&cru USB480M>; 818 assigned-clock-parents = <&u2phy>; 819 status = "disabled"; 820 821 u2phy_otg: otg-port { 822 #phy-cells = <0>; 823 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "otg-bvalid", "otg-id", 827 "linestate"; 828 status = "disabled"; 829 }; 830 831 u2phy_host: host-port { 832 #phy-cells = <0>; 833 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "linestate"; 835 status = "disabled"; 836 }; 837 }; 838 }; 839 840 sdmmc: dwmmc@ff500000 { 841 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 842 reg = <0x0 0xff500000 0x0 0x4000>; 843 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 845 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 846 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 847 fifo-depth = <0x100>; 848 max-frequency = <150000000>; 849 status = "disabled"; 850 }; 851 852 sdio: dwmmc@ff510000 { 853 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 854 reg = <0x0 0xff510000 0x0 0x4000>; 855 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 857 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 858 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 859 fifo-depth = <0x100>; 860 max-frequency = <150000000>; 861 status = "disabled"; 862 }; 863 864 emmc: dwmmc@ff520000 { 865 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 866 reg = <0x0 0xff520000 0x0 0x4000>; 867 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 869 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 870 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 871 fifo-depth = <0x100>; 872 max-frequency = <150000000>; 873 status = "disabled"; 874 }; 875 876 gmac2io: ethernet@ff540000 { 877 compatible = "rockchip,rk3328-gmac"; 878 reg = <0x0 0xff540000 0x0 0x10000>; 879 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "macirq"; 881 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 882 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 883 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 884 <&cru PCLK_MAC2IO>; 885 clock-names = "stmmaceth", "mac_clk_rx", 886 "mac_clk_tx", "clk_mac_ref", 887 "clk_mac_refout", "aclk_mac", 888 "pclk_mac"; 889 resets = <&cru SRST_GMAC2IO_A>; 890 reset-names = "stmmaceth"; 891 rockchip,grf = <&grf>; 892 status = "disabled"; 893 }; 894 895 gmac2phy: ethernet@ff550000 { 896 compatible = "rockchip,rk3328-gmac"; 897 reg = <0x0 0xff550000 0x0 0x10000>; 898 rockchip,grf = <&grf>; 899 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "macirq"; 901 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 902 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 903 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 904 <&cru SCLK_MAC2PHY_OUT>; 905 clock-names = "stmmaceth", "mac_clk_rx", 906 "mac_clk_tx", "clk_mac_ref", 907 "aclk_mac", "pclk_mac", 908 "clk_macphy"; 909 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 910 reset-names = "stmmaceth", "mac-phy"; 911 phy-mode = "rmii"; 912 phy-handle = <&phy>; 913 status = "disabled"; 914 915 mdio { 916 compatible = "snps,dwmac-mdio"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 920 phy: phy@0 { 921 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 922 reg = <0>; 923 clocks = <&cru SCLK_MAC2PHY_OUT>; 924 resets = <&cru SRST_MACPHY>; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 927 phy-is-integrated; 928 }; 929 }; 930 }; 931 932 usb20_otg: usb@ff580000 { 933 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 934 "snps,dwc2"; 935 reg = <0x0 0xff580000 0x0 0x40000>; 936 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&cru HCLK_OTG>; 938 clock-names = "otg"; 939 dr_mode = "otg"; 940 g-np-tx-fifo-size = <16>; 941 g-rx-fifo-size = <280>; 942 g-tx-fifo-size = <256 128 128 64 32 16>; 943 g-use-dma; 944 phys = <&u2phy_otg>; 945 phy-names = "usb2-phy"; 946 status = "disabled"; 947 }; 948 949 usb_host0_ehci: usb@ff5c0000 { 950 compatible = "generic-ehci"; 951 reg = <0x0 0xff5c0000 0x0 0x10000>; 952 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&cru HCLK_HOST0>, <&u2phy>; 954 clock-names = "usbhost", "utmi"; 955 phys = <&u2phy_host>; 956 phy-names = "usb"; 957 status = "disabled"; 958 }; 959 960 usb_host0_ohci: usb@ff5d0000 { 961 compatible = "generic-ohci"; 962 reg = <0x0 0xff5d0000 0x0 0x10000>; 963 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&cru HCLK_HOST0>, <&u2phy>; 965 clock-names = "usbhost", "utmi"; 966 phys = <&u2phy_host>; 967 phy-names = "usb"; 968 status = "disabled"; 969 }; 970 971 gic: interrupt-controller@ff811000 { 972 compatible = "arm,gic-400"; 973 #interrupt-cells = <3>; 974 #address-cells = <0>; 975 interrupt-controller; 976 reg = <0x0 0xff811000 0 0x1000>, 977 <0x0 0xff812000 0 0x2000>, 978 <0x0 0xff814000 0 0x2000>, 979 <0x0 0xff816000 0 0x2000>; 980 interrupts = <GIC_PPI 9 981 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 982 }; 983 984 pinctrl: pinctrl { 985 compatible = "rockchip,rk3328-pinctrl"; 986 rockchip,grf = <&grf>; 987 #address-cells = <2>; 988 #size-cells = <2>; 989 ranges; 990 991 gpio0: gpio0@ff210000 { 992 compatible = "rockchip,gpio-bank"; 993 reg = <0x0 0xff210000 0x0 0x100>; 994 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&cru PCLK_GPIO0>; 996 997 gpio-controller; 998 #gpio-cells = <2>; 999 1000 interrupt-controller; 1001 #interrupt-cells = <2>; 1002 }; 1003 1004 gpio1: gpio1@ff220000 { 1005 compatible = "rockchip,gpio-bank"; 1006 reg = <0x0 0xff220000 0x0 0x100>; 1007 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&cru PCLK_GPIO1>; 1009 1010 gpio-controller; 1011 #gpio-cells = <2>; 1012 1013 interrupt-controller; 1014 #interrupt-cells = <2>; 1015 }; 1016 1017 gpio2: gpio2@ff230000 { 1018 compatible = "rockchip,gpio-bank"; 1019 reg = <0x0 0xff230000 0x0 0x100>; 1020 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&cru PCLK_GPIO2>; 1022 1023 gpio-controller; 1024 #gpio-cells = <2>; 1025 1026 interrupt-controller; 1027 #interrupt-cells = <2>; 1028 }; 1029 1030 gpio3: gpio3@ff240000 { 1031 compatible = "rockchip,gpio-bank"; 1032 reg = <0x0 0xff240000 0x0 0x100>; 1033 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cru PCLK_GPIO3>; 1035 1036 gpio-controller; 1037 #gpio-cells = <2>; 1038 1039 interrupt-controller; 1040 #interrupt-cells = <2>; 1041 }; 1042 1043 pcfg_pull_up: pcfg-pull-up { 1044 bias-pull-up; 1045 }; 1046 1047 pcfg_pull_down: pcfg-pull-down { 1048 bias-pull-down; 1049 }; 1050 1051 pcfg_pull_none: pcfg-pull-none { 1052 bias-disable; 1053 }; 1054 1055 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1056 bias-disable; 1057 drive-strength = <2>; 1058 }; 1059 1060 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1061 bias-pull-up; 1062 drive-strength = <2>; 1063 }; 1064 1065 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1066 bias-pull-up; 1067 drive-strength = <4>; 1068 }; 1069 1070 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1071 bias-disable; 1072 drive-strength = <4>; 1073 }; 1074 1075 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1076 bias-pull-down; 1077 drive-strength = <4>; 1078 }; 1079 1080 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1081 bias-disable; 1082 drive-strength = <8>; 1083 }; 1084 1085 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1086 bias-pull-up; 1087 drive-strength = <8>; 1088 }; 1089 1090 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1091 bias-disable; 1092 drive-strength = <12>; 1093 }; 1094 1095 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1096 bias-pull-up; 1097 drive-strength = <12>; 1098 }; 1099 1100 pcfg_output_high: pcfg-output-high { 1101 output-high; 1102 }; 1103 1104 pcfg_output_low: pcfg-output-low { 1105 output-low; 1106 }; 1107 1108 pcfg_input_high: pcfg-input-high { 1109 bias-pull-up; 1110 input-enable; 1111 }; 1112 1113 pcfg_input: pcfg-input { 1114 input-enable; 1115 }; 1116 1117 i2c0 { 1118 i2c0_xfer: i2c0-xfer { 1119 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1120 <2 RK_PD1 1 &pcfg_pull_none>; 1121 }; 1122 }; 1123 1124 i2c1 { 1125 i2c1_xfer: i2c1-xfer { 1126 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1127 <2 RK_PA5 2 &pcfg_pull_none>; 1128 }; 1129 }; 1130 1131 i2c2 { 1132 i2c2_xfer: i2c2-xfer { 1133 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1134 <2 RK_PB6 1 &pcfg_pull_none>; 1135 }; 1136 }; 1137 1138 i2c3 { 1139 i2c3_xfer: i2c3-xfer { 1140 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1141 <0 RK_PA6 2 &pcfg_pull_none>; 1142 }; 1143 i2c3_gpio: i2c3-gpio { 1144 rockchip,pins = 1145 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1146 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1147 }; 1148 }; 1149 1150 hdmi_i2c { 1151 hdmii2c_xfer: hdmii2c-xfer { 1152 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1153 <0 RK_PA6 1 &pcfg_pull_none>; 1154 }; 1155 }; 1156 1157 pdm-0 { 1158 pdmm0_clk: pdmm0-clk { 1159 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1160 }; 1161 1162 pdmm0_fsync: pdmm0-fsync { 1163 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1164 }; 1165 1166 pdmm0_sdi0: pdmm0-sdi0 { 1167 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1168 }; 1169 1170 pdmm0_sdi1: pdmm0-sdi1 { 1171 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1172 }; 1173 1174 pdmm0_sdi2: pdmm0-sdi2 { 1175 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1176 }; 1177 1178 pdmm0_sdi3: pdmm0-sdi3 { 1179 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1180 }; 1181 1182 pdmm0_clk_sleep: pdmm0-clk-sleep { 1183 rockchip,pins = 1184 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1185 }; 1186 1187 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1188 rockchip,pins = 1189 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1190 }; 1191 1192 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1193 rockchip,pins = 1194 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1195 }; 1196 1197 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1198 rockchip,pins = 1199 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1200 }; 1201 1202 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1203 rockchip,pins = 1204 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1205 }; 1206 1207 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1208 rockchip,pins = 1209 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1210 }; 1211 }; 1212 1213 tsadc { 1214 otp_gpio: otp-gpio { 1215 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1216 }; 1217 1218 otp_out: otp-out { 1219 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1220 }; 1221 }; 1222 1223 uart0 { 1224 uart0_xfer: uart0-xfer { 1225 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1226 <1 RK_PB0 1 &pcfg_pull_none>; 1227 }; 1228 1229 uart0_cts: uart0-cts { 1230 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1231 }; 1232 1233 uart0_rts: uart0-rts { 1234 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1235 }; 1236 1237 uart0_rts_gpio: uart0-rts-gpio { 1238 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1239 }; 1240 }; 1241 1242 uart1 { 1243 uart1_xfer: uart1-xfer { 1244 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1245 <3 RK_PA6 4 &pcfg_pull_none>; 1246 }; 1247 1248 uart1_cts: uart1-cts { 1249 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1250 }; 1251 1252 uart1_rts: uart1-rts { 1253 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1254 }; 1255 1256 uart1_rts_gpio: uart1-rts-gpio { 1257 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1258 }; 1259 }; 1260 1261 uart2-0 { 1262 uart2m0_xfer: uart2m0-xfer { 1263 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1264 <1 RK_PA1 2 &pcfg_pull_none>; 1265 }; 1266 }; 1267 1268 uart2-1 { 1269 uart2m1_xfer: uart2m1-xfer { 1270 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1271 <2 RK_PA1 1 &pcfg_pull_none>; 1272 }; 1273 }; 1274 1275 spi0-0 { 1276 spi0m0_clk: spi0m0-clk { 1277 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1278 }; 1279 1280 spi0m0_cs0: spi0m0-cs0 { 1281 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1282 }; 1283 1284 spi0m0_tx: spi0m0-tx { 1285 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1286 }; 1287 1288 spi0m0_rx: spi0m0-rx { 1289 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1290 }; 1291 1292 spi0m0_cs1: spi0m0-cs1 { 1293 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1294 }; 1295 }; 1296 1297 spi0-1 { 1298 spi0m1_clk: spi0m1-clk { 1299 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1300 }; 1301 1302 spi0m1_cs0: spi0m1-cs0 { 1303 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1304 }; 1305 1306 spi0m1_tx: spi0m1-tx { 1307 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1308 }; 1309 1310 spi0m1_rx: spi0m1-rx { 1311 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1312 }; 1313 1314 spi0m1_cs1: spi0m1-cs1 { 1315 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1316 }; 1317 }; 1318 1319 spi0-2 { 1320 spi0m2_clk: spi0m2-clk { 1321 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1322 }; 1323 1324 spi0m2_cs0: spi0m2-cs0 { 1325 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1326 }; 1327 1328 spi0m2_tx: spi0m2-tx { 1329 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1330 }; 1331 1332 spi0m2_rx: spi0m2-rx { 1333 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1334 }; 1335 }; 1336 1337 i2s1 { 1338 i2s1_mclk: i2s1-mclk { 1339 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1340 }; 1341 1342 i2s1_sclk: i2s1-sclk { 1343 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1344 }; 1345 1346 i2s1_lrckrx: i2s1-lrckrx { 1347 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1348 }; 1349 1350 i2s1_lrcktx: i2s1-lrcktx { 1351 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1352 }; 1353 1354 i2s1_sdi: i2s1-sdi { 1355 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1356 }; 1357 1358 i2s1_sdo: i2s1-sdo { 1359 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1360 }; 1361 1362 i2s1_sdio1: i2s1-sdio1 { 1363 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1364 }; 1365 1366 i2s1_sdio2: i2s1-sdio2 { 1367 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1368 }; 1369 1370 i2s1_sdio3: i2s1-sdio3 { 1371 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1372 }; 1373 1374 i2s1_sleep: i2s1-sleep { 1375 rockchip,pins = 1376 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1377 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1378 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1379 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1380 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1381 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1382 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1383 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1384 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1385 }; 1386 }; 1387 1388 i2s2-0 { 1389 i2s2m0_mclk: i2s2m0-mclk { 1390 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1391 }; 1392 1393 i2s2m0_sclk: i2s2m0-sclk { 1394 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1395 }; 1396 1397 i2s2m0_lrckrx: i2s2m0-lrckrx { 1398 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1399 }; 1400 1401 i2s2m0_lrcktx: i2s2m0-lrcktx { 1402 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1403 }; 1404 1405 i2s2m0_sdi: i2s2m0-sdi { 1406 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1407 }; 1408 1409 i2s2m0_sdo: i2s2m0-sdo { 1410 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1411 }; 1412 1413 i2s2m0_sleep: i2s2m0-sleep { 1414 rockchip,pins = 1415 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1416 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1417 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1418 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1419 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1420 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1421 }; 1422 }; 1423 1424 i2s2-1 { 1425 i2s2m1_mclk: i2s2m1-mclk { 1426 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1427 }; 1428 1429 i2s2m1_sclk: i2s2m1-sclk { 1430 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1431 }; 1432 1433 i2s2m1_lrckrx: i2sm1-lrckrx { 1434 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1435 }; 1436 1437 i2s2m1_lrcktx: i2s2m1-lrcktx { 1438 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1439 }; 1440 1441 i2s2m1_sdi: i2s2m1-sdi { 1442 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1443 }; 1444 1445 i2s2m1_sdo: i2s2m1-sdo { 1446 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1447 }; 1448 1449 i2s2m1_sleep: i2s2m1-sleep { 1450 rockchip,pins = 1451 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1452 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1453 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1454 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1455 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1456 }; 1457 }; 1458 1459 spdif-0 { 1460 spdifm0_tx: spdifm0-tx { 1461 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1462 }; 1463 }; 1464 1465 spdif-1 { 1466 spdifm1_tx: spdifm1-tx { 1467 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1468 }; 1469 }; 1470 1471 spdif-2 { 1472 spdifm2_tx: spdifm2-tx { 1473 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1474 }; 1475 }; 1476 1477 sdmmc0-0 { 1478 sdmmc0m0_pwren: sdmmc0m0-pwren { 1479 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1480 }; 1481 1482 sdmmc0m0_gpio: sdmmc0m0-gpio { 1483 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1484 }; 1485 }; 1486 1487 sdmmc0-1 { 1488 sdmmc0m1_pwren: sdmmc0m1-pwren { 1489 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1490 }; 1491 1492 sdmmc0m1_gpio: sdmmc0m1-gpio { 1493 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1494 }; 1495 }; 1496 1497 sdmmc0 { 1498 sdmmc0_clk: sdmmc0-clk { 1499 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1500 }; 1501 1502 sdmmc0_cmd: sdmmc0-cmd { 1503 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1504 }; 1505 1506 sdmmc0_dectn: sdmmc0-dectn { 1507 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1508 }; 1509 1510 sdmmc0_wrprt: sdmmc0-wrprt { 1511 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1512 }; 1513 1514 sdmmc0_bus1: sdmmc0-bus1 { 1515 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1516 }; 1517 1518 sdmmc0_bus4: sdmmc0-bus4 { 1519 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1520 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1521 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1522 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1523 }; 1524 1525 sdmmc0_gpio: sdmmc0-gpio { 1526 rockchip,pins = 1527 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1528 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1529 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1530 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1531 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1532 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1533 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1534 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1535 }; 1536 }; 1537 1538 sdmmc0ext { 1539 sdmmc0ext_clk: sdmmc0ext-clk { 1540 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1541 }; 1542 1543 sdmmc0ext_cmd: sdmmc0ext-cmd { 1544 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1545 }; 1546 1547 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1548 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1549 }; 1550 1551 sdmmc0ext_dectn: sdmmc0ext-dectn { 1552 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1553 }; 1554 1555 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1556 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1557 }; 1558 1559 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1560 rockchip,pins = 1561 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1562 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1563 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1564 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1565 }; 1566 1567 sdmmc0ext_gpio: sdmmc0ext-gpio { 1568 rockchip,pins = 1569 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1570 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1571 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1572 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1573 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1574 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1575 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1576 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1577 }; 1578 }; 1579 1580 sdmmc1 { 1581 sdmmc1_clk: sdmmc1-clk { 1582 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1583 }; 1584 1585 sdmmc1_cmd: sdmmc1-cmd { 1586 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1587 }; 1588 1589 sdmmc1_pwren: sdmmc1-pwren { 1590 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1591 }; 1592 1593 sdmmc1_wrprt: sdmmc1-wrprt { 1594 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1595 }; 1596 1597 sdmmc1_dectn: sdmmc1-dectn { 1598 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1599 }; 1600 1601 sdmmc1_bus1: sdmmc1-bus1 { 1602 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1603 }; 1604 1605 sdmmc1_bus4: sdmmc1-bus4 { 1606 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1607 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1608 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1609 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1610 }; 1611 1612 sdmmc1_gpio: sdmmc1-gpio { 1613 rockchip,pins = 1614 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1615 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1616 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1617 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1618 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1619 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1620 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1621 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1622 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1623 }; 1624 }; 1625 1626 emmc { 1627 emmc_clk: emmc-clk { 1628 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1629 }; 1630 1631 emmc_cmd: emmc-cmd { 1632 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1633 }; 1634 1635 emmc_pwren: emmc-pwren { 1636 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1637 }; 1638 1639 emmc_rstnout: emmc-rstnout { 1640 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1641 }; 1642 1643 emmc_bus1: emmc-bus1 { 1644 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1645 }; 1646 1647 emmc_bus4: emmc-bus4 { 1648 rockchip,pins = 1649 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1650 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1651 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1652 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1653 }; 1654 1655 emmc_bus8: emmc-bus8 { 1656 rockchip,pins = 1657 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1658 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1659 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1660 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1661 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1662 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1663 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1664 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1665 }; 1666 }; 1667 1668 pwm0 { 1669 pwm0_pin: pwm0-pin { 1670 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1671 }; 1672 }; 1673 1674 pwm1 { 1675 pwm1_pin: pwm1-pin { 1676 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1677 }; 1678 }; 1679 1680 pwm2 { 1681 pwm2_pin: pwm2-pin { 1682 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1683 }; 1684 }; 1685 1686 pwmir { 1687 pwmir_pin: pwmir-pin { 1688 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1689 }; 1690 }; 1691 1692 gmac-1 { 1693 rgmiim1_pins: rgmiim1-pins { 1694 rockchip,pins = 1695 /* mac_txclk */ 1696 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1697 /* mac_rxclk */ 1698 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1699 /* mac_mdio */ 1700 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1701 /* mac_txen */ 1702 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1703 /* mac_clk */ 1704 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1705 /* mac_rxdv */ 1706 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1707 /* mac_mdc */ 1708 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1709 /* mac_rxd1 */ 1710 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1711 /* mac_rxd0 */ 1712 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1713 /* mac_txd1 */ 1714 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1715 /* mac_txd0 */ 1716 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1717 /* mac_rxd3 */ 1718 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1719 /* mac_rxd2 */ 1720 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1721 /* mac_txd3 */ 1722 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1723 /* mac_txd2 */ 1724 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1725 1726 /* mac_txclk */ 1727 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1728 /* mac_txen */ 1729 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1730 /* mac_clk */ 1731 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1732 /* mac_txd1 */ 1733 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1734 /* mac_txd0 */ 1735 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1736 /* mac_txd3 */ 1737 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1738 /* mac_txd2 */ 1739 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1740 }; 1741 1742 rmiim1_pins: rmiim1-pins { 1743 rockchip,pins = 1744 /* mac_mdio */ 1745 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1746 /* mac_txen */ 1747 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1748 /* mac_clk */ 1749 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1750 /* mac_rxer */ 1751 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1752 /* mac_rxdv */ 1753 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1754 /* mac_mdc */ 1755 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1756 /* mac_rxd1 */ 1757 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1758 /* mac_rxd0 */ 1759 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1760 /* mac_txd1 */ 1761 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1762 /* mac_txd0 */ 1763 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1764 1765 /* mac_mdio */ 1766 <0 RK_PB3 1 &pcfg_pull_none>, 1767 /* mac_txen */ 1768 <0 RK_PB4 1 &pcfg_pull_none>, 1769 /* mac_clk */ 1770 <0 RK_PD0 1 &pcfg_pull_none>, 1771 /* mac_mdc */ 1772 <0 RK_PC3 1 &pcfg_pull_none>, 1773 /* mac_txd1 */ 1774 <0 RK_PC0 1 &pcfg_pull_none>, 1775 /* mac_txd0 */ 1776 <0 RK_PC1 1 &pcfg_pull_none>; 1777 }; 1778 }; 1779 1780 gmac2phy { 1781 fephyled_speed100: fephyled-speed100 { 1782 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1783 }; 1784 1785 fephyled_speed10: fephyled-speed10 { 1786 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1787 }; 1788 1789 fephyled_duplex: fephyled-duplex { 1790 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1791 }; 1792 1793 fephyled_rxm0: fephyled-rxm0 { 1794 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1795 }; 1796 1797 fephyled_txm0: fephyled-txm0 { 1798 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1799 }; 1800 1801 fephyled_linkm0: fephyled-linkm0 { 1802 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1803 }; 1804 1805 fephyled_rxm1: fephyled-rxm1 { 1806 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1807 }; 1808 1809 fephyled_txm1: fephyled-txm1 { 1810 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1811 }; 1812 1813 fephyled_linkm1: fephyled-linkm1 { 1814 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1815 }; 1816 }; 1817 1818 tsadc_pin { 1819 tsadc_int: tsadc-int { 1820 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1821 }; 1822 tsadc_gpio: tsadc-gpio { 1823 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1824 }; 1825 }; 1826 1827 hdmi_pin { 1828 hdmi_cec: hdmi-cec { 1829 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1830 }; 1831 1832 hdmi_hpd: hdmi-hpd { 1833 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1834 }; 1835 }; 1836 1837 cif-0 { 1838 dvp_d2d9_m0:dvp-d2d9-m0 { 1839 rockchip,pins = 1840 /* cif_d0 */ 1841 <3 RK_PA4 2 &pcfg_pull_none>, 1842 /* cif_d1 */ 1843 <3 RK_PA5 2 &pcfg_pull_none>, 1844 /* cif_d2 */ 1845 <3 RK_PA6 2 &pcfg_pull_none>, 1846 /* cif_d3 */ 1847 <3 RK_PA7 2 &pcfg_pull_none>, 1848 /* cif_d4 */ 1849 <3 RK_PB0 2 &pcfg_pull_none>, 1850 /* cif_d5m0 */ 1851 <3 RK_PB1 2 &pcfg_pull_none>, 1852 /* cif_d6m0 */ 1853 <3 RK_PB2 2 &pcfg_pull_none>, 1854 /* cif_d7m0 */ 1855 <3 RK_PB3 2 &pcfg_pull_none>, 1856 /* cif_href */ 1857 <3 RK_PA1 2 &pcfg_pull_none>, 1858 /* cif_vsync */ 1859 <3 RK_PA0 2 &pcfg_pull_none>, 1860 /* cif_clkoutm0 */ 1861 <3 RK_PA3 2 &pcfg_pull_none>, 1862 /* cif_clkin */ 1863 <3 RK_PA2 2 &pcfg_pull_none>; 1864 }; 1865 }; 1866 1867 cif-1 { 1868 dvp_d2d9_m1:dvp-d2d9-m1 { 1869 rockchip,pins = 1870 /* cif_d0 */ 1871 <3 RK_PA4 2 &pcfg_pull_none>, 1872 /* cif_d1 */ 1873 <3 RK_PA5 2 &pcfg_pull_none>, 1874 /* cif_d2 */ 1875 <3 RK_PA6 2 &pcfg_pull_none>, 1876 /* cif_d3 */ 1877 <3 RK_PA7 2 &pcfg_pull_none>, 1878 /* cif_d4 */ 1879 <3 RK_PB0 2 &pcfg_pull_none>, 1880 /* cif_d5m1 */ 1881 <2 RK_PC0 4 &pcfg_pull_none>, 1882 /* cif_d6m1 */ 1883 <2 RK_PC1 4 &pcfg_pull_none>, 1884 /* cif_d7m1 */ 1885 <2 RK_PC2 4 &pcfg_pull_none>, 1886 /* cif_href */ 1887 <3 RK_PA1 2 &pcfg_pull_none>, 1888 /* cif_vsync */ 1889 <3 RK_PA0 2 &pcfg_pull_none>, 1890 /* cif_clkoutm1 */ 1891 <2 RK_PB7 4 &pcfg_pull_none>, 1892 /* cif_clkin */ 1893 <3 RK_PA2 2 &pcfg_pull_none>; 1894 }; 1895 }; 1896 }; 1897}; 1898