1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 amba { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 dmac_bus: dma-controller@ff6d0000 { 207 compatible = "arm,pl330", "arm,primecell"; 208 reg = <0x0 0xff6d0000 0x0 0x4000>; 209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 211 #dma-cells = <1>; 212 clocks = <&cru ACLK_DMAC0_PERILP>; 213 clock-names = "apb_pclk"; 214 }; 215 216 dmac_peri: dma-controller@ff6e0000 { 217 compatible = "arm,pl330", "arm,primecell"; 218 reg = <0x0 0xff6e0000 0x0 0x4000>; 219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 221 #dma-cells = <1>; 222 clocks = <&cru ACLK_DMAC1_PERILP>; 223 clock-names = "apb_pclk"; 224 }; 225 }; 226 227 pcie0: pcie@f8000000 { 228 compatible = "rockchip,rk3399-pcie"; 229 reg = <0x0 0xf8000000 0x0 0x2000000>, 230 <0x0 0xfd000000 0x0 0x1000000>; 231 reg-names = "axi-base", "apb-base"; 232 #address-cells = <3>; 233 #size-cells = <2>; 234 #interrupt-cells = <1>; 235 aspm-no-l0s; 236 bus-range = <0x0 0x1f>; 237 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 238 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 239 clock-names = "aclk", "aclk-perf", 240 "hclk", "pm"; 241 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 243 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 244 interrupt-names = "sys", "legacy", "client"; 245 interrupt-map-mask = <0 0 0 7>; 246 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 247 <0 0 0 2 &pcie0_intc 1>, 248 <0 0 0 3 &pcie0_intc 2>, 249 <0 0 0 4 &pcie0_intc 3>; 250 linux,pci-domain = <0>; 251 max-link-speed = <1>; 252 msi-map = <0x0 &its 0x0 0x1000>; 253 phys = <&pcie_phy 0>, <&pcie_phy 1>, 254 <&pcie_phy 2>, <&pcie_phy 3>; 255 phy-names = "pcie-phy-0", "pcie-phy-1", 256 "pcie-phy-2", "pcie-phy-3"; 257 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 258 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 259 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 260 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 261 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 262 <&cru SRST_A_PCIE>; 263 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 264 "pm", "pclk", "aclk"; 265 status = "disabled"; 266 267 pcie0_intc: interrupt-controller { 268 interrupt-controller; 269 #address-cells = <0>; 270 #interrupt-cells = <1>; 271 }; 272 }; 273 274 gmac: ethernet@fe300000 { 275 compatible = "rockchip,rk3399-gmac"; 276 reg = <0x0 0xfe300000 0x0 0x10000>; 277 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 278 interrupt-names = "macirq"; 279 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 280 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 281 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 282 <&cru PCLK_GMAC>; 283 clock-names = "stmmaceth", "mac_clk_rx", 284 "mac_clk_tx", "clk_mac_ref", 285 "clk_mac_refout", "aclk_mac", 286 "pclk_mac"; 287 power-domains = <&power RK3399_PD_GMAC>; 288 resets = <&cru SRST_A_GMAC>; 289 reset-names = "stmmaceth"; 290 rockchip,grf = <&grf>; 291 status = "disabled"; 292 }; 293 294 sdio0: dwmmc@fe310000 { 295 compatible = "rockchip,rk3399-dw-mshc", 296 "rockchip,rk3288-dw-mshc"; 297 reg = <0x0 0xfe310000 0x0 0x4000>; 298 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 299 max-frequency = <150000000>; 300 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 301 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 302 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 303 fifo-depth = <0x100>; 304 power-domains = <&power RK3399_PD_SDIOAUDIO>; 305 resets = <&cru SRST_SDIO0>; 306 reset-names = "reset"; 307 status = "disabled"; 308 }; 309 310 sdmmc: dwmmc@fe320000 { 311 compatible = "rockchip,rk3399-dw-mshc", 312 "rockchip,rk3288-dw-mshc"; 313 reg = <0x0 0xfe320000 0x0 0x4000>; 314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 315 max-frequency = <150000000>; 316 assigned-clocks = <&cru HCLK_SD>; 317 assigned-clock-rates = <200000000>; 318 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 319 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 320 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 321 fifo-depth = <0x100>; 322 power-domains = <&power RK3399_PD_SD>; 323 resets = <&cru SRST_SDMMC>; 324 reset-names = "reset"; 325 status = "disabled"; 326 }; 327 328 sdhci: sdhci@fe330000 { 329 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 330 reg = <0x0 0xfe330000 0x0 0x10000>; 331 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 332 arasan,soc-ctl-syscon = <&grf>; 333 assigned-clocks = <&cru SCLK_EMMC>; 334 assigned-clock-rates = <200000000>; 335 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 336 clock-names = "clk_xin", "clk_ahb"; 337 clock-output-names = "emmc_cardclock"; 338 #clock-cells = <0>; 339 phys = <&emmc_phy>; 340 phy-names = "phy_arasan"; 341 power-domains = <&power RK3399_PD_EMMC>; 342 disable-cqe-dcmd; 343 status = "disabled"; 344 }; 345 346 usb_host0_ehci: usb@fe380000 { 347 compatible = "generic-ehci"; 348 reg = <0x0 0xfe380000 0x0 0x20000>; 349 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 350 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 351 <&u2phy0>; 352 clock-names = "usbhost", "arbiter", 353 "utmi"; 354 phys = <&u2phy0_host>; 355 phy-names = "usb"; 356 status = "disabled"; 357 }; 358 359 usb_host0_ohci: usb@fe3a0000 { 360 compatible = "generic-ohci"; 361 reg = <0x0 0xfe3a0000 0x0 0x20000>; 362 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 363 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 364 <&u2phy0>; 365 clock-names = "usbhost", "arbiter", 366 "utmi"; 367 phys = <&u2phy0_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 usb_host1_ehci: usb@fe3c0000 { 373 compatible = "generic-ehci"; 374 reg = <0x0 0xfe3c0000 0x0 0x20000>; 375 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 376 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 377 <&u2phy1>; 378 clock-names = "usbhost", "arbiter", 379 "utmi"; 380 phys = <&u2phy1_host>; 381 phy-names = "usb"; 382 status = "disabled"; 383 }; 384 385 usb_host1_ohci: usb@fe3e0000 { 386 compatible = "generic-ohci"; 387 reg = <0x0 0xfe3e0000 0x0 0x20000>; 388 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 389 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 390 <&u2phy1>; 391 clock-names = "usbhost", "arbiter", 392 "utmi"; 393 phys = <&u2phy1_host>; 394 phy-names = "usb"; 395 status = "disabled"; 396 }; 397 398 usbdrd3_0: usb@fe800000 { 399 compatible = "rockchip,rk3399-dwc3"; 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 404 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 405 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 406 clock-names = "ref_clk", "suspend_clk", 407 "bus_clk", "aclk_usb3_rksoc_axi_perf", 408 "aclk_usb3", "grf_clk"; 409 resets = <&cru SRST_A_USB3_OTG0>; 410 reset-names = "usb3-otg"; 411 status = "disabled"; 412 413 usbdrd_dwc3_0: dwc3 { 414 compatible = "snps,dwc3"; 415 reg = <0x0 0xfe800000 0x0 0x100000>; 416 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 417 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 418 <&cru SCLK_USB3OTG0_SUSPEND>; 419 clock-names = "ref", "bus_early", "suspend"; 420 dr_mode = "otg"; 421 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 422 phy-names = "usb2-phy", "usb3-phy"; 423 phy_type = "utmi_wide"; 424 snps,dis_enblslpm_quirk; 425 snps,dis-u2-freeclk-exists-quirk; 426 snps,dis_u2_susphy_quirk; 427 snps,dis-del-phy-power-chg-quirk; 428 snps,dis-tx-ipgap-linecheck-quirk; 429 power-domains = <&power RK3399_PD_USB3>; 430 status = "disabled"; 431 }; 432 }; 433 434 usbdrd3_1: usb@fe900000 { 435 compatible = "rockchip,rk3399-dwc3"; 436 #address-cells = <2>; 437 #size-cells = <2>; 438 ranges; 439 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 440 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 441 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 442 clock-names = "ref_clk", "suspend_clk", 443 "bus_clk", "aclk_usb3_rksoc_axi_perf", 444 "aclk_usb3", "grf_clk"; 445 resets = <&cru SRST_A_USB3_OTG1>; 446 reset-names = "usb3-otg"; 447 status = "disabled"; 448 449 usbdrd_dwc3_1: dwc3 { 450 compatible = "snps,dwc3"; 451 reg = <0x0 0xfe900000 0x0 0x100000>; 452 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 453 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 454 <&cru SCLK_USB3OTG1_SUSPEND>; 455 clock-names = "ref", "bus_early", "suspend"; 456 dr_mode = "otg"; 457 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 458 phy-names = "usb2-phy", "usb3-phy"; 459 phy_type = "utmi_wide"; 460 snps,dis_enblslpm_quirk; 461 snps,dis-u2-freeclk-exists-quirk; 462 snps,dis_u2_susphy_quirk; 463 snps,dis-del-phy-power-chg-quirk; 464 snps,dis-tx-ipgap-linecheck-quirk; 465 power-domains = <&power RK3399_PD_USB3>; 466 status = "disabled"; 467 }; 468 }; 469 470 cdn_dp: dp@fec00000 { 471 compatible = "rockchip,rk3399-cdn-dp"; 472 reg = <0x0 0xfec00000 0x0 0x100000>; 473 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 474 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 475 assigned-clock-rates = <100000000>, <200000000>; 476 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 477 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 478 clock-names = "core-clk", "pclk", "spdif", "grf"; 479 phys = <&tcphy0_dp>, <&tcphy1_dp>; 480 power-domains = <&power RK3399_PD_HDCP>; 481 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 482 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 483 reset-names = "spdif", "dptx", "apb", "core"; 484 rockchip,grf = <&grf>; 485 #sound-dai-cells = <1>; 486 status = "disabled"; 487 488 ports { 489 dp_in: port { 490 #address-cells = <1>; 491 #size-cells = <0>; 492 493 dp_in_vopb: endpoint@0 { 494 reg = <0>; 495 remote-endpoint = <&vopb_out_dp>; 496 }; 497 498 dp_in_vopl: endpoint@1 { 499 reg = <1>; 500 remote-endpoint = <&vopl_out_dp>; 501 }; 502 }; 503 }; 504 }; 505 506 gic: interrupt-controller@fee00000 { 507 compatible = "arm,gic-v3"; 508 #interrupt-cells = <4>; 509 #address-cells = <2>; 510 #size-cells = <2>; 511 ranges; 512 interrupt-controller; 513 514 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 515 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 516 <0x0 0xfff00000 0 0x10000>, /* GICC */ 517 <0x0 0xfff10000 0 0x10000>, /* GICH */ 518 <0x0 0xfff20000 0 0x10000>; /* GICV */ 519 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 520 its: interrupt-controller@fee20000 { 521 compatible = "arm,gic-v3-its"; 522 msi-controller; 523 #msi-cells = <1>; 524 reg = <0x0 0xfee20000 0x0 0x20000>; 525 }; 526 527 ppi-partitions { 528 ppi_cluster0: interrupt-partition-0 { 529 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 530 }; 531 532 ppi_cluster1: interrupt-partition-1 { 533 affinity = <&cpu_b0 &cpu_b1>; 534 }; 535 }; 536 }; 537 538 saradc: saradc@ff100000 { 539 compatible = "rockchip,rk3399-saradc"; 540 reg = <0x0 0xff100000 0x0 0x100>; 541 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 542 #io-channel-cells = <1>; 543 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 544 clock-names = "saradc", "apb_pclk"; 545 resets = <&cru SRST_P_SARADC>; 546 reset-names = "saradc-apb"; 547 status = "disabled"; 548 }; 549 550 i2c1: i2c@ff110000 { 551 compatible = "rockchip,rk3399-i2c"; 552 reg = <0x0 0xff110000 0x0 0x1000>; 553 assigned-clocks = <&cru SCLK_I2C1>; 554 assigned-clock-rates = <200000000>; 555 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 556 clock-names = "i2c", "pclk"; 557 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&i2c1_xfer>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 status = "disabled"; 563 }; 564 565 i2c2: i2c@ff120000 { 566 compatible = "rockchip,rk3399-i2c"; 567 reg = <0x0 0xff120000 0x0 0x1000>; 568 assigned-clocks = <&cru SCLK_I2C2>; 569 assigned-clock-rates = <200000000>; 570 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 571 clock-names = "i2c", "pclk"; 572 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&i2c2_xfer>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 i2c3: i2c@ff130000 { 581 compatible = "rockchip,rk3399-i2c"; 582 reg = <0x0 0xff130000 0x0 0x1000>; 583 assigned-clocks = <&cru SCLK_I2C3>; 584 assigned-clock-rates = <200000000>; 585 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 586 clock-names = "i2c", "pclk"; 587 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&i2c3_xfer>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 595 i2c5: i2c@ff140000 { 596 compatible = "rockchip,rk3399-i2c"; 597 reg = <0x0 0xff140000 0x0 0x1000>; 598 assigned-clocks = <&cru SCLK_I2C5>; 599 assigned-clock-rates = <200000000>; 600 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 601 clock-names = "i2c", "pclk"; 602 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&i2c5_xfer>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 i2c6: i2c@ff150000 { 611 compatible = "rockchip,rk3399-i2c"; 612 reg = <0x0 0xff150000 0x0 0x1000>; 613 assigned-clocks = <&cru SCLK_I2C6>; 614 assigned-clock-rates = <200000000>; 615 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 616 clock-names = "i2c", "pclk"; 617 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&i2c6_xfer>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 status = "disabled"; 623 }; 624 625 i2c7: i2c@ff160000 { 626 compatible = "rockchip,rk3399-i2c"; 627 reg = <0x0 0xff160000 0x0 0x1000>; 628 assigned-clocks = <&cru SCLK_I2C7>; 629 assigned-clock-rates = <200000000>; 630 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 631 clock-names = "i2c", "pclk"; 632 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&i2c7_xfer>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 uart0: serial@ff180000 { 641 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 642 reg = <0x0 0xff180000 0x0 0x100>; 643 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 644 clock-names = "baudclk", "apb_pclk"; 645 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 646 reg-shift = <2>; 647 reg-io-width = <4>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&uart0_xfer>; 650 status = "disabled"; 651 }; 652 653 uart1: serial@ff190000 { 654 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 655 reg = <0x0 0xff190000 0x0 0x100>; 656 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 657 clock-names = "baudclk", "apb_pclk"; 658 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 659 reg-shift = <2>; 660 reg-io-width = <4>; 661 pinctrl-names = "default"; 662 pinctrl-0 = <&uart1_xfer>; 663 status = "disabled"; 664 }; 665 666 uart2: serial@ff1a0000 { 667 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 668 reg = <0x0 0xff1a0000 0x0 0x100>; 669 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 670 clock-names = "baudclk", "apb_pclk"; 671 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 672 reg-shift = <2>; 673 reg-io-width = <4>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&uart2c_xfer>; 676 status = "disabled"; 677 }; 678 679 uart3: serial@ff1b0000 { 680 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 681 reg = <0x0 0xff1b0000 0x0 0x100>; 682 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 683 clock-names = "baudclk", "apb_pclk"; 684 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 685 reg-shift = <2>; 686 reg-io-width = <4>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&uart3_xfer>; 689 status = "disabled"; 690 }; 691 692 spi0: spi@ff1c0000 { 693 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 694 reg = <0x0 0xff1c0000 0x0 0x1000>; 695 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 696 clock-names = "spiclk", "apb_pclk"; 697 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 698 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 699 dma-names = "tx", "rx"; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 spi1: spi@ff1d0000 { 708 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 709 reg = <0x0 0xff1d0000 0x0 0x1000>; 710 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 711 clock-names = "spiclk", "apb_pclk"; 712 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 713 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 714 dma-names = "tx", "rx"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 spi2: spi@ff1e0000 { 723 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 724 reg = <0x0 0xff1e0000 0x0 0x1000>; 725 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 726 clock-names = "spiclk", "apb_pclk"; 727 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 728 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 729 dma-names = "tx", "rx"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 spi4: spi@ff1f0000 { 738 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 739 reg = <0x0 0xff1f0000 0x0 0x1000>; 740 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 741 clock-names = "spiclk", "apb_pclk"; 742 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 743 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 744 dma-names = "tx", "rx"; 745 pinctrl-names = "default"; 746 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 status = "disabled"; 750 }; 751 752 spi5: spi@ff200000 { 753 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 754 reg = <0x0 0xff200000 0x0 0x1000>; 755 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 756 clock-names = "spiclk", "apb_pclk"; 757 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 758 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 759 dma-names = "tx", "rx"; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 762 power-domains = <&power RK3399_PD_SDIOAUDIO>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 thermal_zones: thermal-zones { 769 cpu_thermal: cpu { 770 polling-delay-passive = <100>; 771 polling-delay = <1000>; 772 773 thermal-sensors = <&tsadc 0>; 774 775 trips { 776 cpu_alert0: cpu_alert0 { 777 temperature = <70000>; 778 hysteresis = <2000>; 779 type = "passive"; 780 }; 781 cpu_alert1: cpu_alert1 { 782 temperature = <75000>; 783 hysteresis = <2000>; 784 type = "passive"; 785 }; 786 cpu_crit: cpu_crit { 787 temperature = <95000>; 788 hysteresis = <2000>; 789 type = "critical"; 790 }; 791 }; 792 793 cooling-maps { 794 map0 { 795 trip = <&cpu_alert0>; 796 cooling-device = 797 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 798 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 799 }; 800 map1 { 801 trip = <&cpu_alert1>; 802 cooling-device = 803 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 804 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 805 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 806 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 807 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 808 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 809 }; 810 }; 811 }; 812 813 gpu_thermal: gpu { 814 polling-delay-passive = <100>; 815 polling-delay = <1000>; 816 817 thermal-sensors = <&tsadc 1>; 818 819 trips { 820 gpu_alert0: gpu_alert0 { 821 temperature = <75000>; 822 hysteresis = <2000>; 823 type = "passive"; 824 }; 825 gpu_crit: gpu_crit { 826 temperature = <95000>; 827 hysteresis = <2000>; 828 type = "critical"; 829 }; 830 }; 831 }; 832 }; 833 834 tsadc: tsadc@ff260000 { 835 compatible = "rockchip,rk3399-tsadc"; 836 reg = <0x0 0xff260000 0x0 0x100>; 837 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 838 assigned-clocks = <&cru SCLK_TSADC>; 839 assigned-clock-rates = <750000>; 840 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 841 clock-names = "tsadc", "apb_pclk"; 842 resets = <&cru SRST_TSADC>; 843 reset-names = "tsadc-apb"; 844 rockchip,grf = <&grf>; 845 rockchip,hw-tshut-temp = <95000>; 846 pinctrl-names = "init", "default", "sleep"; 847 pinctrl-0 = <&otp_gpio>; 848 pinctrl-1 = <&otp_out>; 849 pinctrl-2 = <&otp_gpio>; 850 #thermal-sensor-cells = <1>; 851 status = "disabled"; 852 }; 853 854 qos_emmc: qos@ffa58000 { 855 compatible = "syscon"; 856 reg = <0x0 0xffa58000 0x0 0x20>; 857 }; 858 859 qos_gmac: qos@ffa5c000 { 860 compatible = "syscon"; 861 reg = <0x0 0xffa5c000 0x0 0x20>; 862 }; 863 864 qos_pcie: qos@ffa60080 { 865 compatible = "syscon"; 866 reg = <0x0 0xffa60080 0x0 0x20>; 867 }; 868 869 qos_usb_host0: qos@ffa60100 { 870 compatible = "syscon"; 871 reg = <0x0 0xffa60100 0x0 0x20>; 872 }; 873 874 qos_usb_host1: qos@ffa60180 { 875 compatible = "syscon"; 876 reg = <0x0 0xffa60180 0x0 0x20>; 877 }; 878 879 qos_usb_otg0: qos@ffa70000 { 880 compatible = "syscon"; 881 reg = <0x0 0xffa70000 0x0 0x20>; 882 }; 883 884 qos_usb_otg1: qos@ffa70080 { 885 compatible = "syscon"; 886 reg = <0x0 0xffa70080 0x0 0x20>; 887 }; 888 889 qos_sd: qos@ffa74000 { 890 compatible = "syscon"; 891 reg = <0x0 0xffa74000 0x0 0x20>; 892 }; 893 894 qos_sdioaudio: qos@ffa76000 { 895 compatible = "syscon"; 896 reg = <0x0 0xffa76000 0x0 0x20>; 897 }; 898 899 qos_hdcp: qos@ffa90000 { 900 compatible = "syscon"; 901 reg = <0x0 0xffa90000 0x0 0x20>; 902 }; 903 904 qos_iep: qos@ffa98000 { 905 compatible = "syscon"; 906 reg = <0x0 0xffa98000 0x0 0x20>; 907 }; 908 909 qos_isp0_m0: qos@ffaa0000 { 910 compatible = "syscon"; 911 reg = <0x0 0xffaa0000 0x0 0x20>; 912 }; 913 914 qos_isp0_m1: qos@ffaa0080 { 915 compatible = "syscon"; 916 reg = <0x0 0xffaa0080 0x0 0x20>; 917 }; 918 919 qos_isp1_m0: qos@ffaa8000 { 920 compatible = "syscon"; 921 reg = <0x0 0xffaa8000 0x0 0x20>; 922 }; 923 924 qos_isp1_m1: qos@ffaa8080 { 925 compatible = "syscon"; 926 reg = <0x0 0xffaa8080 0x0 0x20>; 927 }; 928 929 qos_rga_r: qos@ffab0000 { 930 compatible = "syscon"; 931 reg = <0x0 0xffab0000 0x0 0x20>; 932 }; 933 934 qos_rga_w: qos@ffab0080 { 935 compatible = "syscon"; 936 reg = <0x0 0xffab0080 0x0 0x20>; 937 }; 938 939 qos_video_m0: qos@ffab8000 { 940 compatible = "syscon"; 941 reg = <0x0 0xffab8000 0x0 0x20>; 942 }; 943 944 qos_video_m1_r: qos@ffac0000 { 945 compatible = "syscon"; 946 reg = <0x0 0xffac0000 0x0 0x20>; 947 }; 948 949 qos_video_m1_w: qos@ffac0080 { 950 compatible = "syscon"; 951 reg = <0x0 0xffac0080 0x0 0x20>; 952 }; 953 954 qos_vop_big_r: qos@ffac8000 { 955 compatible = "syscon"; 956 reg = <0x0 0xffac8000 0x0 0x20>; 957 }; 958 959 qos_vop_big_w: qos@ffac8080 { 960 compatible = "syscon"; 961 reg = <0x0 0xffac8080 0x0 0x20>; 962 }; 963 964 qos_vop_little: qos@ffad0000 { 965 compatible = "syscon"; 966 reg = <0x0 0xffad0000 0x0 0x20>; 967 }; 968 969 qos_perihp: qos@ffad8080 { 970 compatible = "syscon"; 971 reg = <0x0 0xffad8080 0x0 0x20>; 972 }; 973 974 qos_gpu: qos@ffae0000 { 975 compatible = "syscon"; 976 reg = <0x0 0xffae0000 0x0 0x20>; 977 }; 978 979 pmu: power-management@ff310000 { 980 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 981 reg = <0x0 0xff310000 0x0 0x1000>; 982 983 /* 984 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 985 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 986 * Some of the power domains are grouped together for every 987 * voltage domain. 988 * The detail contents as below. 989 */ 990 power: power-controller { 991 compatible = "rockchip,rk3399-power-controller"; 992 #power-domain-cells = <1>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 /* These power domains are grouped by VD_CENTER */ 997 pd_iep@RK3399_PD_IEP { 998 reg = <RK3399_PD_IEP>; 999 clocks = <&cru ACLK_IEP>, 1000 <&cru HCLK_IEP>; 1001 pm_qos = <&qos_iep>; 1002 }; 1003 pd_rga@RK3399_PD_RGA { 1004 reg = <RK3399_PD_RGA>; 1005 clocks = <&cru ACLK_RGA>, 1006 <&cru HCLK_RGA>; 1007 pm_qos = <&qos_rga_r>, 1008 <&qos_rga_w>; 1009 }; 1010 pd_vcodec@RK3399_PD_VCODEC { 1011 reg = <RK3399_PD_VCODEC>; 1012 clocks = <&cru ACLK_VCODEC>, 1013 <&cru HCLK_VCODEC>; 1014 pm_qos = <&qos_video_m0>; 1015 }; 1016 pd_vdu@RK3399_PD_VDU { 1017 reg = <RK3399_PD_VDU>; 1018 clocks = <&cru ACLK_VDU>, 1019 <&cru HCLK_VDU>; 1020 pm_qos = <&qos_video_m1_r>, 1021 <&qos_video_m1_w>; 1022 }; 1023 1024 /* These power domains are grouped by VD_GPU */ 1025 pd_gpu@RK3399_PD_GPU { 1026 reg = <RK3399_PD_GPU>; 1027 clocks = <&cru ACLK_GPU>; 1028 pm_qos = <&qos_gpu>; 1029 }; 1030 1031 /* These power domains are grouped by VD_LOGIC */ 1032 pd_edp@RK3399_PD_EDP { 1033 reg = <RK3399_PD_EDP>; 1034 clocks = <&cru PCLK_EDP_CTRL>; 1035 }; 1036 pd_emmc@RK3399_PD_EMMC { 1037 reg = <RK3399_PD_EMMC>; 1038 clocks = <&cru ACLK_EMMC>; 1039 pm_qos = <&qos_emmc>; 1040 }; 1041 pd_gmac@RK3399_PD_GMAC { 1042 reg = <RK3399_PD_GMAC>; 1043 clocks = <&cru ACLK_GMAC>, 1044 <&cru PCLK_GMAC>; 1045 pm_qos = <&qos_gmac>; 1046 }; 1047 pd_sd@RK3399_PD_SD { 1048 reg = <RK3399_PD_SD>; 1049 clocks = <&cru HCLK_SDMMC>, 1050 <&cru SCLK_SDMMC>; 1051 pm_qos = <&qos_sd>; 1052 }; 1053 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1054 reg = <RK3399_PD_SDIOAUDIO>; 1055 clocks = <&cru HCLK_SDIO>; 1056 pm_qos = <&qos_sdioaudio>; 1057 }; 1058 pd_usb3@RK3399_PD_USB3 { 1059 reg = <RK3399_PD_USB3>; 1060 clocks = <&cru ACLK_USB3>; 1061 pm_qos = <&qos_usb_otg0>, 1062 <&qos_usb_otg1>; 1063 }; 1064 pd_vio@RK3399_PD_VIO { 1065 reg = <RK3399_PD_VIO>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 1069 pd_hdcp@RK3399_PD_HDCP { 1070 reg = <RK3399_PD_HDCP>; 1071 clocks = <&cru ACLK_HDCP>, 1072 <&cru HCLK_HDCP>, 1073 <&cru PCLK_HDCP>; 1074 pm_qos = <&qos_hdcp>; 1075 }; 1076 pd_isp0@RK3399_PD_ISP0 { 1077 reg = <RK3399_PD_ISP0>; 1078 clocks = <&cru ACLK_ISP0>, 1079 <&cru HCLK_ISP0>; 1080 pm_qos = <&qos_isp0_m0>, 1081 <&qos_isp0_m1>; 1082 }; 1083 pd_isp1@RK3399_PD_ISP1 { 1084 reg = <RK3399_PD_ISP1>; 1085 clocks = <&cru ACLK_ISP1>, 1086 <&cru HCLK_ISP1>; 1087 pm_qos = <&qos_isp1_m0>, 1088 <&qos_isp1_m1>; 1089 }; 1090 pd_tcpc0@RK3399_PD_TCPC0 { 1091 reg = <RK3399_PD_TCPD0>; 1092 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1093 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1094 }; 1095 pd_tcpc1@RK3399_PD_TCPC1 { 1096 reg = <RK3399_PD_TCPD1>; 1097 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1098 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1099 }; 1100 pd_vo@RK3399_PD_VO { 1101 reg = <RK3399_PD_VO>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 1105 pd_vopb@RK3399_PD_VOPB { 1106 reg = <RK3399_PD_VOPB>; 1107 clocks = <&cru ACLK_VOP0>, 1108 <&cru HCLK_VOP0>; 1109 pm_qos = <&qos_vop_big_r>, 1110 <&qos_vop_big_w>; 1111 }; 1112 pd_vopl@RK3399_PD_VOPL { 1113 reg = <RK3399_PD_VOPL>; 1114 clocks = <&cru ACLK_VOP1>, 1115 <&cru HCLK_VOP1>; 1116 pm_qos = <&qos_vop_little>; 1117 }; 1118 }; 1119 }; 1120 }; 1121 }; 1122 1123 pmugrf: syscon@ff320000 { 1124 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1125 reg = <0x0 0xff320000 0x0 0x1000>; 1126 #address-cells = <1>; 1127 #size-cells = <1>; 1128 1129 pmu_io_domains: io-domains { 1130 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1131 status = "disabled"; 1132 }; 1133 }; 1134 1135 spi3: spi@ff350000 { 1136 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1137 reg = <0x0 0xff350000 0x0 0x1000>; 1138 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1139 clock-names = "spiclk", "apb_pclk"; 1140 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 uart4: serial@ff370000 { 1149 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1150 reg = <0x0 0xff370000 0x0 0x100>; 1151 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1152 clock-names = "baudclk", "apb_pclk"; 1153 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1154 reg-shift = <2>; 1155 reg-io-width = <4>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&uart4_xfer>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c0: i2c@ff3c0000 { 1162 compatible = "rockchip,rk3399-i2c"; 1163 reg = <0x0 0xff3c0000 0x0 0x1000>; 1164 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1165 assigned-clock-rates = <200000000>; 1166 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1167 clock-names = "i2c", "pclk"; 1168 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&i2c0_xfer>; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 i2c4: i2c@ff3d0000 { 1177 compatible = "rockchip,rk3399-i2c"; 1178 reg = <0x0 0xff3d0000 0x0 0x1000>; 1179 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1180 assigned-clock-rates = <200000000>; 1181 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1182 clock-names = "i2c", "pclk"; 1183 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&i2c4_xfer>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 1191 i2c8: i2c@ff3e0000 { 1192 compatible = "rockchip,rk3399-i2c"; 1193 reg = <0x0 0xff3e0000 0x0 0x1000>; 1194 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1195 assigned-clock-rates = <200000000>; 1196 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1197 clock-names = "i2c", "pclk"; 1198 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&i2c8_xfer>; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 status = "disabled"; 1204 }; 1205 1206 pwm0: pwm@ff420000 { 1207 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1208 reg = <0x0 0xff420000 0x0 0x10>; 1209 #pwm-cells = <3>; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&pwm0_pin>; 1212 clocks = <&pmucru PCLK_RKPWM_PMU>; 1213 clock-names = "pwm"; 1214 status = "disabled"; 1215 }; 1216 1217 pwm1: pwm@ff420010 { 1218 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1219 reg = <0x0 0xff420010 0x0 0x10>; 1220 #pwm-cells = <3>; 1221 pinctrl-names = "default"; 1222 pinctrl-0 = <&pwm1_pin>; 1223 clocks = <&pmucru PCLK_RKPWM_PMU>; 1224 clock-names = "pwm"; 1225 status = "disabled"; 1226 }; 1227 1228 pwm2: pwm@ff420020 { 1229 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1230 reg = <0x0 0xff420020 0x0 0x10>; 1231 #pwm-cells = <3>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&pwm2_pin>; 1234 clocks = <&pmucru PCLK_RKPWM_PMU>; 1235 clock-names = "pwm"; 1236 status = "disabled"; 1237 }; 1238 1239 pwm3: pwm@ff420030 { 1240 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1241 reg = <0x0 0xff420030 0x0 0x10>; 1242 #pwm-cells = <3>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&pwm3a_pin>; 1245 clocks = <&pmucru PCLK_RKPWM_PMU>; 1246 clock-names = "pwm"; 1247 status = "disabled"; 1248 }; 1249 1250 vpu: video-codec@ff650000 { 1251 compatible = "rockchip,rk3399-vpu"; 1252 reg = <0x0 0xff650000 0x0 0x800>; 1253 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1254 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1255 interrupt-names = "vepu", "vdpu"; 1256 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1257 clock-names = "aclk", "hclk"; 1258 iommus = <&vpu_mmu>; 1259 power-domains = <&power RK3399_PD_VCODEC>; 1260 }; 1261 1262 vpu_mmu: iommu@ff650800 { 1263 compatible = "rockchip,iommu"; 1264 reg = <0x0 0xff650800 0x0 0x40>; 1265 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1266 interrupt-names = "vpu_mmu"; 1267 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1268 clock-names = "aclk", "iface"; 1269 #iommu-cells = <0>; 1270 power-domains = <&power RK3399_PD_VCODEC>; 1271 }; 1272 1273 vdec_mmu: iommu@ff660480 { 1274 compatible = "rockchip,iommu"; 1275 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1276 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1277 interrupt-names = "vdec_mmu"; 1278 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1279 clock-names = "aclk", "iface"; 1280 #iommu-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 1284 iep_mmu: iommu@ff670800 { 1285 compatible = "rockchip,iommu"; 1286 reg = <0x0 0xff670800 0x0 0x40>; 1287 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1288 interrupt-names = "iep_mmu"; 1289 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1290 clock-names = "aclk", "iface"; 1291 #iommu-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 rga: rga@ff680000 { 1296 compatible = "rockchip,rk3399-rga"; 1297 reg = <0x0 0xff680000 0x0 0x10000>; 1298 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1299 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1300 clock-names = "aclk", "hclk", "sclk"; 1301 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1302 reset-names = "core", "axi", "ahb"; 1303 power-domains = <&power RK3399_PD_RGA>; 1304 }; 1305 1306 efuse0: efuse@ff690000 { 1307 compatible = "rockchip,rk3399-efuse"; 1308 reg = <0x0 0xff690000 0x0 0x80>; 1309 #address-cells = <1>; 1310 #size-cells = <1>; 1311 clocks = <&cru PCLK_EFUSE1024NS>; 1312 clock-names = "pclk_efuse"; 1313 1314 /* Data cells */ 1315 cpu_id: cpu-id@7 { 1316 reg = <0x07 0x10>; 1317 }; 1318 cpub_leakage: cpu-leakage@17 { 1319 reg = <0x17 0x1>; 1320 }; 1321 gpu_leakage: gpu-leakage@18 { 1322 reg = <0x18 0x1>; 1323 }; 1324 center_leakage: center-leakage@19 { 1325 reg = <0x19 0x1>; 1326 }; 1327 cpul_leakage: cpu-leakage@1a { 1328 reg = <0x1a 0x1>; 1329 }; 1330 logic_leakage: logic-leakage@1b { 1331 reg = <0x1b 0x1>; 1332 }; 1333 wafer_info: wafer-info@1c { 1334 reg = <0x1c 0x1>; 1335 }; 1336 }; 1337 1338 pmucru: pmu-clock-controller@ff750000 { 1339 compatible = "rockchip,rk3399-pmucru"; 1340 reg = <0x0 0xff750000 0x0 0x1000>; 1341 rockchip,grf = <&pmugrf>; 1342 #clock-cells = <1>; 1343 #reset-cells = <1>; 1344 assigned-clocks = <&pmucru PLL_PPLL>; 1345 assigned-clock-rates = <676000000>; 1346 }; 1347 1348 cru: clock-controller@ff760000 { 1349 compatible = "rockchip,rk3399-cru"; 1350 reg = <0x0 0xff760000 0x0 0x1000>; 1351 rockchip,grf = <&grf>; 1352 #clock-cells = <1>; 1353 #reset-cells = <1>; 1354 assigned-clocks = 1355 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1356 <&cru PLL_NPLL>, 1357 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1358 <&cru PCLK_PERIHP>, 1359 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1360 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1361 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1362 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1363 <&cru ACLK_GIC_PRE>, 1364 <&cru PCLK_DDR>; 1365 assigned-clock-rates = 1366 <594000000>, <800000000>, 1367 <1000000000>, 1368 <150000000>, <75000000>, 1369 <37500000>, 1370 <100000000>, <100000000>, 1371 <50000000>, <600000000>, 1372 <100000000>, <50000000>, 1373 <400000000>, <400000000>, 1374 <200000000>, 1375 <200000000>; 1376 }; 1377 1378 grf: syscon@ff770000 { 1379 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1380 reg = <0x0 0xff770000 0x0 0x10000>; 1381 #address-cells = <1>; 1382 #size-cells = <1>; 1383 1384 io_domains: io-domains { 1385 compatible = "rockchip,rk3399-io-voltage-domain"; 1386 status = "disabled"; 1387 }; 1388 1389 u2phy0: usb2-phy@e450 { 1390 compatible = "rockchip,rk3399-usb2phy"; 1391 reg = <0xe450 0x10>; 1392 clocks = <&cru SCLK_USB2PHY0_REF>; 1393 clock-names = "phyclk"; 1394 #clock-cells = <0>; 1395 clock-output-names = "clk_usbphy0_480m"; 1396 status = "disabled"; 1397 1398 u2phy0_host: host-port { 1399 #phy-cells = <0>; 1400 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1401 interrupt-names = "linestate"; 1402 status = "disabled"; 1403 }; 1404 1405 u2phy0_otg: otg-port { 1406 #phy-cells = <0>; 1407 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1408 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1409 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1410 interrupt-names = "otg-bvalid", "otg-id", 1411 "linestate"; 1412 status = "disabled"; 1413 }; 1414 }; 1415 1416 u2phy1: usb2-phy@e460 { 1417 compatible = "rockchip,rk3399-usb2phy"; 1418 reg = <0xe460 0x10>; 1419 clocks = <&cru SCLK_USB2PHY1_REF>; 1420 clock-names = "phyclk"; 1421 #clock-cells = <0>; 1422 clock-output-names = "clk_usbphy1_480m"; 1423 status = "disabled"; 1424 1425 u2phy1_host: host-port { 1426 #phy-cells = <0>; 1427 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1428 interrupt-names = "linestate"; 1429 status = "disabled"; 1430 }; 1431 1432 u2phy1_otg: otg-port { 1433 #phy-cells = <0>; 1434 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1435 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1436 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1437 interrupt-names = "otg-bvalid", "otg-id", 1438 "linestate"; 1439 status = "disabled"; 1440 }; 1441 }; 1442 1443 emmc_phy: phy@f780 { 1444 compatible = "rockchip,rk3399-emmc-phy"; 1445 reg = <0xf780 0x24>; 1446 clocks = <&sdhci>; 1447 clock-names = "emmcclk"; 1448 #phy-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 pcie_phy: pcie-phy { 1453 compatible = "rockchip,rk3399-pcie-phy"; 1454 clocks = <&cru SCLK_PCIEPHY_REF>; 1455 clock-names = "refclk"; 1456 #phy-cells = <1>; 1457 resets = <&cru SRST_PCIEPHY>; 1458 drive-impedance-ohm = <50>; 1459 reset-names = "phy"; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 tcphy0: phy@ff7c0000 { 1465 compatible = "rockchip,rk3399-typec-phy"; 1466 reg = <0x0 0xff7c0000 0x0 0x40000>; 1467 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1468 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1469 clock-names = "tcpdcore", "tcpdphy-ref"; 1470 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1471 assigned-clock-rates = <50000000>; 1472 power-domains = <&power RK3399_PD_TCPD0>; 1473 resets = <&cru SRST_UPHY0>, 1474 <&cru SRST_UPHY0_PIPE_L00>, 1475 <&cru SRST_P_UPHY0_TCPHY>; 1476 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1477 rockchip,grf = <&grf>; 1478 status = "disabled"; 1479 1480 tcphy0_dp: dp-port { 1481 #phy-cells = <0>; 1482 }; 1483 1484 tcphy0_usb3: usb3-port { 1485 #phy-cells = <0>; 1486 }; 1487 }; 1488 1489 tcphy1: phy@ff800000 { 1490 compatible = "rockchip,rk3399-typec-phy"; 1491 reg = <0x0 0xff800000 0x0 0x40000>; 1492 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1493 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1494 clock-names = "tcpdcore", "tcpdphy-ref"; 1495 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1496 assigned-clock-rates = <50000000>; 1497 power-domains = <&power RK3399_PD_TCPD1>; 1498 resets = <&cru SRST_UPHY1>, 1499 <&cru SRST_UPHY1_PIPE_L00>, 1500 <&cru SRST_P_UPHY1_TCPHY>; 1501 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1502 rockchip,grf = <&grf>; 1503 status = "disabled"; 1504 1505 tcphy1_dp: dp-port { 1506 #phy-cells = <0>; 1507 }; 1508 1509 tcphy1_usb3: usb3-port { 1510 #phy-cells = <0>; 1511 }; 1512 }; 1513 1514 watchdog@ff848000 { 1515 compatible = "snps,dw-wdt"; 1516 reg = <0x0 0xff848000 0x0 0x100>; 1517 clocks = <&cru PCLK_WDT>; 1518 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1519 }; 1520 1521 rktimer: rktimer@ff850000 { 1522 compatible = "rockchip,rk3399-timer"; 1523 reg = <0x0 0xff850000 0x0 0x1000>; 1524 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1525 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1526 clock-names = "pclk", "timer"; 1527 }; 1528 1529 spdif: spdif@ff870000 { 1530 compatible = "rockchip,rk3399-spdif"; 1531 reg = <0x0 0xff870000 0x0 0x1000>; 1532 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1533 dmas = <&dmac_bus 7>; 1534 dma-names = "tx"; 1535 clock-names = "mclk", "hclk"; 1536 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1537 pinctrl-names = "default"; 1538 pinctrl-0 = <&spdif_bus>; 1539 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1540 #sound-dai-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 1544 i2s0: i2s@ff880000 { 1545 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1546 reg = <0x0 0xff880000 0x0 0x1000>; 1547 rockchip,grf = <&grf>; 1548 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1549 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1550 dma-names = "tx", "rx"; 1551 clock-names = "i2s_clk", "i2s_hclk"; 1552 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1553 pinctrl-names = "default"; 1554 pinctrl-0 = <&i2s0_8ch_bus>; 1555 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1556 #sound-dai-cells = <0>; 1557 status = "disabled"; 1558 }; 1559 1560 i2s1: i2s@ff890000 { 1561 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1562 reg = <0x0 0xff890000 0x0 0x1000>; 1563 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1564 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1565 dma-names = "tx", "rx"; 1566 clock-names = "i2s_clk", "i2s_hclk"; 1567 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&i2s1_2ch_bus>; 1570 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1571 #sound-dai-cells = <0>; 1572 status = "disabled"; 1573 }; 1574 1575 i2s2: i2s@ff8a0000 { 1576 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1577 reg = <0x0 0xff8a0000 0x0 0x1000>; 1578 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1579 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1580 dma-names = "tx", "rx"; 1581 clock-names = "i2s_clk", "i2s_hclk"; 1582 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1583 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1584 #sound-dai-cells = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 vopl: vop@ff8f0000 { 1589 compatible = "rockchip,rk3399-vop-lit"; 1590 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1591 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1592 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1593 assigned-clock-rates = <400000000>, <100000000>; 1594 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1595 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1596 iommus = <&vopl_mmu>; 1597 power-domains = <&power RK3399_PD_VOPL>; 1598 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1599 reset-names = "axi", "ahb", "dclk"; 1600 status = "disabled"; 1601 1602 vopl_out: port { 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 1606 vopl_out_mipi: endpoint@0 { 1607 reg = <0>; 1608 remote-endpoint = <&mipi_in_vopl>; 1609 }; 1610 1611 vopl_out_edp: endpoint@1 { 1612 reg = <1>; 1613 remote-endpoint = <&edp_in_vopl>; 1614 }; 1615 1616 vopl_out_hdmi: endpoint@2 { 1617 reg = <2>; 1618 remote-endpoint = <&hdmi_in_vopl>; 1619 }; 1620 1621 vopl_out_mipi1: endpoint@3 { 1622 reg = <3>; 1623 remote-endpoint = <&mipi1_in_vopl>; 1624 }; 1625 1626 vopl_out_dp: endpoint@4 { 1627 reg = <4>; 1628 remote-endpoint = <&dp_in_vopl>; 1629 }; 1630 }; 1631 }; 1632 1633 vopl_mmu: iommu@ff8f3f00 { 1634 compatible = "rockchip,iommu"; 1635 reg = <0x0 0xff8f3f00 0x0 0x100>; 1636 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1637 interrupt-names = "vopl_mmu"; 1638 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1639 clock-names = "aclk", "iface"; 1640 power-domains = <&power RK3399_PD_VOPL>; 1641 #iommu-cells = <0>; 1642 status = "disabled"; 1643 }; 1644 1645 vopb: vop@ff900000 { 1646 compatible = "rockchip,rk3399-vop-big"; 1647 reg = <0x0 0xff900000 0x0 0x3efc>; 1648 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1649 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1650 assigned-clock-rates = <400000000>, <100000000>; 1651 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1652 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1653 iommus = <&vopb_mmu>; 1654 power-domains = <&power RK3399_PD_VOPB>; 1655 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1656 reset-names = "axi", "ahb", "dclk"; 1657 status = "disabled"; 1658 1659 vopb_out: port { 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 1663 vopb_out_edp: endpoint@0 { 1664 reg = <0>; 1665 remote-endpoint = <&edp_in_vopb>; 1666 }; 1667 1668 vopb_out_mipi: endpoint@1 { 1669 reg = <1>; 1670 remote-endpoint = <&mipi_in_vopb>; 1671 }; 1672 1673 vopb_out_hdmi: endpoint@2 { 1674 reg = <2>; 1675 remote-endpoint = <&hdmi_in_vopb>; 1676 }; 1677 1678 vopb_out_mipi1: endpoint@3 { 1679 reg = <3>; 1680 remote-endpoint = <&mipi1_in_vopb>; 1681 }; 1682 1683 vopb_out_dp: endpoint@4 { 1684 reg = <4>; 1685 remote-endpoint = <&dp_in_vopb>; 1686 }; 1687 }; 1688 }; 1689 1690 vopb_mmu: iommu@ff903f00 { 1691 compatible = "rockchip,iommu"; 1692 reg = <0x0 0xff903f00 0x0 0x100>; 1693 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1694 interrupt-names = "vopb_mmu"; 1695 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1696 clock-names = "aclk", "iface"; 1697 power-domains = <&power RK3399_PD_VOPB>; 1698 #iommu-cells = <0>; 1699 status = "disabled"; 1700 }; 1701 1702 isp0_mmu: iommu@ff914000 { 1703 compatible = "rockchip,iommu"; 1704 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1705 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1706 interrupt-names = "isp0_mmu"; 1707 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1708 clock-names = "aclk", "iface"; 1709 #iommu-cells = <0>; 1710 power-domains = <&power RK3399_PD_ISP0>; 1711 rockchip,disable-mmu-reset; 1712 }; 1713 1714 isp1_mmu: iommu@ff924000 { 1715 compatible = "rockchip,iommu"; 1716 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1717 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1718 interrupt-names = "isp1_mmu"; 1719 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1720 clock-names = "aclk", "iface"; 1721 #iommu-cells = <0>; 1722 power-domains = <&power RK3399_PD_ISP1>; 1723 rockchip,disable-mmu-reset; 1724 }; 1725 1726 hdmi_sound: hdmi-sound { 1727 compatible = "simple-audio-card"; 1728 simple-audio-card,format = "i2s"; 1729 simple-audio-card,mclk-fs = <256>; 1730 simple-audio-card,name = "hdmi-sound"; 1731 status = "disabled"; 1732 1733 simple-audio-card,cpu { 1734 sound-dai = <&i2s2>; 1735 }; 1736 simple-audio-card,codec { 1737 sound-dai = <&hdmi>; 1738 }; 1739 }; 1740 1741 hdmi: hdmi@ff940000 { 1742 compatible = "rockchip,rk3399-dw-hdmi"; 1743 reg = <0x0 0xff940000 0x0 0x20000>; 1744 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1745 clocks = <&cru PCLK_HDMI_CTRL>, 1746 <&cru SCLK_HDMI_SFR>, 1747 <&cru PLL_VPLL>, 1748 <&cru PCLK_VIO_GRF>, 1749 <&cru SCLK_HDMI_CEC>; 1750 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1751 power-domains = <&power RK3399_PD_HDCP>; 1752 reg-io-width = <4>; 1753 rockchip,grf = <&grf>; 1754 #sound-dai-cells = <0>; 1755 status = "disabled"; 1756 1757 ports { 1758 hdmi_in: port { 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 1762 hdmi_in_vopb: endpoint@0 { 1763 reg = <0>; 1764 remote-endpoint = <&vopb_out_hdmi>; 1765 }; 1766 hdmi_in_vopl: endpoint@1 { 1767 reg = <1>; 1768 remote-endpoint = <&vopl_out_hdmi>; 1769 }; 1770 }; 1771 }; 1772 }; 1773 1774 mipi_dsi: mipi@ff960000 { 1775 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1776 reg = <0x0 0xff960000 0x0 0x8000>; 1777 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1778 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1779 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1780 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1781 power-domains = <&power RK3399_PD_VIO>; 1782 resets = <&cru SRST_P_MIPI_DSI0>; 1783 reset-names = "apb"; 1784 rockchip,grf = <&grf>; 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 status = "disabled"; 1788 1789 ports { 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 1793 mipi_in: port@0 { 1794 reg = <0>; 1795 #address-cells = <1>; 1796 #size-cells = <0>; 1797 1798 mipi_in_vopb: endpoint@0 { 1799 reg = <0>; 1800 remote-endpoint = <&vopb_out_mipi>; 1801 }; 1802 mipi_in_vopl: endpoint@1 { 1803 reg = <1>; 1804 remote-endpoint = <&vopl_out_mipi>; 1805 }; 1806 }; 1807 }; 1808 }; 1809 1810 mipi_dsi1: mipi@ff968000 { 1811 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1812 reg = <0x0 0xff968000 0x0 0x8000>; 1813 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1814 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1815 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1816 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1817 power-domains = <&power RK3399_PD_VIO>; 1818 resets = <&cru SRST_P_MIPI_DSI1>; 1819 reset-names = "apb"; 1820 rockchip,grf = <&grf>; 1821 #address-cells = <1>; 1822 #size-cells = <0>; 1823 status = "disabled"; 1824 1825 ports { 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 mipi1_in: port@0 { 1830 reg = <0>; 1831 #address-cells = <1>; 1832 #size-cells = <0>; 1833 1834 mipi1_in_vopb: endpoint@0 { 1835 reg = <0>; 1836 remote-endpoint = <&vopb_out_mipi1>; 1837 }; 1838 1839 mipi1_in_vopl: endpoint@1 { 1840 reg = <1>; 1841 remote-endpoint = <&vopl_out_mipi1>; 1842 }; 1843 }; 1844 }; 1845 }; 1846 1847 edp: edp@ff970000 { 1848 compatible = "rockchip,rk3399-edp"; 1849 reg = <0x0 0xff970000 0x0 0x8000>; 1850 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1851 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1852 clock-names = "dp", "pclk", "grf"; 1853 pinctrl-names = "default"; 1854 pinctrl-0 = <&edp_hpd>; 1855 power-domains = <&power RK3399_PD_EDP>; 1856 resets = <&cru SRST_P_EDP_CTRL>; 1857 reset-names = "dp"; 1858 rockchip,grf = <&grf>; 1859 status = "disabled"; 1860 1861 ports { 1862 #address-cells = <1>; 1863 #size-cells = <0>; 1864 edp_in: port@0 { 1865 reg = <0>; 1866 #address-cells = <1>; 1867 #size-cells = <0>; 1868 1869 edp_in_vopb: endpoint@0 { 1870 reg = <0>; 1871 remote-endpoint = <&vopb_out_edp>; 1872 }; 1873 1874 edp_in_vopl: endpoint@1 { 1875 reg = <1>; 1876 remote-endpoint = <&vopl_out_edp>; 1877 }; 1878 }; 1879 }; 1880 }; 1881 1882 gpu: gpu@ff9a0000 { 1883 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1884 reg = <0x0 0xff9a0000 0x0 0x10000>; 1885 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1886 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1887 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1888 interrupt-names = "gpu", "job", "mmu"; 1889 clocks = <&cru ACLK_GPU>; 1890 power-domains = <&power RK3399_PD_GPU>; 1891 status = "disabled"; 1892 }; 1893 1894 pinctrl: pinctrl { 1895 compatible = "rockchip,rk3399-pinctrl"; 1896 rockchip,grf = <&grf>; 1897 rockchip,pmu = <&pmugrf>; 1898 #address-cells = <2>; 1899 #size-cells = <2>; 1900 ranges; 1901 1902 gpio0: gpio0@ff720000 { 1903 compatible = "rockchip,gpio-bank"; 1904 reg = <0x0 0xff720000 0x0 0x100>; 1905 clocks = <&pmucru PCLK_GPIO0_PMU>; 1906 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1907 1908 gpio-controller; 1909 #gpio-cells = <0x2>; 1910 1911 interrupt-controller; 1912 #interrupt-cells = <0x2>; 1913 }; 1914 1915 gpio1: gpio1@ff730000 { 1916 compatible = "rockchip,gpio-bank"; 1917 reg = <0x0 0xff730000 0x0 0x100>; 1918 clocks = <&pmucru PCLK_GPIO1_PMU>; 1919 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1920 1921 gpio-controller; 1922 #gpio-cells = <0x2>; 1923 1924 interrupt-controller; 1925 #interrupt-cells = <0x2>; 1926 }; 1927 1928 gpio2: gpio2@ff780000 { 1929 compatible = "rockchip,gpio-bank"; 1930 reg = <0x0 0xff780000 0x0 0x100>; 1931 clocks = <&cru PCLK_GPIO2>; 1932 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1933 1934 gpio-controller; 1935 #gpio-cells = <0x2>; 1936 1937 interrupt-controller; 1938 #interrupt-cells = <0x2>; 1939 }; 1940 1941 gpio3: gpio3@ff788000 { 1942 compatible = "rockchip,gpio-bank"; 1943 reg = <0x0 0xff788000 0x0 0x100>; 1944 clocks = <&cru PCLK_GPIO3>; 1945 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1946 1947 gpio-controller; 1948 #gpio-cells = <0x2>; 1949 1950 interrupt-controller; 1951 #interrupt-cells = <0x2>; 1952 }; 1953 1954 gpio4: gpio4@ff790000 { 1955 compatible = "rockchip,gpio-bank"; 1956 reg = <0x0 0xff790000 0x0 0x100>; 1957 clocks = <&cru PCLK_GPIO4>; 1958 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1959 1960 gpio-controller; 1961 #gpio-cells = <0x2>; 1962 1963 interrupt-controller; 1964 #interrupt-cells = <0x2>; 1965 }; 1966 1967 pcfg_pull_up: pcfg-pull-up { 1968 bias-pull-up; 1969 }; 1970 1971 pcfg_pull_down: pcfg-pull-down { 1972 bias-pull-down; 1973 }; 1974 1975 pcfg_pull_none: pcfg-pull-none { 1976 bias-disable; 1977 }; 1978 1979 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1980 bias-disable; 1981 drive-strength = <12>; 1982 }; 1983 1984 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1985 bias-disable; 1986 drive-strength = <13>; 1987 }; 1988 1989 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1990 bias-disable; 1991 drive-strength = <18>; 1992 }; 1993 1994 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 1995 bias-disable; 1996 drive-strength = <20>; 1997 }; 1998 1999 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2000 bias-pull-up; 2001 drive-strength = <2>; 2002 }; 2003 2004 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2005 bias-pull-up; 2006 drive-strength = <8>; 2007 }; 2008 2009 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2010 bias-pull-up; 2011 drive-strength = <18>; 2012 }; 2013 2014 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2015 bias-pull-up; 2016 drive-strength = <20>; 2017 }; 2018 2019 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2020 bias-pull-down; 2021 drive-strength = <4>; 2022 }; 2023 2024 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2025 bias-pull-down; 2026 drive-strength = <8>; 2027 }; 2028 2029 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2030 bias-pull-down; 2031 drive-strength = <12>; 2032 }; 2033 2034 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2035 bias-pull-down; 2036 drive-strength = <18>; 2037 }; 2038 2039 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2040 bias-pull-down; 2041 drive-strength = <20>; 2042 }; 2043 2044 pcfg_output_high: pcfg-output-high { 2045 output-high; 2046 }; 2047 2048 pcfg_output_low: pcfg-output-low { 2049 output-low; 2050 }; 2051 2052 clock { 2053 clk_32k: clk-32k { 2054 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2055 }; 2056 }; 2057 2058 edp { 2059 edp_hpd: edp-hpd { 2060 rockchip,pins = 2061 <4 RK_PC7 2 &pcfg_pull_none>; 2062 }; 2063 }; 2064 2065 gmac { 2066 rgmii_pins: rgmii-pins { 2067 rockchip,pins = 2068 /* mac_txclk */ 2069 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2070 /* mac_rxclk */ 2071 <3 RK_PB6 1 &pcfg_pull_none>, 2072 /* mac_mdio */ 2073 <3 RK_PB5 1 &pcfg_pull_none>, 2074 /* mac_txen */ 2075 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2076 /* mac_clk */ 2077 <3 RK_PB3 1 &pcfg_pull_none>, 2078 /* mac_rxdv */ 2079 <3 RK_PB1 1 &pcfg_pull_none>, 2080 /* mac_mdc */ 2081 <3 RK_PB0 1 &pcfg_pull_none>, 2082 /* mac_rxd1 */ 2083 <3 RK_PA7 1 &pcfg_pull_none>, 2084 /* mac_rxd0 */ 2085 <3 RK_PA6 1 &pcfg_pull_none>, 2086 /* mac_txd1 */ 2087 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2088 /* mac_txd0 */ 2089 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2090 /* mac_rxd3 */ 2091 <3 RK_PA3 1 &pcfg_pull_none>, 2092 /* mac_rxd2 */ 2093 <3 RK_PA2 1 &pcfg_pull_none>, 2094 /* mac_txd3 */ 2095 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2096 /* mac_txd2 */ 2097 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2098 }; 2099 2100 rmii_pins: rmii-pins { 2101 rockchip,pins = 2102 /* mac_mdio */ 2103 <3 RK_PB5 1 &pcfg_pull_none>, 2104 /* mac_txen */ 2105 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2106 /* mac_clk */ 2107 <3 RK_PB3 1 &pcfg_pull_none>, 2108 /* mac_rxer */ 2109 <3 RK_PB2 1 &pcfg_pull_none>, 2110 /* mac_rxdv */ 2111 <3 RK_PB1 1 &pcfg_pull_none>, 2112 /* mac_mdc */ 2113 <3 RK_PB0 1 &pcfg_pull_none>, 2114 /* mac_rxd1 */ 2115 <3 RK_PA7 1 &pcfg_pull_none>, 2116 /* mac_rxd0 */ 2117 <3 RK_PA6 1 &pcfg_pull_none>, 2118 /* mac_txd1 */ 2119 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2120 /* mac_txd0 */ 2121 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2122 }; 2123 }; 2124 2125 i2c0 { 2126 i2c0_xfer: i2c0-xfer { 2127 rockchip,pins = 2128 <1 RK_PB7 2 &pcfg_pull_none>, 2129 <1 RK_PC0 2 &pcfg_pull_none>; 2130 }; 2131 }; 2132 2133 i2c1 { 2134 i2c1_xfer: i2c1-xfer { 2135 rockchip,pins = 2136 <4 RK_PA2 1 &pcfg_pull_none>, 2137 <4 RK_PA1 1 &pcfg_pull_none>; 2138 }; 2139 }; 2140 2141 i2c2 { 2142 i2c2_xfer: i2c2-xfer { 2143 rockchip,pins = 2144 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2145 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2146 }; 2147 }; 2148 2149 i2c3 { 2150 i2c3_xfer: i2c3-xfer { 2151 rockchip,pins = 2152 <4 RK_PC1 1 &pcfg_pull_none>, 2153 <4 RK_PC0 1 &pcfg_pull_none>; 2154 }; 2155 }; 2156 2157 i2c4 { 2158 i2c4_xfer: i2c4-xfer { 2159 rockchip,pins = 2160 <1 RK_PB4 1 &pcfg_pull_none>, 2161 <1 RK_PB3 1 &pcfg_pull_none>; 2162 }; 2163 }; 2164 2165 i2c5 { 2166 i2c5_xfer: i2c5-xfer { 2167 rockchip,pins = 2168 <3 RK_PB3 2 &pcfg_pull_none>, 2169 <3 RK_PB2 2 &pcfg_pull_none>; 2170 }; 2171 }; 2172 2173 i2c6 { 2174 i2c6_xfer: i2c6-xfer { 2175 rockchip,pins = 2176 <2 RK_PB2 2 &pcfg_pull_none>, 2177 <2 RK_PB1 2 &pcfg_pull_none>; 2178 }; 2179 }; 2180 2181 i2c7 { 2182 i2c7_xfer: i2c7-xfer { 2183 rockchip,pins = 2184 <2 RK_PB0 2 &pcfg_pull_none>, 2185 <2 RK_PA7 2 &pcfg_pull_none>; 2186 }; 2187 }; 2188 2189 i2c8 { 2190 i2c8_xfer: i2c8-xfer { 2191 rockchip,pins = 2192 <1 RK_PC5 1 &pcfg_pull_none>, 2193 <1 RK_PC4 1 &pcfg_pull_none>; 2194 }; 2195 }; 2196 2197 i2s0 { 2198 i2s0_2ch_bus: i2s0-2ch-bus { 2199 rockchip,pins = 2200 <3 RK_PD0 1 &pcfg_pull_none>, 2201 <3 RK_PD1 1 &pcfg_pull_none>, 2202 <3 RK_PD2 1 &pcfg_pull_none>, 2203 <3 RK_PD3 1 &pcfg_pull_none>, 2204 <3 RK_PD7 1 &pcfg_pull_none>, 2205 <4 RK_PA0 1 &pcfg_pull_none>; 2206 }; 2207 2208 i2s0_8ch_bus: i2s0-8ch-bus { 2209 rockchip,pins = 2210 <3 RK_PD0 1 &pcfg_pull_none>, 2211 <3 RK_PD1 1 &pcfg_pull_none>, 2212 <3 RK_PD2 1 &pcfg_pull_none>, 2213 <3 RK_PD3 1 &pcfg_pull_none>, 2214 <3 RK_PD4 1 &pcfg_pull_none>, 2215 <3 RK_PD5 1 &pcfg_pull_none>, 2216 <3 RK_PD6 1 &pcfg_pull_none>, 2217 <3 RK_PD7 1 &pcfg_pull_none>, 2218 <4 RK_PA0 1 &pcfg_pull_none>; 2219 }; 2220 }; 2221 2222 i2s1 { 2223 i2s1_2ch_bus: i2s1-2ch-bus { 2224 rockchip,pins = 2225 <4 RK_PA3 1 &pcfg_pull_none>, 2226 <4 RK_PA4 1 &pcfg_pull_none>, 2227 <4 RK_PA5 1 &pcfg_pull_none>, 2228 <4 RK_PA6 1 &pcfg_pull_none>, 2229 <4 RK_PA7 1 &pcfg_pull_none>; 2230 }; 2231 }; 2232 2233 sdio0 { 2234 sdio0_bus1: sdio0-bus1 { 2235 rockchip,pins = 2236 <2 RK_PC4 1 &pcfg_pull_up>; 2237 }; 2238 2239 sdio0_bus4: sdio0-bus4 { 2240 rockchip,pins = 2241 <2 RK_PC4 1 &pcfg_pull_up>, 2242 <2 RK_PC5 1 &pcfg_pull_up>, 2243 <2 RK_PC6 1 &pcfg_pull_up>, 2244 <2 RK_PC7 1 &pcfg_pull_up>; 2245 }; 2246 2247 sdio0_cmd: sdio0-cmd { 2248 rockchip,pins = 2249 <2 RK_PD0 1 &pcfg_pull_up>; 2250 }; 2251 2252 sdio0_clk: sdio0-clk { 2253 rockchip,pins = 2254 <2 RK_PD1 1 &pcfg_pull_none>; 2255 }; 2256 2257 sdio0_cd: sdio0-cd { 2258 rockchip,pins = 2259 <2 RK_PD2 1 &pcfg_pull_up>; 2260 }; 2261 2262 sdio0_pwr: sdio0-pwr { 2263 rockchip,pins = 2264 <2 RK_PD3 1 &pcfg_pull_up>; 2265 }; 2266 2267 sdio0_bkpwr: sdio0-bkpwr { 2268 rockchip,pins = 2269 <2 RK_PD4 1 &pcfg_pull_up>; 2270 }; 2271 2272 sdio0_wp: sdio0-wp { 2273 rockchip,pins = 2274 <0 RK_PA3 1 &pcfg_pull_up>; 2275 }; 2276 2277 sdio0_int: sdio0-int { 2278 rockchip,pins = 2279 <0 RK_PA4 1 &pcfg_pull_up>; 2280 }; 2281 }; 2282 2283 sdmmc { 2284 sdmmc_bus1: sdmmc-bus1 { 2285 rockchip,pins = 2286 <4 RK_PB0 1 &pcfg_pull_up>; 2287 }; 2288 2289 sdmmc_bus4: sdmmc-bus4 { 2290 rockchip,pins = 2291 <4 RK_PB0 1 &pcfg_pull_up>, 2292 <4 RK_PB1 1 &pcfg_pull_up>, 2293 <4 RK_PB2 1 &pcfg_pull_up>, 2294 <4 RK_PB3 1 &pcfg_pull_up>; 2295 }; 2296 2297 sdmmc_clk: sdmmc-clk { 2298 rockchip,pins = 2299 <4 RK_PB4 1 &pcfg_pull_none>; 2300 }; 2301 2302 sdmmc_cmd: sdmmc-cmd { 2303 rockchip,pins = 2304 <4 RK_PB5 1 &pcfg_pull_up>; 2305 }; 2306 2307 sdmmc_cd: sdmmc-cd { 2308 rockchip,pins = 2309 <0 RK_PA7 1 &pcfg_pull_up>; 2310 }; 2311 2312 sdmmc_wp: sdmmc-wp { 2313 rockchip,pins = 2314 <0 RK_PB0 1 &pcfg_pull_up>; 2315 }; 2316 }; 2317 2318 sleep { 2319 ap_pwroff: ap-pwroff { 2320 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2321 }; 2322 2323 ddrio_pwroff: ddrio-pwroff { 2324 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2325 }; 2326 }; 2327 2328 spdif { 2329 spdif_bus: spdif-bus { 2330 rockchip,pins = 2331 <4 RK_PC5 1 &pcfg_pull_none>; 2332 }; 2333 2334 spdif_bus_1: spdif-bus-1 { 2335 rockchip,pins = 2336 <3 RK_PC0 3 &pcfg_pull_none>; 2337 }; 2338 }; 2339 2340 spi0 { 2341 spi0_clk: spi0-clk { 2342 rockchip,pins = 2343 <3 RK_PA6 2 &pcfg_pull_up>; 2344 }; 2345 spi0_cs0: spi0-cs0 { 2346 rockchip,pins = 2347 <3 RK_PA7 2 &pcfg_pull_up>; 2348 }; 2349 spi0_cs1: spi0-cs1 { 2350 rockchip,pins = 2351 <3 RK_PB0 2 &pcfg_pull_up>; 2352 }; 2353 spi0_tx: spi0-tx { 2354 rockchip,pins = 2355 <3 RK_PA5 2 &pcfg_pull_up>; 2356 }; 2357 spi0_rx: spi0-rx { 2358 rockchip,pins = 2359 <3 RK_PA4 2 &pcfg_pull_up>; 2360 }; 2361 }; 2362 2363 spi1 { 2364 spi1_clk: spi1-clk { 2365 rockchip,pins = 2366 <1 RK_PB1 2 &pcfg_pull_up>; 2367 }; 2368 spi1_cs0: spi1-cs0 { 2369 rockchip,pins = 2370 <1 RK_PB2 2 &pcfg_pull_up>; 2371 }; 2372 spi1_rx: spi1-rx { 2373 rockchip,pins = 2374 <1 RK_PA7 2 &pcfg_pull_up>; 2375 }; 2376 spi1_tx: spi1-tx { 2377 rockchip,pins = 2378 <1 RK_PB0 2 &pcfg_pull_up>; 2379 }; 2380 }; 2381 2382 spi2 { 2383 spi2_clk: spi2-clk { 2384 rockchip,pins = 2385 <2 RK_PB3 1 &pcfg_pull_up>; 2386 }; 2387 spi2_cs0: spi2-cs0 { 2388 rockchip,pins = 2389 <2 RK_PB4 1 &pcfg_pull_up>; 2390 }; 2391 spi2_rx: spi2-rx { 2392 rockchip,pins = 2393 <2 RK_PB1 1 &pcfg_pull_up>; 2394 }; 2395 spi2_tx: spi2-tx { 2396 rockchip,pins = 2397 <2 RK_PB2 1 &pcfg_pull_up>; 2398 }; 2399 }; 2400 2401 spi3 { 2402 spi3_clk: spi3-clk { 2403 rockchip,pins = 2404 <1 RK_PC1 1 &pcfg_pull_up>; 2405 }; 2406 spi3_cs0: spi3-cs0 { 2407 rockchip,pins = 2408 <1 RK_PC2 1 &pcfg_pull_up>; 2409 }; 2410 spi3_rx: spi3-rx { 2411 rockchip,pins = 2412 <1 RK_PB7 1 &pcfg_pull_up>; 2413 }; 2414 spi3_tx: spi3-tx { 2415 rockchip,pins = 2416 <1 RK_PC0 1 &pcfg_pull_up>; 2417 }; 2418 }; 2419 2420 spi4 { 2421 spi4_clk: spi4-clk { 2422 rockchip,pins = 2423 <3 RK_PA2 2 &pcfg_pull_up>; 2424 }; 2425 spi4_cs0: spi4-cs0 { 2426 rockchip,pins = 2427 <3 RK_PA3 2 &pcfg_pull_up>; 2428 }; 2429 spi4_rx: spi4-rx { 2430 rockchip,pins = 2431 <3 RK_PA0 2 &pcfg_pull_up>; 2432 }; 2433 spi4_tx: spi4-tx { 2434 rockchip,pins = 2435 <3 RK_PA1 2 &pcfg_pull_up>; 2436 }; 2437 }; 2438 2439 spi5 { 2440 spi5_clk: spi5-clk { 2441 rockchip,pins = 2442 <2 RK_PC6 2 &pcfg_pull_up>; 2443 }; 2444 spi5_cs0: spi5-cs0 { 2445 rockchip,pins = 2446 <2 RK_PC7 2 &pcfg_pull_up>; 2447 }; 2448 spi5_rx: spi5-rx { 2449 rockchip,pins = 2450 <2 RK_PC4 2 &pcfg_pull_up>; 2451 }; 2452 spi5_tx: spi5-tx { 2453 rockchip,pins = 2454 <2 RK_PC5 2 &pcfg_pull_up>; 2455 }; 2456 }; 2457 2458 testclk { 2459 test_clkout0: test-clkout0 { 2460 rockchip,pins = 2461 <0 RK_PA0 1 &pcfg_pull_none>; 2462 }; 2463 2464 test_clkout1: test-clkout1 { 2465 rockchip,pins = 2466 <2 RK_PD1 2 &pcfg_pull_none>; 2467 }; 2468 2469 test_clkout2: test-clkout2 { 2470 rockchip,pins = 2471 <0 RK_PB0 3 &pcfg_pull_none>; 2472 }; 2473 }; 2474 2475 tsadc { 2476 otp_gpio: otp-gpio { 2477 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2478 }; 2479 2480 otp_out: otp-out { 2481 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2482 }; 2483 }; 2484 2485 uart0 { 2486 uart0_xfer: uart0-xfer { 2487 rockchip,pins = 2488 <2 RK_PC0 1 &pcfg_pull_up>, 2489 <2 RK_PC1 1 &pcfg_pull_none>; 2490 }; 2491 2492 uart0_cts: uart0-cts { 2493 rockchip,pins = 2494 <2 RK_PC2 1 &pcfg_pull_none>; 2495 }; 2496 2497 uart0_rts: uart0-rts { 2498 rockchip,pins = 2499 <2 RK_PC3 1 &pcfg_pull_none>; 2500 }; 2501 }; 2502 2503 uart1 { 2504 uart1_xfer: uart1-xfer { 2505 rockchip,pins = 2506 <3 RK_PB4 2 &pcfg_pull_up>, 2507 <3 RK_PB5 2 &pcfg_pull_none>; 2508 }; 2509 }; 2510 2511 uart2a { 2512 uart2a_xfer: uart2a-xfer { 2513 rockchip,pins = 2514 <4 RK_PB0 2 &pcfg_pull_up>, 2515 <4 RK_PB1 2 &pcfg_pull_none>; 2516 }; 2517 }; 2518 2519 uart2b { 2520 uart2b_xfer: uart2b-xfer { 2521 rockchip,pins = 2522 <4 RK_PC0 2 &pcfg_pull_up>, 2523 <4 RK_PC1 2 &pcfg_pull_none>; 2524 }; 2525 }; 2526 2527 uart2c { 2528 uart2c_xfer: uart2c-xfer { 2529 rockchip,pins = 2530 <4 RK_PC3 1 &pcfg_pull_up>, 2531 <4 RK_PC4 1 &pcfg_pull_none>; 2532 }; 2533 }; 2534 2535 uart3 { 2536 uart3_xfer: uart3-xfer { 2537 rockchip,pins = 2538 <3 RK_PB6 2 &pcfg_pull_up>, 2539 <3 RK_PB7 2 &pcfg_pull_none>; 2540 }; 2541 2542 uart3_cts: uart3-cts { 2543 rockchip,pins = 2544 <3 RK_PC0 2 &pcfg_pull_none>; 2545 }; 2546 2547 uart3_rts: uart3-rts { 2548 rockchip,pins = 2549 <3 RK_PC1 2 &pcfg_pull_none>; 2550 }; 2551 }; 2552 2553 uart4 { 2554 uart4_xfer: uart4-xfer { 2555 rockchip,pins = 2556 <1 RK_PA7 1 &pcfg_pull_up>, 2557 <1 RK_PB0 1 &pcfg_pull_none>; 2558 }; 2559 }; 2560 2561 uarthdcp { 2562 uarthdcp_xfer: uarthdcp-xfer { 2563 rockchip,pins = 2564 <4 RK_PC5 2 &pcfg_pull_up>, 2565 <4 RK_PC6 2 &pcfg_pull_none>; 2566 }; 2567 }; 2568 2569 pwm0 { 2570 pwm0_pin: pwm0-pin { 2571 rockchip,pins = 2572 <4 RK_PC2 1 &pcfg_pull_none>; 2573 }; 2574 2575 pwm0_pin_pull_down: pwm0-pin-pull-down { 2576 rockchip,pins = 2577 <4 RK_PC2 1 &pcfg_pull_down>; 2578 }; 2579 2580 vop0_pwm_pin: vop0-pwm-pin { 2581 rockchip,pins = 2582 <4 RK_PC2 2 &pcfg_pull_none>; 2583 }; 2584 2585 vop1_pwm_pin: vop1-pwm-pin { 2586 rockchip,pins = 2587 <4 RK_PC2 3 &pcfg_pull_none>; 2588 }; 2589 }; 2590 2591 pwm1 { 2592 pwm1_pin: pwm1-pin { 2593 rockchip,pins = 2594 <4 RK_PC6 1 &pcfg_pull_none>; 2595 }; 2596 2597 pwm1_pin_pull_down: pwm1-pin-pull-down { 2598 rockchip,pins = 2599 <4 RK_PC6 1 &pcfg_pull_down>; 2600 }; 2601 }; 2602 2603 pwm2 { 2604 pwm2_pin: pwm2-pin { 2605 rockchip,pins = 2606 <1 RK_PC3 1 &pcfg_pull_none>; 2607 }; 2608 2609 pwm2_pin_pull_down: pwm2-pin-pull-down { 2610 rockchip,pins = 2611 <1 RK_PC3 1 &pcfg_pull_down>; 2612 }; 2613 }; 2614 2615 pwm3a { 2616 pwm3a_pin: pwm3a-pin { 2617 rockchip,pins = 2618 <0 RK_PA6 1 &pcfg_pull_none>; 2619 }; 2620 }; 2621 2622 pwm3b { 2623 pwm3b_pin: pwm3b-pin { 2624 rockchip,pins = 2625 <1 RK_PB6 1 &pcfg_pull_none>; 2626 }; 2627 }; 2628 2629 hdmi { 2630 hdmi_i2c_xfer: hdmi-i2c-xfer { 2631 rockchip,pins = 2632 <4 RK_PC1 3 &pcfg_pull_none>, 2633 <4 RK_PC0 3 &pcfg_pull_none>; 2634 }; 2635 2636 hdmi_cec: hdmi-cec { 2637 rockchip,pins = 2638 <4 RK_PC7 1 &pcfg_pull_none>; 2639 }; 2640 }; 2641 2642 pcie { 2643 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2644 rockchip,pins = 2645 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2646 }; 2647 2648 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2649 rockchip,pins = 2650 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2651 }; 2652 }; 2653 2654 }; 2655}; 2656