1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 display_subsystem: display-subsystem { 133 compatible = "rockchip,display-subsystem"; 134 ports = <&vop_out>; 135 }; 136 137 firmware { 138 scmi: scmi { 139 compatible = "arm,scmi-smc"; 140 arm,smc-id = <0x82000010>; 141 shmem = <&scmi_shmem>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 scmi_clk: protocol@14 { 146 reg = <0x14>; 147 #clock-cells = <1>; 148 }; 149 }; 150 }; 151 152 gpu_opp_table: opp-table-1 { 153 compatible = "operating-points-v2"; 154 155 opp-200000000 { 156 opp-hz = /bits/ 64 <200000000>; 157 opp-microvolt = <825000>; 158 }; 159 160 opp-300000000 { 161 opp-hz = /bits/ 64 <300000000>; 162 opp-microvolt = <825000>; 163 }; 164 165 opp-400000000 { 166 opp-hz = /bits/ 64 <400000000>; 167 opp-microvolt = <825000>; 168 }; 169 170 opp-600000000 { 171 opp-hz = /bits/ 64 <600000000>; 172 opp-microvolt = <825000>; 173 }; 174 175 opp-700000000 { 176 opp-hz = /bits/ 64 <700000000>; 177 opp-microvolt = <900000>; 178 }; 179 180 opp-800000000 { 181 opp-hz = /bits/ 64 <800000000>; 182 opp-microvolt = <1000000>; 183 }; 184 }; 185 186 hdmi_sound: hdmi-sound { 187 compatible = "simple-audio-card"; 188 simple-audio-card,name = "HDMI"; 189 simple-audio-card,format = "i2s"; 190 simple-audio-card,mclk-fs = <256>; 191 status = "disabled"; 192 193 simple-audio-card,codec { 194 sound-dai = <&hdmi>; 195 }; 196 197 simple-audio-card,cpu { 198 sound-dai = <&i2s0_8ch>; 199 }; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a55-pmu"; 204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 209 }; 210 211 psci { 212 compatible = "arm,psci-1.0"; 213 method = "smc"; 214 }; 215 216 timer { 217 compatible = "arm,armv8-timer"; 218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 222 arm,no-tick-in-suspend; 223 }; 224 225 xin24m: xin24m { 226 compatible = "fixed-clock"; 227 clock-frequency = <24000000>; 228 clock-output-names = "xin24m"; 229 #clock-cells = <0>; 230 }; 231 232 xin32k: xin32k { 233 compatible = "fixed-clock"; 234 clock-frequency = <32768>; 235 clock-output-names = "xin32k"; 236 pinctrl-0 = <&clk32k_out0>; 237 pinctrl-names = "default"; 238 #clock-cells = <0>; 239 }; 240 241 sram@10f000 { 242 compatible = "mmio-sram"; 243 reg = <0x0 0x0010f000 0x0 0x100>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0 0x0 0x0010f000 0x100>; 247 248 scmi_shmem: sram@0 { 249 compatible = "arm,scmi-shmem"; 250 reg = <0x0 0x100>; 251 }; 252 }; 253 254 sata1: sata@fc400000 { 255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 256 reg = <0 0xfc400000 0 0x1000>; 257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 258 <&cru CLK_SATA1_RXOOB>; 259 clock-names = "sata", "pmalive", "rxoob"; 260 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 261 phys = <&combphy1 PHY_TYPE_SATA>; 262 phy-names = "sata-phy"; 263 ports-implemented = <0x1>; 264 power-domains = <&power RK3568_PD_PIPE>; 265 status = "disabled"; 266 }; 267 268 sata2: sata@fc800000 { 269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 270 reg = <0 0xfc800000 0 0x1000>; 271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 272 <&cru CLK_SATA2_RXOOB>; 273 clock-names = "sata", "pmalive", "rxoob"; 274 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 275 phys = <&combphy2 PHY_TYPE_SATA>; 276 phy-names = "sata-phy"; 277 ports-implemented = <0x1>; 278 power-domains = <&power RK3568_PD_PIPE>; 279 status = "disabled"; 280 }; 281 282 usb_host0_xhci: usb@fcc00000 { 283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 284 reg = <0x0 0xfcc00000 0x0 0x400000>; 285 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 287 <&cru ACLK_USB3OTG0>; 288 clock-names = "ref_clk", "suspend_clk", 289 "bus_clk"; 290 dr_mode = "otg"; 291 phy_type = "utmi_wide"; 292 power-domains = <&power RK3568_PD_PIPE>; 293 resets = <&cru SRST_USB3OTG0>; 294 snps,dis_u2_susphy_quirk; 295 status = "disabled"; 296 }; 297 298 usb_host1_xhci: usb@fd000000 { 299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 300 reg = <0x0 0xfd000000 0x0 0x400000>; 301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 303 <&cru ACLK_USB3OTG1>; 304 clock-names = "ref_clk", "suspend_clk", 305 "bus_clk"; 306 dr_mode = "host"; 307 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 308 phy-names = "usb2-phy", "usb3-phy"; 309 phy_type = "utmi_wide"; 310 power-domains = <&power RK3568_PD_PIPE>; 311 resets = <&cru SRST_USB3OTG1>; 312 snps,dis_u2_susphy_quirk; 313 status = "disabled"; 314 }; 315 316 gic: interrupt-controller@fd400000 { 317 compatible = "arm,gic-v3"; 318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 319 <0x0 0xfd460000 0 0x80000>; /* GICR */ 320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 321 interrupt-controller; 322 #interrupt-cells = <3>; 323 mbi-alias = <0x0 0xfd410000>; 324 mbi-ranges = <296 24>; 325 msi-controller; 326 }; 327 328 usb_host0_ehci: usb@fd800000 { 329 compatible = "generic-ehci"; 330 reg = <0x0 0xfd800000 0x0 0x40000>; 331 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 333 <&cru PCLK_USB>; 334 phys = <&usb2phy1_otg>; 335 phy-names = "usb"; 336 status = "disabled"; 337 }; 338 339 usb_host0_ohci: usb@fd840000 { 340 compatible = "generic-ohci"; 341 reg = <0x0 0xfd840000 0x0 0x40000>; 342 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 344 <&cru PCLK_USB>; 345 phys = <&usb2phy1_otg>; 346 phy-names = "usb"; 347 status = "disabled"; 348 }; 349 350 usb_host1_ehci: usb@fd880000 { 351 compatible = "generic-ehci"; 352 reg = <0x0 0xfd880000 0x0 0x40000>; 353 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 355 <&cru PCLK_USB>; 356 phys = <&usb2phy1_host>; 357 phy-names = "usb"; 358 status = "disabled"; 359 }; 360 361 usb_host1_ohci: usb@fd8c0000 { 362 compatible = "generic-ohci"; 363 reg = <0x0 0xfd8c0000 0x0 0x40000>; 364 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 366 <&cru PCLK_USB>; 367 phys = <&usb2phy1_host>; 368 phy-names = "usb"; 369 status = "disabled"; 370 }; 371 372 pmugrf: syscon@fdc20000 { 373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 374 reg = <0x0 0xfdc20000 0x0 0x10000>; 375 376 pmu_io_domains: io-domains { 377 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 378 status = "disabled"; 379 }; 380 }; 381 382 pipegrf: syscon@fdc50000 { 383 reg = <0x0 0xfdc50000 0x0 0x1000>; 384 }; 385 386 grf: syscon@fdc60000 { 387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 388 reg = <0x0 0xfdc60000 0x0 0x10000>; 389 }; 390 391 pipe_phy_grf1: syscon@fdc80000 { 392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 393 reg = <0x0 0xfdc80000 0x0 0x1000>; 394 }; 395 396 pipe_phy_grf2: syscon@fdc90000 { 397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 398 reg = <0x0 0xfdc90000 0x0 0x1000>; 399 }; 400 401 usb2phy0_grf: syscon@fdca0000 { 402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 403 reg = <0x0 0xfdca0000 0x0 0x8000>; 404 }; 405 406 usb2phy1_grf: syscon@fdca8000 { 407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 408 reg = <0x0 0xfdca8000 0x0 0x8000>; 409 }; 410 411 pmucru: clock-controller@fdd00000 { 412 compatible = "rockchip,rk3568-pmucru"; 413 reg = <0x0 0xfdd00000 0x0 0x1000>; 414 #clock-cells = <1>; 415 #reset-cells = <1>; 416 }; 417 418 cru: clock-controller@fdd20000 { 419 compatible = "rockchip,rk3568-cru"; 420 reg = <0x0 0xfdd20000 0x0 0x1000>; 421 clocks = <&xin24m>; 422 clock-names = "xin24m"; 423 #clock-cells = <1>; 424 #reset-cells = <1>; 425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 426 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 428 rockchip,grf = <&grf>; 429 }; 430 431 i2c0: i2c@fdd40000 { 432 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 433 reg = <0x0 0xfdd40000 0x0 0x1000>; 434 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 436 clock-names = "i2c", "pclk"; 437 pinctrl-0 = <&i2c0_xfer>; 438 pinctrl-names = "default"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 uart0: serial@fdd50000 { 445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 446 reg = <0x0 0xfdd50000 0x0 0x100>; 447 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 449 clock-names = "baudclk", "apb_pclk"; 450 dmas = <&dmac0 0>, <&dmac0 1>; 451 pinctrl-0 = <&uart0_xfer>; 452 pinctrl-names = "default"; 453 reg-io-width = <4>; 454 reg-shift = <2>; 455 status = "disabled"; 456 }; 457 458 pwm0: pwm@fdd70000 { 459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 460 reg = <0x0 0xfdd70000 0x0 0x10>; 461 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 462 clock-names = "pwm", "pclk"; 463 pinctrl-0 = <&pwm0m0_pins>; 464 pinctrl-names = "default"; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 pwm1: pwm@fdd70010 { 470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 471 reg = <0x0 0xfdd70010 0x0 0x10>; 472 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 473 clock-names = "pwm", "pclk"; 474 pinctrl-0 = <&pwm1m0_pins>; 475 pinctrl-names = "default"; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pwm2: pwm@fdd70020 { 481 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 482 reg = <0x0 0xfdd70020 0x0 0x10>; 483 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 484 clock-names = "pwm", "pclk"; 485 pinctrl-0 = <&pwm2m0_pins>; 486 pinctrl-names = "default"; 487 #pwm-cells = <3>; 488 status = "disabled"; 489 }; 490 491 pwm3: pwm@fdd70030 { 492 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 493 reg = <0x0 0xfdd70030 0x0 0x10>; 494 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 495 clock-names = "pwm", "pclk"; 496 pinctrl-0 = <&pwm3_pins>; 497 pinctrl-names = "default"; 498 #pwm-cells = <3>; 499 status = "disabled"; 500 }; 501 502 pmu: power-management@fdd90000 { 503 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 504 reg = <0x0 0xfdd90000 0x0 0x1000>; 505 506 power: power-controller { 507 compatible = "rockchip,rk3568-power-controller"; 508 #power-domain-cells = <1>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 /* These power domains are grouped by VD_GPU */ 513 power-domain@RK3568_PD_GPU { 514 reg = <RK3568_PD_GPU>; 515 clocks = <&cru ACLK_GPU_PRE>, 516 <&cru PCLK_GPU_PRE>; 517 pm_qos = <&qos_gpu>; 518 #power-domain-cells = <0>; 519 }; 520 521 /* These power domains are grouped by VD_LOGIC */ 522 power-domain@RK3568_PD_VI { 523 reg = <RK3568_PD_VI>; 524 clocks = <&cru HCLK_VI>, 525 <&cru PCLK_VI>; 526 pm_qos = <&qos_isp>, 527 <&qos_vicap0>, 528 <&qos_vicap1>; 529 #power-domain-cells = <0>; 530 }; 531 532 power-domain@RK3568_PD_VO { 533 reg = <RK3568_PD_VO>; 534 clocks = <&cru HCLK_VO>, 535 <&cru PCLK_VO>, 536 <&cru ACLK_VOP_PRE>; 537 pm_qos = <&qos_hdcp>, 538 <&qos_vop_m0>, 539 <&qos_vop_m1>; 540 #power-domain-cells = <0>; 541 }; 542 543 power-domain@RK3568_PD_RGA { 544 reg = <RK3568_PD_RGA>; 545 clocks = <&cru HCLK_RGA_PRE>, 546 <&cru PCLK_RGA_PRE>; 547 pm_qos = <&qos_ebc>, 548 <&qos_iep>, 549 <&qos_jpeg_dec>, 550 <&qos_jpeg_enc>, 551 <&qos_rga_rd>, 552 <&qos_rga_wr>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@RK3568_PD_VPU { 557 reg = <RK3568_PD_VPU>; 558 clocks = <&cru HCLK_VPU_PRE>; 559 pm_qos = <&qos_vpu>; 560 #power-domain-cells = <0>; 561 }; 562 563 power-domain@RK3568_PD_RKVDEC { 564 clocks = <&cru HCLK_RKVDEC_PRE>; 565 reg = <RK3568_PD_RKVDEC>; 566 pm_qos = <&qos_rkvdec>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@RK3568_PD_RKVENC { 571 reg = <RK3568_PD_RKVENC>; 572 clocks = <&cru HCLK_RKVENC_PRE>; 573 pm_qos = <&qos_rkvenc_rd_m0>, 574 <&qos_rkvenc_rd_m1>, 575 <&qos_rkvenc_wr_m0>; 576 #power-domain-cells = <0>; 577 }; 578 }; 579 }; 580 581 gpu: gpu@fde60000 { 582 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 583 reg = <0x0 0xfde60000 0x0 0x4000>; 584 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 587 interrupt-names = "job", "mmu", "gpu"; 588 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 589 clock-names = "gpu", "bus"; 590 #cooling-cells = <2>; 591 operating-points-v2 = <&gpu_opp_table>; 592 power-domains = <&power RK3568_PD_GPU>; 593 status = "disabled"; 594 }; 595 596 vpu: video-codec@fdea0400 { 597 compatible = "rockchip,rk3568-vpu"; 598 reg = <0x0 0xfdea0000 0x0 0x800>; 599 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 600 interrupt-names = "vdpu"; 601 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 602 clock-names = "aclk", "hclk"; 603 iommus = <&vdpu_mmu>; 604 power-domains = <&power RK3568_PD_VPU>; 605 }; 606 607 vdpu_mmu: iommu@fdea0800 { 608 compatible = "rockchip,rk3568-iommu"; 609 reg = <0x0 0xfdea0800 0x0 0x40>; 610 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 611 clock-names = "aclk", "iface"; 612 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 613 power-domains = <&power RK3568_PD_VPU>; 614 #iommu-cells = <0>; 615 }; 616 617 rga: rga@fdeb0000 { 618 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 619 reg = <0x0 0xfdeb0000 0x0 0x180>; 620 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 622 clock-names = "aclk", "hclk", "sclk"; 623 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 624 reset-names = "core", "axi", "ahb"; 625 power-domains = <&power RK3568_PD_RGA>; 626 }; 627 628 vepu: video-codec@fdee0000 { 629 compatible = "rockchip,rk3568-vepu"; 630 reg = <0x0 0xfdee0000 0x0 0x800>; 631 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 633 clock-names = "aclk", "hclk"; 634 iommus = <&vepu_mmu>; 635 power-domains = <&power RK3568_PD_RGA>; 636 }; 637 638 vepu_mmu: iommu@fdee0800 { 639 compatible = "rockchip,rk3568-iommu"; 640 reg = <0x0 0xfdee0800 0x0 0x40>; 641 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 643 clock-names = "aclk", "iface"; 644 power-domains = <&power RK3568_PD_RGA>; 645 #iommu-cells = <0>; 646 }; 647 648 sdmmc2: mmc@fe000000 { 649 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 650 reg = <0x0 0xfe000000 0x0 0x4000>; 651 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 653 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 654 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 655 fifo-depth = <0x100>; 656 max-frequency = <150000000>; 657 resets = <&cru SRST_SDMMC2>; 658 reset-names = "reset"; 659 status = "disabled"; 660 }; 661 662 gmac1: ethernet@fe010000 { 663 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 664 reg = <0x0 0xfe010000 0x0 0x10000>; 665 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "macirq", "eth_wake_irq"; 668 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 669 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 670 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 671 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 672 clock-names = "stmmaceth", "mac_clk_rx", 673 "mac_clk_tx", "clk_mac_refout", 674 "aclk_mac", "pclk_mac", 675 "clk_mac_speed", "ptp_ref"; 676 resets = <&cru SRST_A_GMAC1>; 677 reset-names = "stmmaceth"; 678 rockchip,grf = <&grf>; 679 snps,axi-config = <&gmac1_stmmac_axi_setup>; 680 snps,mixed-burst; 681 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 682 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 683 snps,tso; 684 status = "disabled"; 685 686 mdio1: mdio { 687 compatible = "snps,dwmac-mdio"; 688 #address-cells = <0x1>; 689 #size-cells = <0x0>; 690 }; 691 692 gmac1_stmmac_axi_setup: stmmac-axi-config { 693 snps,blen = <0 0 0 0 16 8 4>; 694 snps,rd_osr_lmt = <8>; 695 snps,wr_osr_lmt = <4>; 696 }; 697 698 gmac1_mtl_rx_setup: rx-queues-config { 699 snps,rx-queues-to-use = <1>; 700 queue0 {}; 701 }; 702 703 gmac1_mtl_tx_setup: tx-queues-config { 704 snps,tx-queues-to-use = <1>; 705 queue0 {}; 706 }; 707 }; 708 709 vop: vop@fe040000 { 710 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 711 reg-names = "vop", "gamma-lut"; 712 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 714 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 715 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 716 iommus = <&vop_mmu>; 717 power-domains = <&power RK3568_PD_VO>; 718 rockchip,grf = <&grf>; 719 status = "disabled"; 720 721 vop_out: ports { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 725 vp0: port@0 { 726 reg = <0>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 }; 730 731 vp1: port@1 { 732 reg = <1>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 }; 736 737 vp2: port@2 { 738 reg = <2>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 }; 742 }; 743 }; 744 745 vop_mmu: iommu@fe043e00 { 746 compatible = "rockchip,rk3568-iommu"; 747 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 748 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 750 clock-names = "aclk", "iface"; 751 #iommu-cells = <0>; 752 status = "disabled"; 753 }; 754 755 dsi0: dsi@fe060000 { 756 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 757 reg = <0x00 0xfe060000 0x00 0x10000>; 758 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 759 clock-names = "pclk"; 760 clocks = <&cru PCLK_DSITX_0>; 761 phy-names = "dphy"; 762 phys = <&dsi_dphy0>; 763 power-domains = <&power RK3568_PD_VO>; 764 reset-names = "apb"; 765 resets = <&cru SRST_P_DSITX_0>; 766 rockchip,grf = <&grf>; 767 status = "disabled"; 768 769 ports { 770 #address-cells = <1>; 771 #size-cells = <0>; 772 773 dsi0_in: port@0 { 774 reg = <0>; 775 }; 776 777 dsi0_out: port@1 { 778 reg = <1>; 779 }; 780 }; 781 }; 782 783 dsi1: dsi@fe070000 { 784 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 785 reg = <0x0 0xfe070000 0x0 0x10000>; 786 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 787 clock-names = "pclk"; 788 clocks = <&cru PCLK_DSITX_1>; 789 phy-names = "dphy"; 790 phys = <&dsi_dphy1>; 791 power-domains = <&power RK3568_PD_VO>; 792 reset-names = "apb"; 793 resets = <&cru SRST_P_DSITX_1>; 794 rockchip,grf = <&grf>; 795 status = "disabled"; 796 797 ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 dsi1_in: port@0 { 802 reg = <0>; 803 }; 804 805 dsi1_out: port@1 { 806 reg = <1>; 807 }; 808 }; 809 }; 810 811 hdmi: hdmi@fe0a0000 { 812 compatible = "rockchip,rk3568-dw-hdmi"; 813 reg = <0x0 0xfe0a0000 0x0 0x20000>; 814 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&cru PCLK_HDMI_HOST>, 816 <&cru CLK_HDMI_SFR>, 817 <&cru CLK_HDMI_CEC>, 818 <&pmucru CLK_HDMI_REF>, 819 <&cru HCLK_VO>; 820 clock-names = "iahb", "isfr", "cec", "ref"; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 823 power-domains = <&power RK3568_PD_VO>; 824 reg-io-width = <4>; 825 rockchip,grf = <&grf>; 826 #sound-dai-cells = <0>; 827 status = "disabled"; 828 829 ports { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 833 hdmi_in: port@0 { 834 reg = <0>; 835 }; 836 837 hdmi_out: port@1 { 838 reg = <1>; 839 }; 840 }; 841 }; 842 843 qos_gpu: qos@fe128000 { 844 compatible = "rockchip,rk3568-qos", "syscon"; 845 reg = <0x0 0xfe128000 0x0 0x20>; 846 }; 847 848 qos_rkvenc_rd_m0: qos@fe138080 { 849 compatible = "rockchip,rk3568-qos", "syscon"; 850 reg = <0x0 0xfe138080 0x0 0x20>; 851 }; 852 853 qos_rkvenc_rd_m1: qos@fe138100 { 854 compatible = "rockchip,rk3568-qos", "syscon"; 855 reg = <0x0 0xfe138100 0x0 0x20>; 856 }; 857 858 qos_rkvenc_wr_m0: qos@fe138180 { 859 compatible = "rockchip,rk3568-qos", "syscon"; 860 reg = <0x0 0xfe138180 0x0 0x20>; 861 }; 862 863 qos_isp: qos@fe148000 { 864 compatible = "rockchip,rk3568-qos", "syscon"; 865 reg = <0x0 0xfe148000 0x0 0x20>; 866 }; 867 868 qos_vicap0: qos@fe148080 { 869 compatible = "rockchip,rk3568-qos", "syscon"; 870 reg = <0x0 0xfe148080 0x0 0x20>; 871 }; 872 873 qos_vicap1: qos@fe148100 { 874 compatible = "rockchip,rk3568-qos", "syscon"; 875 reg = <0x0 0xfe148100 0x0 0x20>; 876 }; 877 878 qos_vpu: qos@fe150000 { 879 compatible = "rockchip,rk3568-qos", "syscon"; 880 reg = <0x0 0xfe150000 0x0 0x20>; 881 }; 882 883 qos_ebc: qos@fe158000 { 884 compatible = "rockchip,rk3568-qos", "syscon"; 885 reg = <0x0 0xfe158000 0x0 0x20>; 886 }; 887 888 qos_iep: qos@fe158100 { 889 compatible = "rockchip,rk3568-qos", "syscon"; 890 reg = <0x0 0xfe158100 0x0 0x20>; 891 }; 892 893 qos_jpeg_dec: qos@fe158180 { 894 compatible = "rockchip,rk3568-qos", "syscon"; 895 reg = <0x0 0xfe158180 0x0 0x20>; 896 }; 897 898 qos_jpeg_enc: qos@fe158200 { 899 compatible = "rockchip,rk3568-qos", "syscon"; 900 reg = <0x0 0xfe158200 0x0 0x20>; 901 }; 902 903 qos_rga_rd: qos@fe158280 { 904 compatible = "rockchip,rk3568-qos", "syscon"; 905 reg = <0x0 0xfe158280 0x0 0x20>; 906 }; 907 908 qos_rga_wr: qos@fe158300 { 909 compatible = "rockchip,rk3568-qos", "syscon"; 910 reg = <0x0 0xfe158300 0x0 0x20>; 911 }; 912 913 qos_npu: qos@fe180000 { 914 compatible = "rockchip,rk3568-qos", "syscon"; 915 reg = <0x0 0xfe180000 0x0 0x20>; 916 }; 917 918 qos_pcie2x1: qos@fe190000 { 919 compatible = "rockchip,rk3568-qos", "syscon"; 920 reg = <0x0 0xfe190000 0x0 0x20>; 921 }; 922 923 qos_sata1: qos@fe190280 { 924 compatible = "rockchip,rk3568-qos", "syscon"; 925 reg = <0x0 0xfe190280 0x0 0x20>; 926 }; 927 928 qos_sata2: qos@fe190300 { 929 compatible = "rockchip,rk3568-qos", "syscon"; 930 reg = <0x0 0xfe190300 0x0 0x20>; 931 }; 932 933 qos_usb3_0: qos@fe190380 { 934 compatible = "rockchip,rk3568-qos", "syscon"; 935 reg = <0x0 0xfe190380 0x0 0x20>; 936 }; 937 938 qos_usb3_1: qos@fe190400 { 939 compatible = "rockchip,rk3568-qos", "syscon"; 940 reg = <0x0 0xfe190400 0x0 0x20>; 941 }; 942 943 qos_rkvdec: qos@fe198000 { 944 compatible = "rockchip,rk3568-qos", "syscon"; 945 reg = <0x0 0xfe198000 0x0 0x20>; 946 }; 947 948 qos_hdcp: qos@fe1a8000 { 949 compatible = "rockchip,rk3568-qos", "syscon"; 950 reg = <0x0 0xfe1a8000 0x0 0x20>; 951 }; 952 953 qos_vop_m0: qos@fe1a8080 { 954 compatible = "rockchip,rk3568-qos", "syscon"; 955 reg = <0x0 0xfe1a8080 0x0 0x20>; 956 }; 957 958 qos_vop_m1: qos@fe1a8100 { 959 compatible = "rockchip,rk3568-qos", "syscon"; 960 reg = <0x0 0xfe1a8100 0x0 0x20>; 961 }; 962 963 dfi: dfi@fe230000 { 964 compatible = "rockchip,rk3568-dfi"; 965 reg = <0x00 0xfe230000 0x00 0x400>; 966 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 967 rockchip,pmu = <&pmugrf>; 968 }; 969 970 pcie2x1: pcie@fe260000 { 971 compatible = "rockchip,rk3568-pcie"; 972 reg = <0x3 0xc0000000 0x0 0x00400000>, 973 <0x0 0xfe260000 0x0 0x00010000>, 974 <0x0 0xf4000000 0x0 0x00100000>; 975 reg-names = "dbi", "apb", "config"; 976 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 981 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 982 bus-range = <0x0 0xf>; 983 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 984 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 985 <&cru CLK_PCIE20_AUX_NDFT>; 986 clock-names = "aclk_mst", "aclk_slv", 987 "aclk_dbi", "pclk", "aux"; 988 device_type = "pci"; 989 #interrupt-cells = <1>; 990 interrupt-map-mask = <0 0 0 7>; 991 interrupt-map = <0 0 0 1 &pcie_intc 0>, 992 <0 0 0 2 &pcie_intc 1>, 993 <0 0 0 3 &pcie_intc 2>, 994 <0 0 0 4 &pcie_intc 3>; 995 linux,pci-domain = <0>; 996 num-ib-windows = <6>; 997 num-ob-windows = <2>; 998 max-link-speed = <2>; 999 msi-map = <0x0 &gic 0x0 0x1000>; 1000 num-lanes = <1>; 1001 phys = <&combphy2 PHY_TYPE_PCIE>; 1002 phy-names = "pcie-phy"; 1003 power-domains = <&power RK3568_PD_PIPE>; 1004 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 1005 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 1006 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 1007 resets = <&cru SRST_PCIE20_POWERUP>; 1008 reset-names = "pipe"; 1009 #address-cells = <3>; 1010 #size-cells = <2>; 1011 status = "disabled"; 1012 1013 pcie_intc: legacy-interrupt-controller { 1014 #address-cells = <0>; 1015 #interrupt-cells = <1>; 1016 interrupt-controller; 1017 interrupt-parent = <&gic>; 1018 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 1019 }; 1020 }; 1021 1022 sdmmc0: mmc@fe2b0000 { 1023 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1024 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1025 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 1027 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1028 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1029 fifo-depth = <0x100>; 1030 max-frequency = <150000000>; 1031 resets = <&cru SRST_SDMMC0>; 1032 reset-names = "reset"; 1033 status = "disabled"; 1034 }; 1035 1036 sdmmc1: mmc@fe2c0000 { 1037 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1038 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1039 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1040 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1041 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1042 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1043 fifo-depth = <0x100>; 1044 max-frequency = <150000000>; 1045 resets = <&cru SRST_SDMMC1>; 1046 reset-names = "reset"; 1047 status = "disabled"; 1048 }; 1049 1050 sfc: spi@fe300000 { 1051 compatible = "rockchip,sfc"; 1052 reg = <0x0 0xfe300000 0x0 0x4000>; 1053 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1055 clock-names = "clk_sfc", "hclk_sfc"; 1056 pinctrl-0 = <&fspi_pins>; 1057 pinctrl-names = "default"; 1058 status = "disabled"; 1059 }; 1060 1061 sdhci: mmc@fe310000 { 1062 compatible = "rockchip,rk3568-dwcmshc"; 1063 reg = <0x0 0xfe310000 0x0 0x10000>; 1064 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1065 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1066 assigned-clock-rates = <200000000>, <24000000>; 1067 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1068 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1069 <&cru TCLK_EMMC>; 1070 clock-names = "core", "bus", "axi", "block", "timer"; 1071 status = "disabled"; 1072 }; 1073 1074 i2s0_8ch: i2s@fe400000 { 1075 compatible = "rockchip,rk3568-i2s-tdm"; 1076 reg = <0x0 0xfe400000 0x0 0x1000>; 1077 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1078 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1079 assigned-clock-rates = <1188000000>, <1188000000>; 1080 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1081 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1082 dmas = <&dmac1 0>; 1083 dma-names = "tx"; 1084 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1085 reset-names = "tx-m", "rx-m"; 1086 rockchip,grf = <&grf>; 1087 #sound-dai-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 i2s1_8ch: i2s@fe410000 { 1092 compatible = "rockchip,rk3568-i2s-tdm"; 1093 reg = <0x0 0xfe410000 0x0 0x1000>; 1094 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1095 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1096 assigned-clock-rates = <1188000000>, <1188000000>; 1097 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1098 <&cru HCLK_I2S1_8CH>; 1099 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1100 dmas = <&dmac1 3>, <&dmac1 2>; 1101 dma-names = "rx", "tx"; 1102 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1103 reset-names = "tx-m", "rx-m"; 1104 rockchip,grf = <&grf>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1107 &i2s1m0_lrcktx &i2s1m0_lrckrx 1108 &i2s1m0_sdi0 &i2s1m0_sdi1 1109 &i2s1m0_sdi2 &i2s1m0_sdi3 1110 &i2s1m0_sdo0 &i2s1m0_sdo1 1111 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1112 #sound-dai-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 i2s2_2ch: i2s@fe420000 { 1117 compatible = "rockchip,rk3568-i2s-tdm"; 1118 reg = <0x0 0xfe420000 0x0 0x1000>; 1119 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1120 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1121 assigned-clock-rates = <1188000000>; 1122 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1123 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1124 dmas = <&dmac1 4>, <&dmac1 5>; 1125 dma-names = "tx", "rx"; 1126 resets = <&cru SRST_M_I2S2_2CH>; 1127 reset-names = "tx-m"; 1128 rockchip,grf = <&grf>; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&i2s2m0_sclktx 1131 &i2s2m0_lrcktx 1132 &i2s2m0_sdi 1133 &i2s2m0_sdo>; 1134 #sound-dai-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 i2s3_2ch: i2s@fe430000 { 1139 compatible = "rockchip,rk3568-i2s-tdm"; 1140 reg = <0x0 0xfe430000 0x0 0x1000>; 1141 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1143 <&cru HCLK_I2S3_2CH>; 1144 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1145 dmas = <&dmac1 6>, <&dmac1 7>; 1146 dma-names = "tx", "rx"; 1147 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1148 reset-names = "tx-m", "rx-m"; 1149 rockchip,grf = <&grf>; 1150 #sound-dai-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 pdm: pdm@fe440000 { 1155 compatible = "rockchip,rk3568-pdm"; 1156 reg = <0x0 0xfe440000 0x0 0x1000>; 1157 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1159 clock-names = "pdm_clk", "pdm_hclk"; 1160 dmas = <&dmac1 9>; 1161 dma-names = "rx"; 1162 pinctrl-0 = <&pdmm0_clk 1163 &pdmm0_clk1 1164 &pdmm0_sdi0 1165 &pdmm0_sdi1 1166 &pdmm0_sdi2 1167 &pdmm0_sdi3>; 1168 pinctrl-names = "default"; 1169 resets = <&cru SRST_M_PDM>; 1170 reset-names = "pdm-m"; 1171 #sound-dai-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 spdif: spdif@fe460000 { 1176 compatible = "rockchip,rk3568-spdif"; 1177 reg = <0x0 0xfe460000 0x0 0x1000>; 1178 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1179 clock-names = "mclk", "hclk"; 1180 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1181 dmas = <&dmac1 1>; 1182 dma-names = "tx"; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&spdifm0_tx>; 1185 #sound-dai-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 dmac0: dma-controller@fe530000 { 1190 compatible = "arm,pl330", "arm,primecell"; 1191 reg = <0x0 0xfe530000 0x0 0x4000>; 1192 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1194 arm,pl330-periph-burst; 1195 clocks = <&cru ACLK_BUS>; 1196 clock-names = "apb_pclk"; 1197 #dma-cells = <1>; 1198 }; 1199 1200 dmac1: dma-controller@fe550000 { 1201 compatible = "arm,pl330", "arm,primecell"; 1202 reg = <0x0 0xfe550000 0x0 0x4000>; 1203 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1205 arm,pl330-periph-burst; 1206 clocks = <&cru ACLK_BUS>; 1207 clock-names = "apb_pclk"; 1208 #dma-cells = <1>; 1209 }; 1210 1211 i2c1: i2c@fe5a0000 { 1212 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1213 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1214 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1216 clock-names = "i2c", "pclk"; 1217 pinctrl-0 = <&i2c1_xfer>; 1218 pinctrl-names = "default"; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 i2c2: i2c@fe5b0000 { 1225 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1226 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1227 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1229 clock-names = "i2c", "pclk"; 1230 pinctrl-0 = <&i2c2m0_xfer>; 1231 pinctrl-names = "default"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 i2c3: i2c@fe5c0000 { 1238 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1239 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1242 clock-names = "i2c", "pclk"; 1243 pinctrl-0 = <&i2c3m0_xfer>; 1244 pinctrl-names = "default"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 i2c4: i2c@fe5d0000 { 1251 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1252 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1253 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1254 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1255 clock-names = "i2c", "pclk"; 1256 pinctrl-0 = <&i2c4m0_xfer>; 1257 pinctrl-names = "default"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 i2c5: i2c@fe5e0000 { 1264 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1265 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1266 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1268 clock-names = "i2c", "pclk"; 1269 pinctrl-0 = <&i2c5m0_xfer>; 1270 pinctrl-names = "default"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 status = "disabled"; 1274 }; 1275 1276 wdt: watchdog@fe600000 { 1277 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1278 reg = <0x0 0xfe600000 0x0 0x100>; 1279 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1280 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1281 clock-names = "tclk", "pclk"; 1282 }; 1283 1284 spi0: spi@fe610000 { 1285 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1286 reg = <0x0 0xfe610000 0x0 0x1000>; 1287 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1289 clock-names = "spiclk", "apb_pclk"; 1290 dmas = <&dmac0 20>, <&dmac0 21>; 1291 dma-names = "tx", "rx"; 1292 pinctrl-names = "default"; 1293 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi1: spi@fe620000 { 1300 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1301 reg = <0x0 0xfe620000 0x0 0x1000>; 1302 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1304 clock-names = "spiclk", "apb_pclk"; 1305 dmas = <&dmac0 22>, <&dmac0 23>; 1306 dma-names = "tx", "rx"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 spi2: spi@fe630000 { 1315 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1316 reg = <0x0 0xfe630000 0x0 0x1000>; 1317 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1319 clock-names = "spiclk", "apb_pclk"; 1320 dmas = <&dmac0 24>, <&dmac0 25>; 1321 dma-names = "tx", "rx"; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 status = "disabled"; 1327 }; 1328 1329 spi3: spi@fe640000 { 1330 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1331 reg = <0x0 0xfe640000 0x0 0x1000>; 1332 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1333 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1334 clock-names = "spiclk", "apb_pclk"; 1335 dmas = <&dmac0 26>, <&dmac0 27>; 1336 dma-names = "tx", "rx"; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 status = "disabled"; 1342 }; 1343 1344 uart1: serial@fe650000 { 1345 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1346 reg = <0x0 0xfe650000 0x0 0x100>; 1347 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1349 clock-names = "baudclk", "apb_pclk"; 1350 dmas = <&dmac0 2>, <&dmac0 3>; 1351 pinctrl-0 = <&uart1m0_xfer>; 1352 pinctrl-names = "default"; 1353 reg-io-width = <4>; 1354 reg-shift = <2>; 1355 status = "disabled"; 1356 }; 1357 1358 uart2: serial@fe660000 { 1359 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1360 reg = <0x0 0xfe660000 0x0 0x100>; 1361 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1363 clock-names = "baudclk", "apb_pclk"; 1364 dmas = <&dmac0 4>, <&dmac0 5>; 1365 pinctrl-0 = <&uart2m0_xfer>; 1366 pinctrl-names = "default"; 1367 reg-io-width = <4>; 1368 reg-shift = <2>; 1369 status = "disabled"; 1370 }; 1371 1372 uart3: serial@fe670000 { 1373 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1374 reg = <0x0 0xfe670000 0x0 0x100>; 1375 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1377 clock-names = "baudclk", "apb_pclk"; 1378 dmas = <&dmac0 6>, <&dmac0 7>; 1379 pinctrl-0 = <&uart3m0_xfer>; 1380 pinctrl-names = "default"; 1381 reg-io-width = <4>; 1382 reg-shift = <2>; 1383 status = "disabled"; 1384 }; 1385 1386 uart4: serial@fe680000 { 1387 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1388 reg = <0x0 0xfe680000 0x0 0x100>; 1389 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1391 clock-names = "baudclk", "apb_pclk"; 1392 dmas = <&dmac0 8>, <&dmac0 9>; 1393 pinctrl-0 = <&uart4m0_xfer>; 1394 pinctrl-names = "default"; 1395 reg-io-width = <4>; 1396 reg-shift = <2>; 1397 status = "disabled"; 1398 }; 1399 1400 uart5: serial@fe690000 { 1401 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1402 reg = <0x0 0xfe690000 0x0 0x100>; 1403 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1405 clock-names = "baudclk", "apb_pclk"; 1406 dmas = <&dmac0 10>, <&dmac0 11>; 1407 pinctrl-0 = <&uart5m0_xfer>; 1408 pinctrl-names = "default"; 1409 reg-io-width = <4>; 1410 reg-shift = <2>; 1411 status = "disabled"; 1412 }; 1413 1414 uart6: serial@fe6a0000 { 1415 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1416 reg = <0x0 0xfe6a0000 0x0 0x100>; 1417 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1419 clock-names = "baudclk", "apb_pclk"; 1420 dmas = <&dmac0 12>, <&dmac0 13>; 1421 pinctrl-0 = <&uart6m0_xfer>; 1422 pinctrl-names = "default"; 1423 reg-io-width = <4>; 1424 reg-shift = <2>; 1425 status = "disabled"; 1426 }; 1427 1428 uart7: serial@fe6b0000 { 1429 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1430 reg = <0x0 0xfe6b0000 0x0 0x100>; 1431 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1433 clock-names = "baudclk", "apb_pclk"; 1434 dmas = <&dmac0 14>, <&dmac0 15>; 1435 pinctrl-0 = <&uart7m0_xfer>; 1436 pinctrl-names = "default"; 1437 reg-io-width = <4>; 1438 reg-shift = <2>; 1439 status = "disabled"; 1440 }; 1441 1442 uart8: serial@fe6c0000 { 1443 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1444 reg = <0x0 0xfe6c0000 0x0 0x100>; 1445 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1447 clock-names = "baudclk", "apb_pclk"; 1448 dmas = <&dmac0 16>, <&dmac0 17>; 1449 pinctrl-0 = <&uart8m0_xfer>; 1450 pinctrl-names = "default"; 1451 reg-io-width = <4>; 1452 reg-shift = <2>; 1453 status = "disabled"; 1454 }; 1455 1456 uart9: serial@fe6d0000 { 1457 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1458 reg = <0x0 0xfe6d0000 0x0 0x100>; 1459 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1460 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1461 clock-names = "baudclk", "apb_pclk"; 1462 dmas = <&dmac0 18>, <&dmac0 19>; 1463 pinctrl-0 = <&uart9m0_xfer>; 1464 pinctrl-names = "default"; 1465 reg-io-width = <4>; 1466 reg-shift = <2>; 1467 status = "disabled"; 1468 }; 1469 1470 thermal_zones: thermal-zones { 1471 cpu_thermal: cpu-thermal { 1472 polling-delay-passive = <100>; 1473 polling-delay = <1000>; 1474 1475 thermal-sensors = <&tsadc 0>; 1476 1477 trips { 1478 cpu_alert0: cpu_alert0 { 1479 temperature = <70000>; 1480 hysteresis = <2000>; 1481 type = "passive"; 1482 }; 1483 cpu_alert1: cpu_alert1 { 1484 temperature = <75000>; 1485 hysteresis = <2000>; 1486 type = "passive"; 1487 }; 1488 cpu_crit: cpu_crit { 1489 temperature = <95000>; 1490 hysteresis = <2000>; 1491 type = "critical"; 1492 }; 1493 }; 1494 1495 cooling-maps { 1496 map0 { 1497 trip = <&cpu_alert0>; 1498 cooling-device = 1499 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1500 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1501 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1502 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1503 }; 1504 }; 1505 }; 1506 1507 gpu_thermal: gpu-thermal { 1508 polling-delay-passive = <20>; /* milliseconds */ 1509 polling-delay = <1000>; /* milliseconds */ 1510 1511 thermal-sensors = <&tsadc 1>; 1512 1513 trips { 1514 gpu_threshold: gpu-threshold { 1515 temperature = <70000>; 1516 hysteresis = <2000>; 1517 type = "passive"; 1518 }; 1519 gpu_target: gpu-target { 1520 temperature = <75000>; 1521 hysteresis = <2000>; 1522 type = "passive"; 1523 }; 1524 gpu_crit: gpu-crit { 1525 temperature = <95000>; 1526 hysteresis = <2000>; 1527 type = "critical"; 1528 }; 1529 }; 1530 1531 cooling-maps { 1532 map0 { 1533 trip = <&gpu_target>; 1534 cooling-device = 1535 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1536 }; 1537 }; 1538 }; 1539 }; 1540 1541 tsadc: tsadc@fe710000 { 1542 compatible = "rockchip,rk3568-tsadc"; 1543 reg = <0x0 0xfe710000 0x0 0x100>; 1544 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1545 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1546 assigned-clock-rates = <17000000>, <700000>; 1547 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1548 clock-names = "tsadc", "apb_pclk"; 1549 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1550 <&cru SRST_TSADCPHY>; 1551 rockchip,grf = <&grf>; 1552 rockchip,hw-tshut-temp = <95000>; 1553 pinctrl-names = "init", "default", "sleep"; 1554 pinctrl-0 = <&tsadc_pin>; 1555 pinctrl-1 = <&tsadc_shutorg>; 1556 pinctrl-2 = <&tsadc_pin>; 1557 #thermal-sensor-cells = <1>; 1558 status = "disabled"; 1559 }; 1560 1561 saradc: saradc@fe720000 { 1562 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1563 reg = <0x0 0xfe720000 0x0 0x100>; 1564 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1566 clock-names = "saradc", "apb_pclk"; 1567 resets = <&cru SRST_P_SARADC>; 1568 reset-names = "saradc-apb"; 1569 #io-channel-cells = <1>; 1570 status = "disabled"; 1571 }; 1572 1573 pwm4: pwm@fe6e0000 { 1574 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1575 reg = <0x0 0xfe6e0000 0x0 0x10>; 1576 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1577 clock-names = "pwm", "pclk"; 1578 pinctrl-0 = <&pwm4_pins>; 1579 pinctrl-names = "default"; 1580 #pwm-cells = <3>; 1581 status = "disabled"; 1582 }; 1583 1584 pwm5: pwm@fe6e0010 { 1585 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1586 reg = <0x0 0xfe6e0010 0x0 0x10>; 1587 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1588 clock-names = "pwm", "pclk"; 1589 pinctrl-0 = <&pwm5_pins>; 1590 pinctrl-names = "default"; 1591 #pwm-cells = <3>; 1592 status = "disabled"; 1593 }; 1594 1595 pwm6: pwm@fe6e0020 { 1596 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1597 reg = <0x0 0xfe6e0020 0x0 0x10>; 1598 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1599 clock-names = "pwm", "pclk"; 1600 pinctrl-0 = <&pwm6_pins>; 1601 pinctrl-names = "default"; 1602 #pwm-cells = <3>; 1603 status = "disabled"; 1604 }; 1605 1606 pwm7: pwm@fe6e0030 { 1607 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1608 reg = <0x0 0xfe6e0030 0x0 0x10>; 1609 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1610 clock-names = "pwm", "pclk"; 1611 pinctrl-0 = <&pwm7_pins>; 1612 pinctrl-names = "default"; 1613 #pwm-cells = <3>; 1614 status = "disabled"; 1615 }; 1616 1617 pwm8: pwm@fe6f0000 { 1618 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1619 reg = <0x0 0xfe6f0000 0x0 0x10>; 1620 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1621 clock-names = "pwm", "pclk"; 1622 pinctrl-0 = <&pwm8m0_pins>; 1623 pinctrl-names = "default"; 1624 #pwm-cells = <3>; 1625 status = "disabled"; 1626 }; 1627 1628 pwm9: pwm@fe6f0010 { 1629 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1630 reg = <0x0 0xfe6f0010 0x0 0x10>; 1631 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1632 clock-names = "pwm", "pclk"; 1633 pinctrl-0 = <&pwm9m0_pins>; 1634 pinctrl-names = "default"; 1635 #pwm-cells = <3>; 1636 status = "disabled"; 1637 }; 1638 1639 pwm10: pwm@fe6f0020 { 1640 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1641 reg = <0x0 0xfe6f0020 0x0 0x10>; 1642 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1643 clock-names = "pwm", "pclk"; 1644 pinctrl-0 = <&pwm10m0_pins>; 1645 pinctrl-names = "default"; 1646 #pwm-cells = <3>; 1647 status = "disabled"; 1648 }; 1649 1650 pwm11: pwm@fe6f0030 { 1651 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1652 reg = <0x0 0xfe6f0030 0x0 0x10>; 1653 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1654 clock-names = "pwm", "pclk"; 1655 pinctrl-0 = <&pwm11m0_pins>; 1656 pinctrl-names = "default"; 1657 #pwm-cells = <3>; 1658 status = "disabled"; 1659 }; 1660 1661 pwm12: pwm@fe700000 { 1662 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1663 reg = <0x0 0xfe700000 0x0 0x10>; 1664 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1665 clock-names = "pwm", "pclk"; 1666 pinctrl-0 = <&pwm12m0_pins>; 1667 pinctrl-names = "default"; 1668 #pwm-cells = <3>; 1669 status = "disabled"; 1670 }; 1671 1672 pwm13: pwm@fe700010 { 1673 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1674 reg = <0x0 0xfe700010 0x0 0x10>; 1675 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1676 clock-names = "pwm", "pclk"; 1677 pinctrl-0 = <&pwm13m0_pins>; 1678 pinctrl-names = "default"; 1679 #pwm-cells = <3>; 1680 status = "disabled"; 1681 }; 1682 1683 pwm14: pwm@fe700020 { 1684 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1685 reg = <0x0 0xfe700020 0x0 0x10>; 1686 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1687 clock-names = "pwm", "pclk"; 1688 pinctrl-0 = <&pwm14m0_pins>; 1689 pinctrl-names = "default"; 1690 #pwm-cells = <3>; 1691 status = "disabled"; 1692 }; 1693 1694 pwm15: pwm@fe700030 { 1695 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1696 reg = <0x0 0xfe700030 0x0 0x10>; 1697 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1698 clock-names = "pwm", "pclk"; 1699 pinctrl-0 = <&pwm15m0_pins>; 1700 pinctrl-names = "default"; 1701 #pwm-cells = <3>; 1702 status = "disabled"; 1703 }; 1704 1705 combphy1: phy@fe830000 { 1706 compatible = "rockchip,rk3568-naneng-combphy"; 1707 reg = <0x0 0xfe830000 0x0 0x100>; 1708 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1709 <&cru PCLK_PIPEPHY1>, 1710 <&cru PCLK_PIPE>; 1711 clock-names = "ref", "apb", "pipe"; 1712 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1713 assigned-clock-rates = <100000000>; 1714 resets = <&cru SRST_PIPEPHY1>; 1715 rockchip,pipe-grf = <&pipegrf>; 1716 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1717 #phy-cells = <1>; 1718 status = "disabled"; 1719 }; 1720 1721 combphy2: phy@fe840000 { 1722 compatible = "rockchip,rk3568-naneng-combphy"; 1723 reg = <0x0 0xfe840000 0x0 0x100>; 1724 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1725 <&cru PCLK_PIPEPHY2>, 1726 <&cru PCLK_PIPE>; 1727 clock-names = "ref", "apb", "pipe"; 1728 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1729 assigned-clock-rates = <100000000>; 1730 resets = <&cru SRST_PIPEPHY2>; 1731 rockchip,pipe-grf = <&pipegrf>; 1732 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1733 #phy-cells = <1>; 1734 status = "disabled"; 1735 }; 1736 1737 csi_dphy: phy@fe870000 { 1738 compatible = "rockchip,rk3568-csi-dphy"; 1739 reg = <0x0 0xfe870000 0x0 0x10000>; 1740 clocks = <&cru PCLK_MIPICSIPHY>; 1741 clock-names = "pclk"; 1742 #phy-cells = <0>; 1743 resets = <&cru SRST_P_MIPICSIPHY>; 1744 reset-names = "apb"; 1745 rockchip,grf = <&grf>; 1746 status = "disabled"; 1747 }; 1748 1749 dsi_dphy0: mipi-dphy@fe850000 { 1750 compatible = "rockchip,rk3568-dsi-dphy"; 1751 reg = <0x0 0xfe850000 0x0 0x10000>; 1752 clock-names = "ref", "pclk"; 1753 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1754 #phy-cells = <0>; 1755 power-domains = <&power RK3568_PD_VO>; 1756 reset-names = "apb"; 1757 resets = <&cru SRST_P_MIPIDSIPHY0>; 1758 status = "disabled"; 1759 }; 1760 1761 dsi_dphy1: mipi-dphy@fe860000 { 1762 compatible = "rockchip,rk3568-dsi-dphy"; 1763 reg = <0x0 0xfe860000 0x0 0x10000>; 1764 clock-names = "ref", "pclk"; 1765 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1766 #phy-cells = <0>; 1767 power-domains = <&power RK3568_PD_VO>; 1768 reset-names = "apb"; 1769 resets = <&cru SRST_P_MIPIDSIPHY1>; 1770 status = "disabled"; 1771 }; 1772 1773 usb2phy0: usb2phy@fe8a0000 { 1774 compatible = "rockchip,rk3568-usb2phy"; 1775 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1776 clocks = <&pmucru CLK_USBPHY0_REF>; 1777 clock-names = "phyclk"; 1778 clock-output-names = "clk_usbphy0_480m"; 1779 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1780 rockchip,usbgrf = <&usb2phy0_grf>; 1781 #clock-cells = <0>; 1782 status = "disabled"; 1783 1784 usb2phy0_host: host-port { 1785 #phy-cells = <0>; 1786 status = "disabled"; 1787 }; 1788 1789 usb2phy0_otg: otg-port { 1790 #phy-cells = <0>; 1791 status = "disabled"; 1792 }; 1793 }; 1794 1795 usb2phy1: usb2phy@fe8b0000 { 1796 compatible = "rockchip,rk3568-usb2phy"; 1797 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1798 clocks = <&pmucru CLK_USBPHY1_REF>; 1799 clock-names = "phyclk"; 1800 clock-output-names = "clk_usbphy1_480m"; 1801 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1802 rockchip,usbgrf = <&usb2phy1_grf>; 1803 #clock-cells = <0>; 1804 status = "disabled"; 1805 1806 usb2phy1_host: host-port { 1807 #phy-cells = <0>; 1808 status = "disabled"; 1809 }; 1810 1811 usb2phy1_otg: otg-port { 1812 #phy-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 }; 1816 1817 pinctrl: pinctrl { 1818 compatible = "rockchip,rk3568-pinctrl"; 1819 rockchip,grf = <&grf>; 1820 rockchip,pmu = <&pmugrf>; 1821 #address-cells = <2>; 1822 #size-cells = <2>; 1823 ranges; 1824 1825 gpio0: gpio@fdd60000 { 1826 compatible = "rockchip,gpio-bank"; 1827 reg = <0x0 0xfdd60000 0x0 0x100>; 1828 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1829 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1830 gpio-controller; 1831 gpio-ranges = <&pinctrl 0 0 32>; 1832 #gpio-cells = <2>; 1833 interrupt-controller; 1834 #interrupt-cells = <2>; 1835 }; 1836 1837 gpio1: gpio@fe740000 { 1838 compatible = "rockchip,gpio-bank"; 1839 reg = <0x0 0xfe740000 0x0 0x100>; 1840 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1841 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1842 gpio-controller; 1843 gpio-ranges = <&pinctrl 0 32 32>; 1844 #gpio-cells = <2>; 1845 interrupt-controller; 1846 #interrupt-cells = <2>; 1847 }; 1848 1849 gpio2: gpio@fe750000 { 1850 compatible = "rockchip,gpio-bank"; 1851 reg = <0x0 0xfe750000 0x0 0x100>; 1852 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1854 gpio-controller; 1855 gpio-ranges = <&pinctrl 0 64 32>; 1856 #gpio-cells = <2>; 1857 interrupt-controller; 1858 #interrupt-cells = <2>; 1859 }; 1860 1861 gpio3: gpio@fe760000 { 1862 compatible = "rockchip,gpio-bank"; 1863 reg = <0x0 0xfe760000 0x0 0x100>; 1864 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1866 gpio-controller; 1867 gpio-ranges = <&pinctrl 0 96 32>; 1868 #gpio-cells = <2>; 1869 interrupt-controller; 1870 #interrupt-cells = <2>; 1871 }; 1872 1873 gpio4: gpio@fe770000 { 1874 compatible = "rockchip,gpio-bank"; 1875 reg = <0x0 0xfe770000 0x0 0x100>; 1876 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1877 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1878 gpio-controller; 1879 gpio-ranges = <&pinctrl 0 128 32>; 1880 #gpio-cells = <2>; 1881 interrupt-controller; 1882 #interrupt-cells = <2>; 1883 }; 1884 }; 1885}; 1886 1887#include "rk3568-pinctrl.dtsi" 1888