1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Device Tree Source for UniPhier LD20 SoC
4//
5// Copyright (C) 2015-2016 Socionext Inc.
6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/gpio/uniphier-gpio.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/ {
13	compatible = "socionext,uniphier-ld20";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&gic>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu-map {
23			cluster0 {
24				core0 {
25					cpu = <&cpu0>;
26				};
27				core1 {
28					cpu = <&cpu1>;
29				};
30			};
31
32			cluster1 {
33				core0 {
34					cpu = <&cpu2>;
35				};
36				core1 {
37					cpu = <&cpu3>;
38				};
39			};
40		};
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a72";
45			reg = <0 0x000>;
46			clocks = <&sys_clk 32>;
47			enable-method = "psci";
48			operating-points-v2 = <&cluster0_opp>;
49			#cooling-cells = <2>;
50		};
51
52		cpu1: cpu@1 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a72";
55			reg = <0 0x001>;
56			clocks = <&sys_clk 32>;
57			enable-method = "psci";
58			operating-points-v2 = <&cluster0_opp>;
59			#cooling-cells = <2>;
60		};
61
62		cpu2: cpu@100 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a53";
65			reg = <0 0x100>;
66			clocks = <&sys_clk 33>;
67			enable-method = "psci";
68			operating-points-v2 = <&cluster1_opp>;
69			#cooling-cells = <2>;
70		};
71
72		cpu3: cpu@101 {
73			device_type = "cpu";
74			compatible = "arm,cortex-a53";
75			reg = <0 0x101>;
76			clocks = <&sys_clk 33>;
77			enable-method = "psci";
78			operating-points-v2 = <&cluster1_opp>;
79			#cooling-cells = <2>;
80		};
81	};
82
83	cluster0_opp: opp-table0 {
84		compatible = "operating-points-v2";
85		opp-shared;
86
87		opp-250000000 {
88			opp-hz = /bits/ 64 <250000000>;
89			clock-latency-ns = <300>;
90		};
91		opp-275000000 {
92			opp-hz = /bits/ 64 <275000000>;
93			clock-latency-ns = <300>;
94		};
95		opp-500000000 {
96			opp-hz = /bits/ 64 <500000000>;
97			clock-latency-ns = <300>;
98		};
99		opp-550000000 {
100			opp-hz = /bits/ 64 <550000000>;
101			clock-latency-ns = <300>;
102		};
103		opp-666667000 {
104			opp-hz = /bits/ 64 <666667000>;
105			clock-latency-ns = <300>;
106		};
107		opp-733334000 {
108			opp-hz = /bits/ 64 <733334000>;
109			clock-latency-ns = <300>;
110		};
111		opp-1000000000 {
112			opp-hz = /bits/ 64 <1000000000>;
113			clock-latency-ns = <300>;
114		};
115		opp-1100000000 {
116			opp-hz = /bits/ 64 <1100000000>;
117			clock-latency-ns = <300>;
118		};
119	};
120
121	cluster1_opp: opp-table1 {
122		compatible = "operating-points-v2";
123		opp-shared;
124
125		opp-250000000 {
126			opp-hz = /bits/ 64 <250000000>;
127			clock-latency-ns = <300>;
128		};
129		opp-275000000 {
130			opp-hz = /bits/ 64 <275000000>;
131			clock-latency-ns = <300>;
132		};
133		opp-500000000 {
134			opp-hz = /bits/ 64 <500000000>;
135			clock-latency-ns = <300>;
136		};
137		opp-550000000 {
138			opp-hz = /bits/ 64 <550000000>;
139			clock-latency-ns = <300>;
140		};
141		opp-666667000 {
142			opp-hz = /bits/ 64 <666667000>;
143			clock-latency-ns = <300>;
144		};
145		opp-733334000 {
146			opp-hz = /bits/ 64 <733334000>;
147			clock-latency-ns = <300>;
148		};
149		opp-1000000000 {
150			opp-hz = /bits/ 64 <1000000000>;
151			clock-latency-ns = <300>;
152		};
153		opp-1100000000 {
154			opp-hz = /bits/ 64 <1100000000>;
155			clock-latency-ns = <300>;
156		};
157	};
158
159	psci {
160		compatible = "arm,psci-1.0";
161		method = "smc";
162	};
163
164	clocks {
165		refclk: ref {
166			compatible = "fixed-clock";
167			#clock-cells = <0>;
168			clock-frequency = <25000000>;
169		};
170	};
171
172	emmc_pwrseq: emmc-pwrseq {
173		compatible = "mmc-pwrseq-emmc";
174		reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
175	};
176
177	timer {
178		compatible = "arm,armv8-timer";
179		interrupts = <1 13 4>,
180			     <1 14 4>,
181			     <1 11 4>,
182			     <1 10 4>;
183	};
184
185	thermal-zones {
186		cpu-thermal {
187			polling-delay-passive = <250>;	/* 250ms */
188			polling-delay = <1000>;		/* 1000ms */
189			thermal-sensors = <&pvtctl>;
190
191			trips {
192				cpu_crit: cpu-crit {
193					temperature = <110000>;	/* 110C */
194					hysteresis = <2000>;
195					type = "critical";
196				};
197				cpu_alert: cpu-alert {
198					temperature = <100000>;	/* 100C */
199					hysteresis = <2000>;
200					type = "passive";
201				};
202			};
203
204			cooling-maps {
205				map0 {
206					trip = <&cpu_alert>;
207					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211				};
212			};
213		};
214	};
215
216	reserved-memory {
217		#address-cells = <2>;
218		#size-cells = <2>;
219		ranges;
220
221		secure-memory@81000000 {
222			reg = <0x0 0x81000000 0x0 0x01000000>;
223			no-map;
224		};
225	};
226
227	soc@0 {
228		compatible = "simple-bus";
229		#address-cells = <1>;
230		#size-cells = <1>;
231		ranges = <0 0 0 0xffffffff>;
232
233		spi0: spi@54006000 {
234			compatible = "socionext,uniphier-scssi";
235			status = "disabled";
236			reg = <0x54006000 0x100>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			interrupts = <0 39 4>;
240			pinctrl-names = "default";
241			pinctrl-0 = <&pinctrl_spi0>;
242			clocks = <&peri_clk 11>;
243			resets = <&peri_rst 11>;
244		};
245
246		spi1: spi@54006100 {
247			compatible = "socionext,uniphier-scssi";
248			status = "disabled";
249			reg = <0x54006100 0x100>;
250			#address-cells = <1>;
251			#size-cells = <0>;
252			interrupts = <0 216 4>;
253			pinctrl-names = "default";
254			pinctrl-0 = <&pinctrl_spi1>;
255			clocks = <&peri_clk 12>;
256			resets = <&peri_rst 12>;
257		};
258
259		spi2: spi@54006200 {
260			compatible = "socionext,uniphier-scssi";
261			status = "disabled";
262			reg = <0x54006200 0x100>;
263			#address-cells = <1>;
264			#size-cells = <0>;
265			interrupts = <0 229 4>;
266			pinctrl-names = "default";
267			pinctrl-0 = <&pinctrl_spi2>;
268			clocks = <&peri_clk 13>;
269			resets = <&peri_rst 13>;
270		};
271
272		spi3: spi@54006300 {
273			compatible = "socionext,uniphier-scssi";
274			status = "disabled";
275			reg = <0x54006300 0x100>;
276			#address-cells = <1>;
277			#size-cells = <0>;
278			interrupts = <0 230 4>;
279			pinctrl-names = "default";
280			pinctrl-0 = <&pinctrl_spi3>;
281			clocks = <&peri_clk 14>;
282			resets = <&peri_rst 14>;
283		};
284
285		serial0: serial@54006800 {
286			compatible = "socionext,uniphier-uart";
287			status = "disabled";
288			reg = <0x54006800 0x40>;
289			interrupts = <0 33 4>;
290			pinctrl-names = "default";
291			pinctrl-0 = <&pinctrl_uart0>;
292			clocks = <&peri_clk 0>;
293			resets = <&peri_rst 0>;
294		};
295
296		serial1: serial@54006900 {
297			compatible = "socionext,uniphier-uart";
298			status = "disabled";
299			reg = <0x54006900 0x40>;
300			interrupts = <0 35 4>;
301			pinctrl-names = "default";
302			pinctrl-0 = <&pinctrl_uart1>;
303			clocks = <&peri_clk 1>;
304			resets = <&peri_rst 1>;
305		};
306
307		serial2: serial@54006a00 {
308			compatible = "socionext,uniphier-uart";
309			status = "disabled";
310			reg = <0x54006a00 0x40>;
311			interrupts = <0 37 4>;
312			pinctrl-names = "default";
313			pinctrl-0 = <&pinctrl_uart2>;
314			clocks = <&peri_clk 2>;
315			resets = <&peri_rst 2>;
316		};
317
318		serial3: serial@54006b00 {
319			compatible = "socionext,uniphier-uart";
320			status = "disabled";
321			reg = <0x54006b00 0x40>;
322			interrupts = <0 177 4>;
323			pinctrl-names = "default";
324			pinctrl-0 = <&pinctrl_uart3>;
325			clocks = <&peri_clk 3>;
326			resets = <&peri_rst 3>;
327		};
328
329		gpio: gpio@55000000 {
330			compatible = "socionext,uniphier-gpio";
331			reg = <0x55000000 0x200>;
332			interrupt-parent = <&aidet>;
333			interrupt-controller;
334			#interrupt-cells = <2>;
335			gpio-controller;
336			#gpio-cells = <2>;
337			gpio-ranges = <&pinctrl 0 0 0>,
338				      <&pinctrl 96 0 0>,
339				      <&pinctrl 160 0 0>;
340			gpio-ranges-group-names = "gpio_range0",
341						  "gpio_range1",
342						  "gpio_range2";
343			ngpios = <205>;
344			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
345						     <21 217 3>;
346		};
347
348		audio@56000000 {
349			compatible = "socionext,uniphier-ld20-aio";
350			reg = <0x56000000 0x80000>;
351			interrupts = <0 144 4>;
352			pinctrl-names = "default";
353			pinctrl-0 = <&pinctrl_aout1>,
354				    <&pinctrl_aoutiec1>;
355			clock-names = "aio";
356			clocks = <&sys_clk 40>;
357			reset-names = "aio";
358			resets = <&sys_rst 40>;
359			#sound-dai-cells = <1>;
360			socionext,syscon = <&soc_glue>;
361
362			i2s_port0: port@0 {
363				i2s_hdmi: endpoint {
364				};
365			};
366
367			i2s_port1: port@1 {
368				i2s_pcmin2: endpoint {
369				};
370			};
371
372			i2s_port2: port@2 {
373				i2s_line: endpoint {
374					dai-format = "i2s";
375					remote-endpoint = <&evea_line>;
376				};
377			};
378
379			i2s_port3: port@3 {
380				i2s_hpcmout1: endpoint {
381				};
382			};
383
384			i2s_port4: port@4 {
385				i2s_hp: endpoint {
386					dai-format = "i2s";
387					remote-endpoint = <&evea_hp>;
388				};
389			};
390
391			spdif_port0: port@5 {
392				spdif_hiecout1: endpoint {
393				};
394			};
395
396			src_port0: port@6 {
397				i2s_epcmout2: endpoint {
398				};
399			};
400
401			src_port1: port@7 {
402				i2s_epcmout3: endpoint {
403				};
404			};
405
406			comp_spdif_port0: port@8 {
407				comp_spdif_hiecout1: endpoint {
408				};
409			};
410		};
411
412		codec@57900000 {
413			compatible = "socionext,uniphier-evea";
414			reg = <0x57900000 0x1000>;
415			clock-names = "evea", "exiv";
416			clocks = <&sys_clk 41>, <&sys_clk 42>;
417			reset-names = "evea", "exiv", "adamv";
418			resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
419			#sound-dai-cells = <1>;
420
421			port@0 {
422				evea_line: endpoint {
423					remote-endpoint = <&i2s_line>;
424				};
425			};
426
427			port@1 {
428				evea_hp: endpoint {
429					remote-endpoint = <&i2s_hp>;
430				};
431			};
432		};
433
434		adamv@57920000 {
435			compatible = "socionext,uniphier-ld20-adamv",
436				     "simple-mfd", "syscon";
437			reg = <0x57920000 0x1000>;
438
439			adamv_rst: reset {
440				compatible = "socionext,uniphier-ld20-adamv-reset";
441				#reset-cells = <1>;
442			};
443		};
444
445		i2c0: i2c@58780000 {
446			compatible = "socionext,uniphier-fi2c";
447			status = "disabled";
448			reg = <0x58780000 0x80>;
449			#address-cells = <1>;
450			#size-cells = <0>;
451			interrupts = <0 41 4>;
452			pinctrl-names = "default";
453			pinctrl-0 = <&pinctrl_i2c0>;
454			clocks = <&peri_clk 4>;
455			resets = <&peri_rst 4>;
456			clock-frequency = <100000>;
457		};
458
459		i2c1: i2c@58781000 {
460			compatible = "socionext,uniphier-fi2c";
461			status = "disabled";
462			reg = <0x58781000 0x80>;
463			#address-cells = <1>;
464			#size-cells = <0>;
465			interrupts = <0 42 4>;
466			pinctrl-names = "default";
467			pinctrl-0 = <&pinctrl_i2c1>;
468			clocks = <&peri_clk 5>;
469			resets = <&peri_rst 5>;
470			clock-frequency = <100000>;
471		};
472
473		i2c2: i2c@58782000 {
474			compatible = "socionext,uniphier-fi2c";
475			reg = <0x58782000 0x80>;
476			#address-cells = <1>;
477			#size-cells = <0>;
478			interrupts = <0 43 4>;
479			clocks = <&peri_clk 6>;
480			resets = <&peri_rst 6>;
481			clock-frequency = <400000>;
482		};
483
484		i2c3: i2c@58783000 {
485			compatible = "socionext,uniphier-fi2c";
486			status = "disabled";
487			reg = <0x58783000 0x80>;
488			#address-cells = <1>;
489			#size-cells = <0>;
490			interrupts = <0 44 4>;
491			pinctrl-names = "default";
492			pinctrl-0 = <&pinctrl_i2c3>;
493			clocks = <&peri_clk 7>;
494			resets = <&peri_rst 7>;
495			clock-frequency = <100000>;
496		};
497
498		i2c4: i2c@58784000 {
499			compatible = "socionext,uniphier-fi2c";
500			status = "disabled";
501			reg = <0x58784000 0x80>;
502			#address-cells = <1>;
503			#size-cells = <0>;
504			interrupts = <0 45 4>;
505			pinctrl-names = "default";
506			pinctrl-0 = <&pinctrl_i2c4>;
507			clocks = <&peri_clk 8>;
508			resets = <&peri_rst 8>;
509			clock-frequency = <100000>;
510		};
511
512		i2c5: i2c@58785000 {
513			compatible = "socionext,uniphier-fi2c";
514			reg = <0x58785000 0x80>;
515			#address-cells = <1>;
516			#size-cells = <0>;
517			interrupts = <0 25 4>;
518			clocks = <&peri_clk 9>;
519			resets = <&peri_rst 9>;
520			clock-frequency = <400000>;
521		};
522
523		system_bus: system-bus@58c00000 {
524			compatible = "socionext,uniphier-system-bus";
525			status = "disabled";
526			reg = <0x58c00000 0x400>;
527			#address-cells = <2>;
528			#size-cells = <1>;
529			pinctrl-names = "default";
530			pinctrl-0 = <&pinctrl_system_bus>;
531		};
532
533		smpctrl@59801000 {
534			compatible = "socionext,uniphier-smpctrl";
535			reg = <0x59801000 0x400>;
536		};
537
538		sdctrl@59810000 {
539			compatible = "socionext,uniphier-ld20-sdctrl",
540				     "simple-mfd", "syscon";
541			reg = <0x59810000 0x400>;
542
543			sd_clk: clock {
544				compatible = "socionext,uniphier-ld20-sd-clock";
545				#clock-cells = <1>;
546			};
547
548			sd_rst: reset {
549				compatible = "socionext,uniphier-ld20-sd-reset";
550				#reset-cells = <1>;
551			};
552		};
553
554		perictrl@59820000 {
555			compatible = "socionext,uniphier-ld20-perictrl",
556				     "simple-mfd", "syscon";
557			reg = <0x59820000 0x200>;
558
559			peri_clk: clock {
560				compatible = "socionext,uniphier-ld20-peri-clock";
561				#clock-cells = <1>;
562			};
563
564			peri_rst: reset {
565				compatible = "socionext,uniphier-ld20-peri-reset";
566				#reset-cells = <1>;
567			};
568		};
569
570		emmc: mmc@5a000000 {
571			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
572			reg = <0x5a000000 0x400>;
573			interrupts = <0 78 4>;
574			pinctrl-names = "default";
575			pinctrl-0 = <&pinctrl_emmc>;
576			clocks = <&sys_clk 4>;
577			resets = <&sys_rst 4>;
578			bus-width = <8>;
579			mmc-ddr-1_8v;
580			mmc-hs200-1_8v;
581			mmc-pwrseq = <&emmc_pwrseq>;
582			cdns,phy-input-delay-legacy = <9>;
583			cdns,phy-input-delay-mmc-highspeed = <2>;
584			cdns,phy-input-delay-mmc-ddr = <3>;
585			cdns,phy-dll-delay-sdclk = <21>;
586			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
587		};
588
589		sd: mmc@5a400000 {
590			compatible = "socionext,uniphier-sd-v3.1.1";
591			status = "disabled";
592			reg = <0x5a400000 0x800>;
593			interrupts = <0 76 4>;
594			pinctrl-names = "default";
595			pinctrl-0 = <&pinctrl_sd>;
596			clocks = <&sd_clk 0>;
597			reset-names = "host";
598			resets = <&sd_rst 0>;
599			bus-width = <4>;
600			cap-sd-highspeed;
601		};
602
603		soc_glue: soc-glue@5f800000 {
604			compatible = "socionext,uniphier-ld20-soc-glue",
605				     "simple-mfd", "syscon";
606			reg = <0x5f800000 0x2000>;
607
608			pinctrl: pinctrl {
609				compatible = "socionext,uniphier-ld20-pinctrl";
610			};
611		};
612
613		soc-glue@5f900000 {
614			compatible = "socionext,uniphier-ld20-soc-glue-debug",
615				     "simple-mfd";
616			#address-cells = <1>;
617			#size-cells = <1>;
618			ranges = <0 0x5f900000 0x2000>;
619
620			efuse@100 {
621				compatible = "socionext,uniphier-efuse";
622				reg = <0x100 0x28>;
623			};
624
625			efuse@200 {
626				compatible = "socionext,uniphier-efuse";
627				reg = <0x200 0x68>;
628				#address-cells = <1>;
629				#size-cells = <1>;
630
631				/* USB cells */
632				usb_rterm0: trim@54,4 {
633					reg = <0x54 1>;
634					bits = <4 2>;
635				};
636				usb_rterm1: trim@55,4 {
637					reg = <0x55 1>;
638					bits = <4 2>;
639				};
640				usb_rterm2: trim@58,4 {
641					reg = <0x58 1>;
642					bits = <4 2>;
643				};
644				usb_rterm3: trim@59,4 {
645					reg = <0x59 1>;
646					bits = <4 2>;
647				};
648				usb_sel_t0: trim@54,0 {
649					reg = <0x54 1>;
650					bits = <0 4>;
651				};
652				usb_sel_t1: trim@55,0 {
653					reg = <0x55 1>;
654					bits = <0 4>;
655				};
656				usb_sel_t2: trim@58,0 {
657					reg = <0x58 1>;
658					bits = <0 4>;
659				};
660				usb_sel_t3: trim@59,0 {
661					reg = <0x59 1>;
662					bits = <0 4>;
663				};
664				usb_hs_i0: trim@56,0 {
665					reg = <0x56 1>;
666					bits = <0 4>;
667				};
668				usb_hs_i2: trim@5a,0 {
669					reg = <0x5a 1>;
670					bits = <0 4>;
671				};
672			};
673		};
674
675		xdmac: dma-controller@5fc10000 {
676			compatible = "socionext,uniphier-xdmac";
677			reg = <0x5fc10000 0x5300>;
678			interrupts = <0 188 4>;
679			dma-channels = <16>;
680			#dma-cells = <2>;
681		};
682
683		aidet: interrupt-controller@5fc20000 {
684			compatible = "socionext,uniphier-ld20-aidet";
685			reg = <0x5fc20000 0x200>;
686			interrupt-controller;
687			#interrupt-cells = <2>;
688		};
689
690		gic: interrupt-controller@5fe00000 {
691			compatible = "arm,gic-v3";
692			reg = <0x5fe00000 0x10000>,	/* GICD */
693			      <0x5fe80000 0x80000>;	/* GICR */
694			interrupt-controller;
695			#interrupt-cells = <3>;
696			interrupts = <1 9 4>;
697		};
698
699		sysctrl@61840000 {
700			compatible = "socionext,uniphier-ld20-sysctrl",
701				     "simple-mfd", "syscon";
702			reg = <0x61840000 0x10000>;
703
704			sys_clk: clock {
705				compatible = "socionext,uniphier-ld20-clock";
706				#clock-cells = <1>;
707			};
708
709			sys_rst: reset {
710				compatible = "socionext,uniphier-ld20-reset";
711				#reset-cells = <1>;
712			};
713
714			watchdog {
715				compatible = "socionext,uniphier-wdt";
716			};
717
718			pvtctl: pvtctl {
719				compatible = "socionext,uniphier-ld20-thermal";
720				interrupts = <0 3 4>;
721				#thermal-sensor-cells = <0>;
722				socionext,tmod-calibration = <0x0f22 0x68ee>;
723			};
724		};
725
726		eth: ethernet@65000000 {
727			compatible = "socionext,uniphier-ld20-ave4";
728			status = "disabled";
729			reg = <0x65000000 0x8500>;
730			interrupts = <0 66 4>;
731			pinctrl-names = "default";
732			pinctrl-0 = <&pinctrl_ether_rgmii>;
733			clock-names = "ether";
734			clocks = <&sys_clk 6>;
735			reset-names = "ether";
736			resets = <&sys_rst 6>;
737			phy-mode = "rgmii-id";
738			local-mac-address = [00 00 00 00 00 00];
739			socionext,syscon-phy-mode = <&soc_glue 0>;
740
741			mdio: mdio {
742				#address-cells = <1>;
743				#size-cells = <0>;
744			};
745		};
746
747		usb: usb@65a00000 {
748			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
749			status = "disabled";
750			reg = <0x65a00000 0xcd00>;
751			interrupt-names = "host";
752			interrupts = <0 134 4>;
753			pinctrl-names = "default";
754			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
755				    <&pinctrl_usb2>, <&pinctrl_usb3>;
756			clock-names = "ref", "bus_early", "suspend";
757			clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
758			resets = <&usb_rst 15>;
759			phys = <&usb_hsphy0>, <&usb_hsphy1>,
760			       <&usb_hsphy2>, <&usb_hsphy3>,
761			       <&usb_ssphy0>, <&usb_ssphy1>;
762			dr_mode = "host";
763		};
764
765		usb-glue@65b00000 {
766			compatible = "socionext,uniphier-ld20-dwc3-glue",
767				     "simple-mfd";
768			#address-cells = <1>;
769			#size-cells = <1>;
770			ranges = <0 0x65b00000 0x400>;
771
772			usb_rst: reset@0 {
773				compatible = "socionext,uniphier-ld20-usb3-reset";
774				reg = <0x0 0x4>;
775				#reset-cells = <1>;
776				clock-names = "link";
777				clocks = <&sys_clk 14>;
778				reset-names = "link";
779				resets = <&sys_rst 14>;
780			};
781
782			usb_vbus0: regulator@100 {
783				compatible = "socionext,uniphier-ld20-usb3-regulator";
784				reg = <0x100 0x10>;
785				clock-names = "link";
786				clocks = <&sys_clk 14>;
787				reset-names = "link";
788				resets = <&sys_rst 14>;
789			};
790
791			usb_vbus1: regulator@110 {
792				compatible = "socionext,uniphier-ld20-usb3-regulator";
793				reg = <0x110 0x10>;
794				clock-names = "link";
795				clocks = <&sys_clk 14>;
796				reset-names = "link";
797				resets = <&sys_rst 14>;
798			};
799
800			usb_vbus2: regulator@120 {
801				compatible = "socionext,uniphier-ld20-usb3-regulator";
802				reg = <0x120 0x10>;
803				clock-names = "link";
804				clocks = <&sys_clk 14>;
805				reset-names = "link";
806				resets = <&sys_rst 14>;
807			};
808
809			usb_vbus3: regulator@130 {
810				compatible = "socionext,uniphier-ld20-usb3-regulator";
811				reg = <0x130 0x10>;
812				clock-names = "link";
813				clocks = <&sys_clk 14>;
814				reset-names = "link";
815				resets = <&sys_rst 14>;
816			};
817
818			usb_hsphy0: hs-phy@200 {
819				compatible = "socionext,uniphier-ld20-usb3-hsphy";
820				reg = <0x200 0x10>;
821				#phy-cells = <0>;
822				clock-names = "link", "phy";
823				clocks = <&sys_clk 14>, <&sys_clk 16>;
824				reset-names = "link", "phy";
825				resets = <&sys_rst 14>, <&sys_rst 16>;
826				vbus-supply = <&usb_vbus0>;
827				nvmem-cell-names = "rterm", "sel_t", "hs_i";
828				nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
829					      <&usb_hs_i0>;
830			};
831
832			usb_hsphy1: hs-phy@210 {
833				compatible = "socionext,uniphier-ld20-usb3-hsphy";
834				reg = <0x210 0x10>;
835				#phy-cells = <0>;
836				clock-names = "link", "phy";
837				clocks = <&sys_clk 14>, <&sys_clk 16>;
838				reset-names = "link", "phy";
839				resets = <&sys_rst 14>, <&sys_rst 16>;
840				vbus-supply = <&usb_vbus1>;
841				nvmem-cell-names = "rterm", "sel_t", "hs_i";
842				nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
843					      <&usb_hs_i0>;
844			};
845
846			usb_hsphy2: hs-phy@220 {
847				compatible = "socionext,uniphier-ld20-usb3-hsphy";
848				reg = <0x220 0x10>;
849				#phy-cells = <0>;
850				clock-names = "link", "phy";
851				clocks = <&sys_clk 14>, <&sys_clk 17>;
852				reset-names = "link", "phy";
853				resets = <&sys_rst 14>, <&sys_rst 17>;
854				vbus-supply = <&usb_vbus2>;
855				nvmem-cell-names = "rterm", "sel_t", "hs_i";
856				nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
857					      <&usb_hs_i2>;
858			};
859
860			usb_hsphy3: hs-phy@230 {
861				compatible = "socionext,uniphier-ld20-usb3-hsphy";
862				reg = <0x230 0x10>;
863				#phy-cells = <0>;
864				clock-names = "link", "phy";
865				clocks = <&sys_clk 14>, <&sys_clk 17>;
866				reset-names = "link", "phy";
867				resets = <&sys_rst 14>, <&sys_rst 17>;
868				vbus-supply = <&usb_vbus3>;
869				nvmem-cell-names = "rterm", "sel_t", "hs_i";
870				nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
871					      <&usb_hs_i2>;
872			};
873
874			usb_ssphy0: ss-phy@300 {
875				compatible = "socionext,uniphier-ld20-usb3-ssphy";
876				reg = <0x300 0x10>;
877				#phy-cells = <0>;
878				clock-names = "link", "phy";
879				clocks = <&sys_clk 14>, <&sys_clk 18>;
880				reset-names = "link", "phy";
881				resets = <&sys_rst 14>, <&sys_rst 18>;
882				vbus-supply = <&usb_vbus0>;
883			};
884
885			usb_ssphy1: ss-phy@310 {
886				compatible = "socionext,uniphier-ld20-usb3-ssphy";
887				reg = <0x310 0x10>;
888				#phy-cells = <0>;
889				clock-names = "link", "phy";
890				clocks = <&sys_clk 14>, <&sys_clk 19>;
891				reset-names = "link", "phy";
892				resets = <&sys_rst 14>, <&sys_rst 19>;
893				vbus-supply = <&usb_vbus1>;
894			};
895		};
896
897		pcie: pcie@66000000 {
898			compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
899			status = "disabled";
900			reg-names = "dbi", "link", "config";
901			reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
902			      <0x2fff0000 0x10000>;
903			#address-cells = <3>;
904			#size-cells = <2>;
905			clocks = <&sys_clk 24>;
906			resets = <&sys_rst 24>;
907			num-lanes = <1>;
908			num-viewport = <1>;
909			bus-range = <0x0 0xff>;
910			device_type = "pci";
911			ranges =
912			/* downstream I/O */
913				<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
914			/* non-prefetchable memory */
915				<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
916			#interrupt-cells = <1>;
917			interrupt-names = "dma", "msi";
918			interrupts = <0 224 4>, <0 225 4>;
919			interrupt-map-mask = <0 0 0 7>;
920			interrupt-map = <0 0 0 1 &pcie_intc 0>,	/* INTA */
921					<0 0 0 2 &pcie_intc 1>,	/* INTB */
922					<0 0 0 3 &pcie_intc 2>,	/* INTC */
923					<0 0 0 4 &pcie_intc 3>;	/* INTD */
924			phy-names = "pcie-phy";
925			phys = <&pcie_phy>;
926
927			pcie_intc: legacy-interrupt-controller {
928				interrupt-controller;
929				#interrupt-cells = <1>;
930				interrupt-parent = <&gic>;
931				interrupts = <0 226 4>;
932			};
933		};
934
935		pcie_phy: phy@66038000 {
936			compatible = "socionext,uniphier-ld20-pcie-phy";
937			reg = <0x66038000 0x4000>;
938			#phy-cells = <0>;
939			clock-names = "link";
940			clocks = <&sys_clk 24>;
941			reset-names = "link";
942			resets = <&sys_rst 24>;
943			socionext,syscon = <&soc_glue>;
944		};
945
946		nand: nand-controller@68000000 {
947			compatible = "socionext,uniphier-denali-nand-v5b";
948			status = "disabled";
949			reg-names = "nand_data", "denali_reg";
950			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
951			#address-cells = <1>;
952			#size-cells = <0>;
953			interrupts = <0 65 4>;
954			pinctrl-names = "default";
955			pinctrl-0 = <&pinctrl_nand>;
956			clock-names = "nand", "nand_x", "ecc";
957			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
958			reset-names = "nand", "reg";
959			resets = <&sys_rst 2>, <&sys_rst 2>;
960		};
961	};
962};
963
964#include "uniphier-pinctrl.dtsi"
965
966&pinctrl_aout1 {
967	drive-strength = <4>;	/* default: 3.5mA */
968
969	ao1dacck {
970		pins = "AO1DACCK";
971		drive-strength = <5>;	/* 5mA */
972	};
973};
974
975&pinctrl_aoutiec1 {
976	drive-strength = <4>;	/* default: 3.5mA */
977
978	ao1arc {
979		pins = "AO1ARC";
980		drive-strength = <11>;	/* 11mA */
981	};
982};
983