xref: /linux/arch/arm64/boot/dts/sprd/sc9863a.dtsi (revision f86fd32d) 
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Unisoc SC9863A SoC DTS file
4 *
5 * Copyright (C) 2019, Unisoc Inc.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "sharkl3.dtsi"
10
11/ {
12	cpus {
13		#address-cells = <2>;
14		#size-cells = <0>;
15
16		cpu-map {
17			cluster0 {
18				core0 {
19					cpu = <&CPU0>;
20				};
21				core1 {
22					cpu = <&CPU1>;
23				};
24				core2 {
25					cpu = <&CPU2>;
26				};
27				core3 {
28					cpu = <&CPU3>;
29				};
30				core4 {
31					cpu = <&CPU4>;
32				};
33				core5 {
34					cpu = <&CPU5>;
35				};
36				core6 {
37					cpu = <&CPU6>;
38				};
39				core7 {
40					cpu = <&CPU7>;
41				};
42			};
43		};
44
45		CPU0: cpu@0 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a55";
48			reg = <0x0 0x0>;
49			enable-method = "psci";
50			cpu-idle-states = <&CORE_PD>;
51		};
52
53		CPU1: cpu@100 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a55";
56			reg = <0x0 0x100>;
57			enable-method = "psci";
58			cpu-idle-states = <&CORE_PD>;
59		};
60
61		CPU2: cpu@200 {
62			device_type = "cpu";
63			compatible = "arm,cortex-a55";
64			reg = <0x0 0x200>;
65			enable-method = "psci";
66			cpu-idle-states = <&CORE_PD>;
67		};
68
69		CPU3: cpu@300 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a55";
72			reg = <0x0 0x300>;
73			enable-method = "psci";
74			cpu-idle-states = <&CORE_PD>;
75		};
76
77		CPU4: cpu@400 {
78			device_type = "cpu";
79			compatible = "arm,cortex-a55";
80			reg = <0x0 0x400>;
81			enable-method = "psci";
82			cpu-idle-states = <&CORE_PD>;
83		};
84
85		CPU5: cpu@500 {
86			device_type = "cpu";
87			compatible = "arm,cortex-a55";
88			reg = <0x0 0x500>;
89			enable-method = "psci";
90			cpu-idle-states = <&CORE_PD>;
91		};
92
93		CPU6: cpu@600 {
94			device_type = "cpu";
95			compatible = "arm,cortex-a55";
96			reg = <0x0 0x600>;
97			enable-method = "psci";
98			cpu-idle-states = <&CORE_PD>;
99		};
100
101		CPU7: cpu@700 {
102			device_type = "cpu";
103			compatible = "arm,cortex-a55";
104			reg = <0x0 0x700>;
105			enable-method = "psci";
106			cpu-idle-states = <&CORE_PD>;
107		};
108	};
109
110	idle-states {
111		entry-method = "arm,psci";
112		CORE_PD: core-pd {
113			compatible = "arm,idle-state";
114			entry-latency-us = <4000>;
115			exit-latency-us = <4000>;
116			min-residency-us = <10000>;
117			local-timer-stop;
118			arm,psci-suspend-param = <0x00010000>;
119		};
120	};
121
122	psci {
123		compatible = "arm,psci-0.2";
124		method = "smc";
125	};
126
127	timer {
128		compatible = "arm,armv8-timer";
129		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
130			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
131			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
132			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
133	};
134
135	pmu {
136		compatible = "arm,armv8-pmuv3";
137		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
138			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
139			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
140			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
141			     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
142			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
143			     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
144			     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
145	};
146
147	soc {
148		gic: interrupt-controller@14000000 {
149			compatible = "arm,gic-v3";
150			#interrupt-cells = <3>;
151			#address-cells = <2>;
152			#size-cells = <2>;
153			ranges;
154			redistributor-stride = <0x0 0x20000>;	/* 128KB stride */
155			#redistributor-regions = <1>;
156			interrupt-controller;
157			reg = <0x0 0x14000000 0 0x20000>,	/* GICD */
158			      <0x0 0x14040000 0 0x100000>;	/* GICR */
159			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
160		};
161
162		funnel@10001000 {
163			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
164			reg = <0 0x10001000 0 0x1000>;
165			clocks = <&ext_26m>;
166			clock-names = "apb_pclk";
167
168			out-ports {
169				port {
170					funnel_soc_out_port: endpoint {
171						remote-endpoint = <&etb_in>;
172					};
173				};
174			};
175
176			in-ports {
177				port {
178					funnel_soc_in_port: endpoint {
179						remote-endpoint =
180						<&funnel_ca55_out_port>;
181					};
182				};
183			};
184		};
185
186		etb@10003000 {
187			compatible = "arm,coresight-tmc", "arm,primecell";
188			reg = <0 0x10003000 0 0x1000>;
189			clocks = <&ext_26m>;
190			clock-names = "apb_pclk";
191
192			in-ports {
193				port {
194					etb_in: endpoint {
195						remote-endpoint =
196						<&funnel_soc_out_port>;
197					};
198				};
199			};
200		};
201
202		funnel@12001000 {
203			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
204			reg = <0 0x12001000 0 0x1000>;
205			clocks = <&ext_26m>;
206			clock-names = "apb_pclk";
207
208			out-ports {
209				port {
210					funnel_little_out_port: endpoint {
211						remote-endpoint =
212						<&etf_little_in>;
213					};
214				};
215			};
216
217			in-ports {
218				#address-cells = <1>;
219				#size-cells = <0>;
220
221				port@0 {
222					reg = <0>;
223					funnel_little_in_port0: endpoint {
224						remote-endpoint = <&etm0_out>;
225					};
226				};
227
228				port@1 {
229					reg = <1>;
230					funnel_little_in_port1: endpoint {
231						remote-endpoint = <&etm1_out>;
232					};
233				};
234
235				port@2 {
236					reg = <2>;
237					funnel_little_in_port2: endpoint {
238						remote-endpoint = <&etm2_out>;
239					};
240				};
241
242				port@3 {
243					reg = <3>;
244					funnel_little_in_port3: endpoint {
245						remote-endpoint = <&etm3_out>;
246					};
247				};
248			};
249		};
250
251		etf@12002000 {
252			compatible = "arm,coresight-tmc", "arm,primecell";
253			reg = <0 0x12002000 0 0x1000>;
254			clocks = <&ext_26m>;
255			clock-names = "apb_pclk";
256
257			out-ports {
258				port {
259					etf_little_out: endpoint {
260						remote-endpoint =
261						<&funnel_ca55_in_port0>;
262					};
263				};
264			};
265
266			in-port {
267				port {
268					etf_little_in: endpoint {
269						remote-endpoint =
270						<&funnel_little_out_port>;
271					};
272				};
273			};
274		};
275
276		etf@12003000 {
277			compatible = "arm,coresight-tmc", "arm,primecell";
278			reg = <0 0x12003000 0 0x1000>;
279			clocks = <&ext_26m>;
280			clock-names = "apb_pclk";
281
282			out-ports {
283				port {
284					etf_big_out: endpoint {
285						remote-endpoint =
286						<&funnel_ca55_in_port1>;
287					};
288				};
289			};
290
291			in-ports {
292				port {
293					etf_big_in: endpoint {
294						remote-endpoint =
295						<&funnel_big_out_port>;
296					};
297				};
298			};
299		};
300
301		funnel@12004000 {
302			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
303			reg = <0 0x12004000 0 0x1000>;
304			clocks = <&ext_26m>;
305			clock-names = "apb_pclk";
306
307			out-ports {
308				port {
309					funnel_ca55_out_port: endpoint {
310						remote-endpoint =
311						<&funnel_soc_in_port>;
312					};
313				};
314			};
315
316			in-ports {
317				#address-cells = <1>;
318				#size-cells = <0>;
319
320				port@0 {
321					reg = <0>;
322					funnel_ca55_in_port0: endpoint {
323						remote-endpoint =
324						<&etf_little_out>;
325					};
326				};
327
328				port@1 {
329					reg = <1>;
330					funnel_ca55_in_port1: endpoint {
331						remote-endpoint =
332						<&etf_big_out>;
333					};
334				};
335			};
336		};
337
338		funnel@12005000 {
339			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
340			reg = <0 0x12005000 0 0x1000>;
341			clocks = <&ext_26m>;
342			clock-names = "apb_pclk";
343
344			out-ports {
345				port {
346					funnel_big_out_port: endpoint {
347						remote-endpoint =
348						<&etf_big_in>;
349					};
350				};
351			};
352
353			in-ports {
354				#address-cells = <1>;
355				#size-cells = <0>;
356
357				port@0 {
358					reg = <0>;
359					funnel_big_in_port0: endpoint {
360						remote-endpoint = <&etm4_out>;
361					};
362				};
363
364				port@1 {
365					reg = <1>;
366					funnel_big_in_port1: endpoint {
367						remote-endpoint = <&etm5_out>;
368					};
369				};
370
371				port@2 {
372					reg = <2>;
373					funnel_big_in_port2: endpoint {
374						remote-endpoint = <&etm6_out>;
375					};
376				};
377
378				port@3 {
379					reg = <3>;
380					funnel_big_in_port3: endpoint {
381						remote-endpoint = <&etm7_out>;
382					};
383				};
384			};
385		};
386
387		etm@13040000 {
388			compatible = "arm,coresight-etm4x", "arm,primecell";
389			reg = <0 0x13040000 0 0x1000>;
390			cpu = <&CPU0>;
391			clocks = <&ext_26m>;
392			clock-names = "apb_pclk";
393
394			out-ports {
395				port {
396					etm0_out: endpoint {
397						remote-endpoint =
398						<&funnel_little_in_port0>;
399					};
400				};
401			};
402		};
403
404		etm@13140000 {
405			compatible = "arm,coresight-etm4x", "arm,primecell";
406			reg = <0 0x13140000 0 0x1000>;
407			cpu = <&CPU1>;
408			clocks = <&ext_26m>;
409			clock-names = "apb_pclk";
410
411			out-ports {
412				port {
413					etm1_out: endpoint {
414						remote-endpoint =
415						<&funnel_little_in_port1>;
416					};
417				};
418			};
419		};
420
421		etm@13240000 {
422			compatible = "arm,coresight-etm4x", "arm,primecell";
423			reg = <0 0x13240000 0 0x1000>;
424			cpu = <&CPU2>;
425			clocks = <&ext_26m>;
426			clock-names = "apb_pclk";
427
428			out-ports {
429				port {
430					etm2_out: endpoint {
431						remote-endpoint =
432						<&funnel_little_in_port2>;
433					};
434				};
435			};
436		};
437
438		etm@13340000 {
439			compatible = "arm,coresight-etm4x", "arm,primecell";
440			reg = <0 0x13340000 0 0x1000>;
441			cpu = <&CPU3>;
442			clocks = <&ext_26m>;
443			clock-names = "apb_pclk";
444
445			out-ports {
446				port {
447					etm3_out: endpoint {
448						remote-endpoint =
449						<&funnel_little_in_port3>;
450					};
451				};
452			};
453		};
454
455		etm@13440000 {
456			compatible = "arm,coresight-etm4x", "arm,primecell";
457			reg = <0 0x13440000 0 0x1000>;
458			cpu = <&CPU4>;
459			clocks = <&ext_26m>;
460			clock-names = "apb_pclk";
461
462			out-ports {
463				port {
464					etm4_out: endpoint {
465						remote-endpoint =
466						<&funnel_big_in_port0>;
467					};
468				};
469			};
470		};
471
472		etm@13540000 {
473			compatible = "arm,coresight-etm4x", "arm,primecell";
474			reg = <0 0x13540000 0 0x1000>;
475			cpu = <&CPU5>;
476			clocks = <&ext_26m>;
477			clock-names = "apb_pclk";
478
479			out-ports {
480				port {
481					etm5_out: endpoint {
482						remote-endpoint =
483						<&funnel_big_in_port1>;
484					};
485				};
486			};
487		};
488
489		etm@13640000 {
490			compatible = "arm,coresight-etm4x", "arm,primecell";
491			reg = <0 0x13640000 0 0x1000>;
492			cpu = <&CPU6>;
493			clocks = <&ext_26m>;
494			clock-names = "apb_pclk";
495
496			out-ports {
497				port {
498					etm6_out: endpoint {
499						remote-endpoint =
500						<&funnel_big_in_port2>;
501					};
502				};
503			};
504		};
505
506		etm@13740000 {
507			compatible = "arm,coresight-etm4x", "arm,primecell";
508			reg = <0 0x13740000 0 0x1000>;
509			cpu = <&CPU7>;
510			clocks = <&ext_26m>;
511			clock-names = "apb_pclk";
512
513			out-ports {
514				port {
515					etm7_out: endpoint {
516						remote-endpoint =
517						<&funnel_big_in_port3>;
518					};
519				};
520			};
521		};
522	};
523};
524