1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a35"; 18 device_type = "cpu"; 19 reg = <0>; 20 enable-method = "psci"; 21 }; 22 }; 23 24 arm-pmu { 25 compatible = "arm,cortex-a35-pmu"; 26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-affinity = <&cpu0>; 28 interrupt-parent = <&intc>; 29 }; 30 31 arm_wdt: watchdog { 32 compatible = "arm,smc-wdt"; 33 arm,smc-id = <0xb200005a>; 34 status = "disabled"; 35 }; 36 37 clocks { 38 ck_flexgen_08: ck-flexgen-08 { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <100000000>; 42 }; 43 44 ck_flexgen_51: ck-flexgen-51 { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <200000000>; 48 }; 49 50 ck_icn_ls_mcu: ck-icn-ls-mcu { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <200000000>; 54 }; 55 }; 56 57 firmware { 58 optee { 59 compatible = "linaro,optee-tz"; 60 method = "smc"; 61 }; 62 63 scmi { 64 compatible = "linaro,scmi-optee"; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 linaro,optee-channel-id = <0>; 68 69 scmi_clk: protocol@14 { 70 reg = <0x14>; 71 #clock-cells = <1>; 72 }; 73 74 scmi_reset: protocol@16 { 75 reg = <0x16>; 76 #reset-cells = <1>; 77 }; 78 }; 79 }; 80 81 intc: interrupt-controller@4ac00000 { 82 compatible = "arm,cortex-a7-gic"; 83 #interrupt-cells = <3>; 84 #address-cells = <1>; 85 interrupt-controller; 86 reg = <0x0 0x4ac10000 0x0 0x1000>, 87 <0x0 0x4ac20000 0x0 0x2000>, 88 <0x0 0x4ac40000 0x0 0x2000>, 89 <0x0 0x4ac60000 0x0 0x2000>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupt-parent = <&intc>; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 104 always-on; 105 }; 106 107 soc@0 { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 interrupt-parent = <&intc>; 112 ranges = <0x0 0x0 0x0 0x80000000>; 113 114 rifsc: rifsc-bus@42080000 { 115 compatible = "simple-bus"; 116 reg = <0x42080000 0x1000>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 121 usart2: serial@400e0000 { 122 compatible = "st,stm32h7-uart"; 123 reg = <0x400e0000 0x400>; 124 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&ck_flexgen_08>; 126 status = "disabled"; 127 }; 128 129 sdmmc1: mmc@48220000 { 130 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 131 arm,primecell-periphid = <0x00353180>; 132 reg = <0x48220000 0x400>, <0x44230400 0x8>; 133 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&ck_flexgen_51>; 135 clock-names = "apb_pclk"; 136 cap-sd-highspeed; 137 cap-mmc-highspeed; 138 max-frequency = <120000000>; 139 status = "disabled"; 140 }; 141 }; 142 143 syscfg: syscon@44230000 { 144 compatible = "st,stm32mp25-syscfg", "syscon"; 145 reg = <0x44230000 0x10000>; 146 }; 147 148 pinctrl: pinctrl@44240000 { 149 #address-cells = <1>; 150 #size-cells = <1>; 151 compatible = "st,stm32mp257-pinctrl"; 152 ranges = <0 0x44240000 0xa0400>; 153 pins-are-numbered; 154 155 gpioa: gpio@44240000 { 156 gpio-controller; 157 #gpio-cells = <2>; 158 interrupt-controller; 159 #interrupt-cells = <2>; 160 reg = <0x0 0x400>; 161 clocks = <&ck_icn_ls_mcu>; 162 st,bank-name = "GPIOA"; 163 status = "disabled"; 164 }; 165 166 gpiob: gpio@44250000 { 167 gpio-controller; 168 #gpio-cells = <2>; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 reg = <0x10000 0x400>; 172 clocks = <&ck_icn_ls_mcu>; 173 st,bank-name = "GPIOB"; 174 status = "disabled"; 175 }; 176 177 gpioc: gpio@44260000 { 178 gpio-controller; 179 #gpio-cells = <2>; 180 interrupt-controller; 181 #interrupt-cells = <2>; 182 reg = <0x20000 0x400>; 183 clocks = <&ck_icn_ls_mcu>; 184 st,bank-name = "GPIOC"; 185 status = "disabled"; 186 }; 187 188 gpiod: gpio@44270000 { 189 gpio-controller; 190 #gpio-cells = <2>; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 reg = <0x30000 0x400>; 194 clocks = <&ck_icn_ls_mcu>; 195 st,bank-name = "GPIOD"; 196 status = "disabled"; 197 }; 198 199 gpioe: gpio@44280000 { 200 gpio-controller; 201 #gpio-cells = <2>; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 reg = <0x40000 0x400>; 205 clocks = <&ck_icn_ls_mcu>; 206 st,bank-name = "GPIOE"; 207 status = "disabled"; 208 }; 209 210 gpiof: gpio@44290000 { 211 gpio-controller; 212 #gpio-cells = <2>; 213 interrupt-controller; 214 #interrupt-cells = <2>; 215 reg = <0x50000 0x400>; 216 clocks = <&ck_icn_ls_mcu>; 217 st,bank-name = "GPIOF"; 218 status = "disabled"; 219 }; 220 221 gpiog: gpio@442a0000 { 222 gpio-controller; 223 #gpio-cells = <2>; 224 interrupt-controller; 225 #interrupt-cells = <2>; 226 reg = <0x60000 0x400>; 227 clocks = <&ck_icn_ls_mcu>; 228 st,bank-name = "GPIOG"; 229 status = "disabled"; 230 }; 231 232 gpioh: gpio@442b0000 { 233 gpio-controller; 234 #gpio-cells = <2>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 reg = <0x70000 0x400>; 238 clocks = <&ck_icn_ls_mcu>; 239 st,bank-name = "GPIOH"; 240 status = "disabled"; 241 }; 242 243 gpioi: gpio@442c0000 { 244 gpio-controller; 245 #gpio-cells = <2>; 246 interrupt-controller; 247 #interrupt-cells = <2>; 248 reg = <0x80000 0x400>; 249 clocks = <&ck_icn_ls_mcu>; 250 st,bank-name = "GPIOI"; 251 status = "disabled"; 252 }; 253 254 gpioj: gpio@442d0000 { 255 gpio-controller; 256 #gpio-cells = <2>; 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 reg = <0x90000 0x400>; 260 clocks = <&ck_icn_ls_mcu>; 261 st,bank-name = "GPIOJ"; 262 status = "disabled"; 263 }; 264 265 gpiok: gpio@442e0000 { 266 gpio-controller; 267 #gpio-cells = <2>; 268 interrupt-controller; 269 #interrupt-cells = <2>; 270 reg = <0xa0000 0x400>; 271 clocks = <&ck_icn_ls_mcu>; 272 st,bank-name = "GPIOK"; 273 status = "disabled"; 274 }; 275 }; 276 277 pinctrl_z: pinctrl@46200000 { 278 #address-cells = <1>; 279 #size-cells = <1>; 280 compatible = "st,stm32mp257-z-pinctrl"; 281 ranges = <0 0x46200000 0x400>; 282 pins-are-numbered; 283 284 gpioz: gpio@46200000 { 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 reg = <0 0x400>; 290 clocks = <&ck_icn_ls_mcu>; 291 st,bank-name = "GPIOZ"; 292 st,bank-ioport = <11>; 293 status = "disabled"; 294 }; 295 296 }; 297 }; 298}; 299