1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/mux/ti-serdes.h> 10 11/ { 12 cmn_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 18 cmn_refclk1: clock-cmnrefclk1 { 19 #clock-cells = <0>; 20 compatible = "fixed-clock"; 21 clock-frequency = <0>; 22 }; 23}; 24 25&cbass_main { 26 msmc_ram: sram@70000000 { 27 compatible = "mmio-sram"; 28 reg = <0x0 0x70000000 0x0 0x800000>; 29 #address-cells = <1>; 30 #size-cells = <1>; 31 ranges = <0x0 0x0 0x70000000 0x800000>; 32 33 atf-sram@0 { 34 reg = <0x0 0x20000>; 35 }; 36 }; 37 38 scm_conf: scm-conf@100000 { 39 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 41 #address-cells = <1>; 42 #size-cells = <1>; 43 ranges = <0x0 0x0 0x00100000 0x1c000>; 44 45 serdes_ln_ctrl: mux-controller@4080 { 46 compatible = "mmio-mux"; 47 reg = <0x00004080 0x50>; 48 #mux-control-cells = <1>; 49 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 50 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ 51 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ 52 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */ 53 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; 54 /* SERDES4 lane0/1/2/3 select */ 55 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 56 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 57 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 58 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 59 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 60 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 61 }; 62 63 usb_serdes_mux: mux-controller@4000 { 64 compatible = "mmio-mux"; 65 #mux-control-cells = <1>; 66 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ 67 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ 68 }; 69 }; 70 71 gic500: interrupt-controller@1800000 { 72 compatible = "arm,gic-v3"; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 #interrupt-cells = <3>; 77 interrupt-controller; 78 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 79 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 80 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 81 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 82 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 83 84 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 85 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 86 87 gic_its: msi-controller@1820000 { 88 compatible = "arm,gic-v3-its"; 89 reg = <0x00 0x01820000 0x00 0x10000>; 90 socionext,synquacer-pre-its = <0x1000000 0x400000>; 91 msi-controller; 92 #msi-cells = <1>; 93 }; 94 }; 95 96 main_gpio_intr: interrupt-controller@a00000 { 97 compatible = "ti,sci-intr"; 98 reg = <0x00 0x00a00000 0x00 0x800>; 99 ti,intr-trigger-type = <1>; 100 interrupt-controller; 101 interrupt-parent = <&gic500>; 102 #interrupt-cells = <1>; 103 ti,sci = <&dmsc>; 104 ti,sci-dev-id = <131>; 105 ti,interrupt-ranges = <8 392 56>; 106 }; 107 108 main_navss: bus@30000000 { 109 compatible = "simple-mfd"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 113 dma-coherent; 114 dma-ranges; 115 116 ti,sci-dev-id = <199>; 117 118 main_navss_intr: interrupt-controller@310e0000 { 119 compatible = "ti,sci-intr"; 120 reg = <0x0 0x310e0000 0x0 0x4000>; 121 ti,intr-trigger-type = <4>; 122 interrupt-controller; 123 interrupt-parent = <&gic500>; 124 #interrupt-cells = <1>; 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <213>; 127 ti,interrupt-ranges = <0 64 64>, 128 <64 448 64>, 129 <128 672 64>; 130 }; 131 132 main_udmass_inta: interrupt-controller@33d00000 { 133 compatible = "ti,sci-inta"; 134 reg = <0x0 0x33d00000 0x0 0x100000>; 135 interrupt-controller; 136 interrupt-parent = <&main_navss_intr>; 137 msi-controller; 138 #interrupt-cells = <0>; 139 ti,sci = <&dmsc>; 140 ti,sci-dev-id = <209>; 141 ti,interrupt-ranges = <0 0 256>; 142 }; 143 144 secure_proxy_main: mailbox@32c00000 { 145 compatible = "ti,am654-secure-proxy"; 146 #mbox-cells = <1>; 147 reg-names = "target_data", "rt", "scfg"; 148 reg = <0x00 0x32c00000 0x00 0x100000>, 149 <0x00 0x32400000 0x00 0x100000>, 150 <0x00 0x32800000 0x00 0x100000>; 151 interrupt-names = "rx_011"; 152 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 smmu0: iommu@36600000 { 156 compatible = "arm,smmu-v3"; 157 reg = <0x0 0x36600000 0x0 0x100000>; 158 interrupt-parent = <&gic500>; 159 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 160 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 161 interrupt-names = "eventq", "gerror"; 162 #iommu-cells = <1>; 163 }; 164 165 hwspinlock: spinlock@30e00000 { 166 compatible = "ti,am654-hwspinlock"; 167 reg = <0x00 0x30e00000 0x00 0x1000>; 168 #hwlock-cells = <1>; 169 }; 170 171 mailbox0_cluster0: mailbox@31f80000 { 172 compatible = "ti,am654-mailbox"; 173 reg = <0x00 0x31f80000 0x00 0x200>; 174 #mbox-cells = <1>; 175 ti,mbox-num-users = <4>; 176 ti,mbox-num-fifos = <16>; 177 interrupt-parent = <&main_navss_intr>; 178 }; 179 180 mailbox0_cluster1: mailbox@31f81000 { 181 compatible = "ti,am654-mailbox"; 182 reg = <0x00 0x31f81000 0x00 0x200>; 183 #mbox-cells = <1>; 184 ti,mbox-num-users = <4>; 185 ti,mbox-num-fifos = <16>; 186 interrupt-parent = <&main_navss_intr>; 187 }; 188 189 mailbox0_cluster2: mailbox@31f82000 { 190 compatible = "ti,am654-mailbox"; 191 reg = <0x00 0x31f82000 0x00 0x200>; 192 #mbox-cells = <1>; 193 ti,mbox-num-users = <4>; 194 ti,mbox-num-fifos = <16>; 195 interrupt-parent = <&main_navss_intr>; 196 }; 197 198 mailbox0_cluster3: mailbox@31f83000 { 199 compatible = "ti,am654-mailbox"; 200 reg = <0x00 0x31f83000 0x00 0x200>; 201 #mbox-cells = <1>; 202 ti,mbox-num-users = <4>; 203 ti,mbox-num-fifos = <16>; 204 interrupt-parent = <&main_navss_intr>; 205 }; 206 207 mailbox0_cluster4: mailbox@31f84000 { 208 compatible = "ti,am654-mailbox"; 209 reg = <0x00 0x31f84000 0x00 0x200>; 210 #mbox-cells = <1>; 211 ti,mbox-num-users = <4>; 212 ti,mbox-num-fifos = <16>; 213 interrupt-parent = <&main_navss_intr>; 214 }; 215 216 mailbox0_cluster5: mailbox@31f85000 { 217 compatible = "ti,am654-mailbox"; 218 reg = <0x00 0x31f85000 0x00 0x200>; 219 #mbox-cells = <1>; 220 ti,mbox-num-users = <4>; 221 ti,mbox-num-fifos = <16>; 222 interrupt-parent = <&main_navss_intr>; 223 }; 224 225 mailbox0_cluster6: mailbox@31f86000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f86000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 }; 233 234 mailbox0_cluster7: mailbox@31f87000 { 235 compatible = "ti,am654-mailbox"; 236 reg = <0x00 0x31f87000 0x00 0x200>; 237 #mbox-cells = <1>; 238 ti,mbox-num-users = <4>; 239 ti,mbox-num-fifos = <16>; 240 interrupt-parent = <&main_navss_intr>; 241 }; 242 243 mailbox0_cluster8: mailbox@31f88000 { 244 compatible = "ti,am654-mailbox"; 245 reg = <0x00 0x31f88000 0x00 0x200>; 246 #mbox-cells = <1>; 247 ti,mbox-num-users = <4>; 248 ti,mbox-num-fifos = <16>; 249 interrupt-parent = <&main_navss_intr>; 250 }; 251 252 mailbox0_cluster9: mailbox@31f89000 { 253 compatible = "ti,am654-mailbox"; 254 reg = <0x00 0x31f89000 0x00 0x200>; 255 #mbox-cells = <1>; 256 ti,mbox-num-users = <4>; 257 ti,mbox-num-fifos = <16>; 258 interrupt-parent = <&main_navss_intr>; 259 }; 260 261 mailbox0_cluster10: mailbox@31f8a000 { 262 compatible = "ti,am654-mailbox"; 263 reg = <0x00 0x31f8a000 0x00 0x200>; 264 #mbox-cells = <1>; 265 ti,mbox-num-users = <4>; 266 ti,mbox-num-fifos = <16>; 267 interrupt-parent = <&main_navss_intr>; 268 }; 269 270 mailbox0_cluster11: mailbox@31f8b000 { 271 compatible = "ti,am654-mailbox"; 272 reg = <0x00 0x31f8b000 0x00 0x200>; 273 #mbox-cells = <1>; 274 ti,mbox-num-users = <4>; 275 ti,mbox-num-fifos = <16>; 276 interrupt-parent = <&main_navss_intr>; 277 }; 278 279 main_ringacc: ringacc@3c000000 { 280 compatible = "ti,am654-navss-ringacc"; 281 reg = <0x0 0x3c000000 0x0 0x400000>, 282 <0x0 0x38000000 0x0 0x400000>, 283 <0x0 0x31120000 0x0 0x100>, 284 <0x0 0x33000000 0x0 0x40000>; 285 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 286 ti,num-rings = <1024>; 287 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 288 ti,sci = <&dmsc>; 289 ti,sci-dev-id = <211>; 290 msi-parent = <&main_udmass_inta>; 291 }; 292 293 main_udmap: dma-controller@31150000 { 294 compatible = "ti,j721e-navss-main-udmap"; 295 reg = <0x0 0x31150000 0x0 0x100>, 296 <0x0 0x34000000 0x0 0x100000>, 297 <0x0 0x35000000 0x0 0x100000>; 298 reg-names = "gcfg", "rchanrt", "tchanrt"; 299 msi-parent = <&main_udmass_inta>; 300 #dma-cells = <1>; 301 302 ti,sci = <&dmsc>; 303 ti,sci-dev-id = <212>; 304 ti,ringacc = <&main_ringacc>; 305 306 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 307 <0x0f>, /* TX_HCHAN */ 308 <0x10>; /* TX_UHCHAN */ 309 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 310 <0x0b>, /* RX_HCHAN */ 311 <0x0c>; /* RX_UHCHAN */ 312 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 313 }; 314 315 cpts@310d0000 { 316 compatible = "ti,j721e-cpts"; 317 reg = <0x0 0x310d0000 0x0 0x400>; 318 reg-names = "cpts"; 319 clocks = <&k3_clks 201 1>; 320 clock-names = "cpts"; 321 interrupts-extended = <&main_navss_intr 391>; 322 interrupt-names = "cpts"; 323 ti,cpts-periodic-outputs = <6>; 324 ti,cpts-ext-ts-inputs = <8>; 325 }; 326 }; 327 328 main_crypto: crypto@4e00000 { 329 compatible = "ti,j721e-sa2ul"; 330 reg = <0x0 0x4e00000 0x0 0x1200>; 331 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 332 #address-cells = <2>; 333 #size-cells = <2>; 334 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 335 336 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 337 <&main_udmap 0x4001>; 338 dma-names = "tx", "rx1", "rx2"; 339 dma-coherent; 340 341 rng: rng@4e10000 { 342 compatible = "inside-secure,safexcel-eip76"; 343 reg = <0x0 0x4e10000 0x0 0x7d>; 344 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&k3_clks 264 1>; 346 }; 347 }; 348 349 main_pmx0: pinctrl@11c000 { 350 compatible = "pinctrl-single"; 351 /* Proxy 0 addressing */ 352 reg = <0x0 0x11c000 0x0 0x2b4>; 353 #pinctrl-cells = <1>; 354 pinctrl-single,register-width = <32>; 355 pinctrl-single,function-mask = <0xffffffff>; 356 }; 357 358 serdes_wiz0: wiz@5000000 { 359 compatible = "ti,j721e-wiz-16g"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 364 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 365 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 366 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 367 num-lanes = <2>; 368 #reset-cells = <1>; 369 ranges = <0x5000000 0x0 0x5000000 0x10000>; 370 371 wiz0_pll0_refclk: pll0-refclk { 372 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 373 #clock-cells = <0>; 374 assigned-clocks = <&wiz0_pll0_refclk>; 375 assigned-clock-parents = <&k3_clks 292 11>; 376 }; 377 378 wiz0_pll1_refclk: pll1-refclk { 379 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 380 #clock-cells = <0>; 381 assigned-clocks = <&wiz0_pll1_refclk>; 382 assigned-clock-parents = <&k3_clks 292 0>; 383 }; 384 385 wiz0_refclk_dig: refclk-dig { 386 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 387 #clock-cells = <0>; 388 assigned-clocks = <&wiz0_refclk_dig>; 389 assigned-clock-parents = <&k3_clks 292 11>; 390 }; 391 392 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 393 clocks = <&wiz0_refclk_dig>; 394 #clock-cells = <0>; 395 }; 396 397 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 398 clocks = <&wiz0_pll1_refclk>; 399 #clock-cells = <0>; 400 }; 401 402 serdes0: serdes@5000000 { 403 compatible = "ti,sierra-phy-t0"; 404 reg-names = "serdes"; 405 reg = <0x5000000 0x10000>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 #clock-cells = <1>; 409 resets = <&serdes_wiz0 0>; 410 reset-names = "sierra_reset"; 411 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 412 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 413 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 414 "pll0_refclk", "pll1_refclk"; 415 }; 416 }; 417 418 serdes_wiz1: wiz@5010000 { 419 compatible = "ti,j721e-wiz-16g"; 420 #address-cells = <1>; 421 #size-cells = <1>; 422 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 423 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 424 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 425 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 426 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 427 num-lanes = <2>; 428 #reset-cells = <1>; 429 ranges = <0x5010000 0x0 0x5010000 0x10000>; 430 431 wiz1_pll0_refclk: pll0-refclk { 432 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 433 #clock-cells = <0>; 434 assigned-clocks = <&wiz1_pll0_refclk>; 435 assigned-clock-parents = <&k3_clks 293 13>; 436 }; 437 438 wiz1_pll1_refclk: pll1-refclk { 439 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 440 #clock-cells = <0>; 441 assigned-clocks = <&wiz1_pll1_refclk>; 442 assigned-clock-parents = <&k3_clks 293 0>; 443 }; 444 445 wiz1_refclk_dig: refclk-dig { 446 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 447 #clock-cells = <0>; 448 assigned-clocks = <&wiz1_refclk_dig>; 449 assigned-clock-parents = <&k3_clks 293 13>; 450 }; 451 452 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ 453 clocks = <&wiz1_refclk_dig>; 454 #clock-cells = <0>; 455 }; 456 457 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 458 clocks = <&wiz1_pll1_refclk>; 459 #clock-cells = <0>; 460 }; 461 462 serdes1: serdes@5010000 { 463 compatible = "ti,sierra-phy-t0"; 464 reg-names = "serdes"; 465 reg = <0x5010000 0x10000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 #clock-cells = <1>; 469 resets = <&serdes_wiz1 0>; 470 reset-names = "sierra_reset"; 471 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 472 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 473 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 474 "pll0_refclk", "pll1_refclk"; 475 }; 476 }; 477 478 serdes_wiz2: wiz@5020000 { 479 compatible = "ti,j721e-wiz-16g"; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 483 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 484 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 485 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 486 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 487 num-lanes = <2>; 488 #reset-cells = <1>; 489 ranges = <0x5020000 0x0 0x5020000 0x10000>; 490 491 wiz2_pll0_refclk: pll0-refclk { 492 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 493 #clock-cells = <0>; 494 assigned-clocks = <&wiz2_pll0_refclk>; 495 assigned-clock-parents = <&k3_clks 294 11>; 496 }; 497 498 wiz2_pll1_refclk: pll1-refclk { 499 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 500 #clock-cells = <0>; 501 assigned-clocks = <&wiz2_pll1_refclk>; 502 assigned-clock-parents = <&k3_clks 294 0>; 503 }; 504 505 wiz2_refclk_dig: refclk-dig { 506 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 507 #clock-cells = <0>; 508 assigned-clocks = <&wiz2_refclk_dig>; 509 assigned-clock-parents = <&k3_clks 294 11>; 510 }; 511 512 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 513 clocks = <&wiz2_refclk_dig>; 514 #clock-cells = <0>; 515 }; 516 517 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 518 clocks = <&wiz2_pll1_refclk>; 519 #clock-cells = <0>; 520 }; 521 522 serdes2: serdes@5020000 { 523 compatible = "ti,sierra-phy-t0"; 524 reg-names = "serdes"; 525 reg = <0x5020000 0x10000>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 #clock-cells = <1>; 529 resets = <&serdes_wiz2 0>; 530 reset-names = "sierra_reset"; 531 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 532 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 533 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 534 "pll0_refclk", "pll1_refclk"; 535 }; 536 }; 537 538 serdes_wiz3: wiz@5030000 { 539 compatible = "ti,j721e-wiz-16g"; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 543 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 544 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 545 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 546 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 547 num-lanes = <2>; 548 #reset-cells = <1>; 549 ranges = <0x5030000 0x0 0x5030000 0x10000>; 550 551 wiz3_pll0_refclk: pll0-refclk { 552 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 553 #clock-cells = <0>; 554 assigned-clocks = <&wiz3_pll0_refclk>; 555 assigned-clock-parents = <&k3_clks 295 9>; 556 }; 557 558 wiz3_pll1_refclk: pll1-refclk { 559 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 560 #clock-cells = <0>; 561 assigned-clocks = <&wiz3_pll1_refclk>; 562 assigned-clock-parents = <&k3_clks 295 0>; 563 }; 564 565 wiz3_refclk_dig: refclk-dig { 566 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 567 #clock-cells = <0>; 568 assigned-clocks = <&wiz3_refclk_dig>; 569 assigned-clock-parents = <&k3_clks 295 9>; 570 }; 571 572 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 573 clocks = <&wiz3_refclk_dig>; 574 #clock-cells = <0>; 575 }; 576 577 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 578 clocks = <&wiz3_pll1_refclk>; 579 #clock-cells = <0>; 580 }; 581 582 serdes3: serdes@5030000 { 583 compatible = "ti,sierra-phy-t0"; 584 reg-names = "serdes"; 585 reg = <0x5030000 0x10000>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 #clock-cells = <1>; 589 resets = <&serdes_wiz3 0>; 590 reset-names = "sierra_reset"; 591 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 592 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 593 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 594 "pll0_refclk", "pll1_refclk"; 595 }; 596 }; 597 598 pcie0_rc: pcie@2900000 { 599 compatible = "ti,j721e-pcie-host"; 600 reg = <0x00 0x02900000 0x00 0x1000>, 601 <0x00 0x02907000 0x00 0x400>, 602 <0x00 0x0d000000 0x00 0x00800000>, 603 <0x00 0x10000000 0x00 0x00001000>; 604 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 605 interrupt-names = "link_state"; 606 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 607 device_type = "pci"; 608 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 609 max-link-speed = <3>; 610 num-lanes = <2>; 611 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 612 clocks = <&k3_clks 239 1>; 613 clock-names = "fck"; 614 #address-cells = <3>; 615 #size-cells = <2>; 616 bus-range = <0x0 0xff>; 617 vendor-id = <0x104c>; 618 device-id = <0xb00d>; 619 msi-map = <0x0 &gic_its 0x0 0x10000>; 620 dma-coherent; 621 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 622 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 623 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 624 }; 625 626 pcie0_ep: pcie-ep@2900000 { 627 compatible = "ti,j721e-pcie-ep"; 628 reg = <0x00 0x02900000 0x00 0x1000>, 629 <0x00 0x02907000 0x00 0x400>, 630 <0x00 0x0d000000 0x00 0x00800000>, 631 <0x00 0x10000000 0x00 0x08000000>; 632 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 633 interrupt-names = "link_state"; 634 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 635 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; 636 max-link-speed = <3>; 637 num-lanes = <2>; 638 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 639 clocks = <&k3_clks 239 1>; 640 clock-names = "fck"; 641 max-functions = /bits/ 8 <6>; 642 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 643 dma-coherent; 644 }; 645 646 pcie1_rc: pcie@2910000 { 647 compatible = "ti,j721e-pcie-host"; 648 reg = <0x00 0x02910000 0x00 0x1000>, 649 <0x00 0x02917000 0x00 0x400>, 650 <0x00 0x0d800000 0x00 0x00800000>, 651 <0x00 0x18000000 0x00 0x00001000>; 652 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 653 interrupt-names = "link_state"; 654 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 655 device_type = "pci"; 656 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 657 max-link-speed = <3>; 658 num-lanes = <2>; 659 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 660 clocks = <&k3_clks 240 1>; 661 clock-names = "fck"; 662 #address-cells = <3>; 663 #size-cells = <2>; 664 bus-range = <0x0 0xff>; 665 vendor-id = <0x104c>; 666 device-id = <0xb00d>; 667 msi-map = <0x0 &gic_its 0x10000 0x10000>; 668 dma-coherent; 669 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, 670 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; 671 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 672 }; 673 674 pcie1_ep: pcie-ep@2910000 { 675 compatible = "ti,j721e-pcie-ep"; 676 reg = <0x00 0x02910000 0x00 0x1000>, 677 <0x00 0x02917000 0x00 0x400>, 678 <0x00 0x0d800000 0x00 0x00800000>, 679 <0x00 0x18000000 0x00 0x08000000>; 680 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 681 interrupt-names = "link_state"; 682 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 683 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 684 max-link-speed = <3>; 685 num-lanes = <2>; 686 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 687 clocks = <&k3_clks 240 1>; 688 clock-names = "fck"; 689 max-functions = /bits/ 8 <6>; 690 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 691 dma-coherent; 692 }; 693 694 pcie2_rc: pcie@2920000 { 695 compatible = "ti,j721e-pcie-host"; 696 reg = <0x00 0x02920000 0x00 0x1000>, 697 <0x00 0x02927000 0x00 0x400>, 698 <0x00 0x0e000000 0x00 0x00800000>, 699 <0x44 0x00000000 0x00 0x00001000>; 700 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 701 interrupt-names = "link_state"; 702 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 703 device_type = "pci"; 704 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 705 max-link-speed = <3>; 706 num-lanes = <2>; 707 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 708 clocks = <&k3_clks 241 1>; 709 clock-names = "fck"; 710 #address-cells = <3>; 711 #size-cells = <2>; 712 bus-range = <0x0 0xff>; 713 vendor-id = <0x104c>; 714 device-id = <0xb00d>; 715 msi-map = <0x0 &gic_its 0x20000 0x10000>; 716 dma-coherent; 717 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 718 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 719 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 720 }; 721 722 pcie2_ep: pcie-ep@2920000 { 723 compatible = "ti,j721e-pcie-ep"; 724 reg = <0x00 0x02920000 0x00 0x1000>, 725 <0x00 0x02927000 0x00 0x400>, 726 <0x00 0x0e000000 0x00 0x00800000>, 727 <0x44 0x00000000 0x00 0x08000000>; 728 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 729 interrupt-names = "link_state"; 730 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 731 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; 732 max-link-speed = <3>; 733 num-lanes = <2>; 734 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 735 clocks = <&k3_clks 241 1>; 736 clock-names = "fck"; 737 max-functions = /bits/ 8 <6>; 738 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 739 dma-coherent; 740 }; 741 742 pcie3_rc: pcie@2930000 { 743 compatible = "ti,j721e-pcie-host"; 744 reg = <0x00 0x02930000 0x00 0x1000>, 745 <0x00 0x02937000 0x00 0x400>, 746 <0x00 0x0e800000 0x00 0x00800000>, 747 <0x44 0x10000000 0x00 0x00001000>; 748 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 749 interrupt-names = "link_state"; 750 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 751 device_type = "pci"; 752 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 753 max-link-speed = <3>; 754 num-lanes = <2>; 755 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 756 clocks = <&k3_clks 242 1>; 757 clock-names = "fck"; 758 #address-cells = <3>; 759 #size-cells = <2>; 760 bus-range = <0x0 0xff>; 761 vendor-id = <0x104c>; 762 device-id = <0xb00d>; 763 msi-map = <0x0 &gic_its 0x30000 0x10000>; 764 dma-coherent; 765 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 766 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 767 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 768 }; 769 770 pcie3_ep: pcie-ep@2930000 { 771 compatible = "ti,j721e-pcie-ep"; 772 reg = <0x00 0x02930000 0x00 0x1000>, 773 <0x00 0x02937000 0x00 0x400>, 774 <0x00 0x0e800000 0x00 0x00800000>, 775 <0x44 0x10000000 0x00 0x08000000>; 776 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 777 interrupt-names = "link_state"; 778 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 779 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; 780 max-link-speed = <3>; 781 num-lanes = <2>; 782 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 783 clocks = <&k3_clks 242 1>; 784 clock-names = "fck"; 785 max-functions = /bits/ 8 <6>; 786 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 787 dma-coherent; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 }; 791 792 main_uart0: serial@2800000 { 793 compatible = "ti,j721e-uart", "ti,am654-uart"; 794 reg = <0x00 0x02800000 0x00 0x100>; 795 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 796 clock-frequency = <48000000>; 797 current-speed = <115200>; 798 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 799 clocks = <&k3_clks 146 0>; 800 clock-names = "fclk"; 801 }; 802 803 main_uart1: serial@2810000 { 804 compatible = "ti,j721e-uart", "ti,am654-uart"; 805 reg = <0x00 0x02810000 0x00 0x100>; 806 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 807 clock-frequency = <48000000>; 808 current-speed = <115200>; 809 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 810 clocks = <&k3_clks 278 0>; 811 clock-names = "fclk"; 812 }; 813 814 main_uart2: serial@2820000 { 815 compatible = "ti,j721e-uart", "ti,am654-uart"; 816 reg = <0x00 0x02820000 0x00 0x100>; 817 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 818 clock-frequency = <48000000>; 819 current-speed = <115200>; 820 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 821 clocks = <&k3_clks 279 0>; 822 clock-names = "fclk"; 823 }; 824 825 main_uart3: serial@2830000 { 826 compatible = "ti,j721e-uart", "ti,am654-uart"; 827 reg = <0x00 0x02830000 0x00 0x100>; 828 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 829 clock-frequency = <48000000>; 830 current-speed = <115200>; 831 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 832 clocks = <&k3_clks 280 0>; 833 clock-names = "fclk"; 834 }; 835 836 main_uart4: serial@2840000 { 837 compatible = "ti,j721e-uart", "ti,am654-uart"; 838 reg = <0x00 0x02840000 0x00 0x100>; 839 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 840 clock-frequency = <48000000>; 841 current-speed = <115200>; 842 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 843 clocks = <&k3_clks 281 0>; 844 clock-names = "fclk"; 845 }; 846 847 main_uart5: serial@2850000 { 848 compatible = "ti,j721e-uart", "ti,am654-uart"; 849 reg = <0x00 0x02850000 0x00 0x100>; 850 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 851 clock-frequency = <48000000>; 852 current-speed = <115200>; 853 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 854 clocks = <&k3_clks 282 0>; 855 clock-names = "fclk"; 856 }; 857 858 main_uart6: serial@2860000 { 859 compatible = "ti,j721e-uart", "ti,am654-uart"; 860 reg = <0x00 0x02860000 0x00 0x100>; 861 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 862 clock-frequency = <48000000>; 863 current-speed = <115200>; 864 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 865 clocks = <&k3_clks 283 0>; 866 clock-names = "fclk"; 867 }; 868 869 main_uart7: serial@2870000 { 870 compatible = "ti,j721e-uart", "ti,am654-uart"; 871 reg = <0x00 0x02870000 0x00 0x100>; 872 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 873 clock-frequency = <48000000>; 874 current-speed = <115200>; 875 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 876 clocks = <&k3_clks 284 0>; 877 clock-names = "fclk"; 878 }; 879 880 main_uart8: serial@2880000 { 881 compatible = "ti,j721e-uart", "ti,am654-uart"; 882 reg = <0x00 0x02880000 0x00 0x100>; 883 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 884 clock-frequency = <48000000>; 885 current-speed = <115200>; 886 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 887 clocks = <&k3_clks 285 0>; 888 clock-names = "fclk"; 889 }; 890 891 main_uart9: serial@2890000 { 892 compatible = "ti,j721e-uart", "ti,am654-uart"; 893 reg = <0x00 0x02890000 0x00 0x100>; 894 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 895 clock-frequency = <48000000>; 896 current-speed = <115200>; 897 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 898 clocks = <&k3_clks 286 0>; 899 clock-names = "fclk"; 900 }; 901 902 main_gpio0: gpio@600000 { 903 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 904 reg = <0x0 0x00600000 0x0 0x100>; 905 gpio-controller; 906 #gpio-cells = <2>; 907 interrupt-parent = <&main_gpio_intr>; 908 interrupts = <256>, <257>, <258>, <259>, 909 <260>, <261>, <262>, <263>; 910 interrupt-controller; 911 #interrupt-cells = <2>; 912 ti,ngpio = <128>; 913 ti,davinci-gpio-unbanked = <0>; 914 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 915 clocks = <&k3_clks 105 0>; 916 clock-names = "gpio"; 917 }; 918 919 main_gpio1: gpio@601000 { 920 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 921 reg = <0x0 0x00601000 0x0 0x100>; 922 gpio-controller; 923 #gpio-cells = <2>; 924 interrupt-parent = <&main_gpio_intr>; 925 interrupts = <288>, <289>, <290>; 926 interrupt-controller; 927 #interrupt-cells = <2>; 928 ti,ngpio = <36>; 929 ti,davinci-gpio-unbanked = <0>; 930 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 931 clocks = <&k3_clks 106 0>; 932 clock-names = "gpio"; 933 }; 934 935 main_gpio2: gpio@610000 { 936 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 937 reg = <0x0 0x00610000 0x0 0x100>; 938 gpio-controller; 939 #gpio-cells = <2>; 940 interrupt-parent = <&main_gpio_intr>; 941 interrupts = <264>, <265>, <266>, <267>, 942 <268>, <269>, <270>, <271>; 943 interrupt-controller; 944 #interrupt-cells = <2>; 945 ti,ngpio = <128>; 946 ti,davinci-gpio-unbanked = <0>; 947 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 948 clocks = <&k3_clks 107 0>; 949 clock-names = "gpio"; 950 }; 951 952 main_gpio3: gpio@611000 { 953 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 954 reg = <0x0 0x00611000 0x0 0x100>; 955 gpio-controller; 956 #gpio-cells = <2>; 957 interrupt-parent = <&main_gpio_intr>; 958 interrupts = <292>, <293>, <294>; 959 interrupt-controller; 960 #interrupt-cells = <2>; 961 ti,ngpio = <36>; 962 ti,davinci-gpio-unbanked = <0>; 963 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 964 clocks = <&k3_clks 108 0>; 965 clock-names = "gpio"; 966 }; 967 968 main_gpio4: gpio@620000 { 969 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 970 reg = <0x0 0x00620000 0x0 0x100>; 971 gpio-controller; 972 #gpio-cells = <2>; 973 interrupt-parent = <&main_gpio_intr>; 974 interrupts = <272>, <273>, <274>, <275>, 975 <276>, <277>, <278>, <279>; 976 interrupt-controller; 977 #interrupt-cells = <2>; 978 ti,ngpio = <128>; 979 ti,davinci-gpio-unbanked = <0>; 980 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 981 clocks = <&k3_clks 109 0>; 982 clock-names = "gpio"; 983 }; 984 985 main_gpio5: gpio@621000 { 986 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 987 reg = <0x0 0x00621000 0x0 0x100>; 988 gpio-controller; 989 #gpio-cells = <2>; 990 interrupt-parent = <&main_gpio_intr>; 991 interrupts = <296>, <297>, <298>; 992 interrupt-controller; 993 #interrupt-cells = <2>; 994 ti,ngpio = <36>; 995 ti,davinci-gpio-unbanked = <0>; 996 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 997 clocks = <&k3_clks 110 0>; 998 clock-names = "gpio"; 999 }; 1000 1001 main_gpio6: gpio@630000 { 1002 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1003 reg = <0x0 0x00630000 0x0 0x100>; 1004 gpio-controller; 1005 #gpio-cells = <2>; 1006 interrupt-parent = <&main_gpio_intr>; 1007 interrupts = <280>, <281>, <282>, <283>, 1008 <284>, <285>, <286>, <287>; 1009 interrupt-controller; 1010 #interrupt-cells = <2>; 1011 ti,ngpio = <128>; 1012 ti,davinci-gpio-unbanked = <0>; 1013 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1014 clocks = <&k3_clks 111 0>; 1015 clock-names = "gpio"; 1016 }; 1017 1018 main_gpio7: gpio@631000 { 1019 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1020 reg = <0x0 0x00631000 0x0 0x100>; 1021 gpio-controller; 1022 #gpio-cells = <2>; 1023 interrupt-parent = <&main_gpio_intr>; 1024 interrupts = <300>, <301>, <302>; 1025 interrupt-controller; 1026 #interrupt-cells = <2>; 1027 ti,ngpio = <36>; 1028 ti,davinci-gpio-unbanked = <0>; 1029 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1030 clocks = <&k3_clks 112 0>; 1031 clock-names = "gpio"; 1032 }; 1033 1034 main_sdhci0: mmc@4f80000 { 1035 compatible = "ti,j721e-sdhci-8bit"; 1036 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1037 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1038 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1039 clock-names = "clk_ahb", "clk_xin"; 1040 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1041 assigned-clocks = <&k3_clks 91 1>; 1042 assigned-clock-parents = <&k3_clks 91 2>; 1043 bus-width = <8>; 1044 mmc-hs200-1_8v; 1045 mmc-ddr-1_8v; 1046 ti,otap-del-sel-legacy = <0xf>; 1047 ti,otap-del-sel-mmc-hs = <0xf>; 1048 ti,otap-del-sel-ddr52 = <0x5>; 1049 ti,otap-del-sel-hs200 = <0x6>; 1050 ti,otap-del-sel-hs400 = <0x0>; 1051 ti,itap-del-sel-legacy = <0x10>; 1052 ti,itap-del-sel-mmc-hs = <0xa>; 1053 ti,itap-del-sel-ddr52 = <0x3>; 1054 ti,trm-icp = <0x8>; 1055 ti,strobe-sel = <0x77>; 1056 dma-coherent; 1057 }; 1058 1059 main_sdhci1: mmc@4fb0000 { 1060 compatible = "ti,j721e-sdhci-4bit"; 1061 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1062 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1063 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1064 clock-names = "clk_ahb", "clk_xin"; 1065 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1066 assigned-clocks = <&k3_clks 92 0>; 1067 assigned-clock-parents = <&k3_clks 92 1>; 1068 ti,otap-del-sel-legacy = <0x0>; 1069 ti,otap-del-sel-sd-hs = <0xf>; 1070 ti,otap-del-sel-sdr12 = <0xf>; 1071 ti,otap-del-sel-sdr25 = <0xf>; 1072 ti,otap-del-sel-sdr50 = <0xc>; 1073 ti,otap-del-sel-ddr50 = <0xc>; 1074 ti,itap-del-sel-legacy = <0x0>; 1075 ti,itap-del-sel-sd-hs = <0x0>; 1076 ti,itap-del-sel-sdr12 = <0x0>; 1077 ti,itap-del-sel-sdr25 = <0x0>; 1078 ti,itap-del-sel-ddr50 = <0x2>; 1079 ti,trm-icp = <0x8>; 1080 ti,clkbuf-sel = <0x7>; 1081 dma-coherent; 1082 sdhci-caps-mask = <0x2 0x0>; 1083 }; 1084 1085 main_sdhci2: mmc@4f98000 { 1086 compatible = "ti,j721e-sdhci-4bit"; 1087 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1088 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1089 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1090 clock-names = "clk_ahb", "clk_xin"; 1091 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1092 assigned-clocks = <&k3_clks 93 0>; 1093 assigned-clock-parents = <&k3_clks 93 1>; 1094 ti,otap-del-sel-legacy = <0x0>; 1095 ti,otap-del-sel-sd-hs = <0xf>; 1096 ti,otap-del-sel-sdr12 = <0xf>; 1097 ti,otap-del-sel-sdr25 = <0xf>; 1098 ti,otap-del-sel-sdr50 = <0xc>; 1099 ti,otap-del-sel-ddr50 = <0xc>; 1100 ti,itap-del-sel-legacy = <0x0>; 1101 ti,itap-del-sel-sd-hs = <0x0>; 1102 ti,itap-del-sel-sdr12 = <0x0>; 1103 ti,itap-del-sel-sdr25 = <0x0>; 1104 ti,itap-del-sel-ddr50 = <0x2>; 1105 ti,trm-icp = <0x8>; 1106 ti,clkbuf-sel = <0x7>; 1107 dma-coherent; 1108 sdhci-caps-mask = <0x2 0x0>; 1109 }; 1110 1111 usbss0: cdns-usb@4104000 { 1112 compatible = "ti,j721e-usb"; 1113 reg = <0x00 0x4104000 0x00 0x100>; 1114 dma-coherent; 1115 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1116 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1117 clock-names = "ref", "lpm"; 1118 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1119 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1120 #address-cells = <2>; 1121 #size-cells = <2>; 1122 ranges; 1123 1124 usb0: usb@6000000 { 1125 compatible = "cdns,usb3"; 1126 reg = <0x00 0x6000000 0x00 0x10000>, 1127 <0x00 0x6010000 0x00 0x10000>, 1128 <0x00 0x6020000 0x00 0x10000>; 1129 reg-names = "otg", "xhci", "dev"; 1130 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1131 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1132 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1133 interrupt-names = "host", 1134 "peripheral", 1135 "otg"; 1136 maximum-speed = "super-speed"; 1137 dr_mode = "otg"; 1138 }; 1139 }; 1140 1141 usbss1: cdns-usb@4114000 { 1142 compatible = "ti,j721e-usb"; 1143 reg = <0x00 0x4114000 0x00 0x100>; 1144 dma-coherent; 1145 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1146 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1147 clock-names = "ref", "lpm"; 1148 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1149 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1150 #address-cells = <2>; 1151 #size-cells = <2>; 1152 ranges; 1153 1154 usb1: usb@6400000 { 1155 compatible = "cdns,usb3"; 1156 reg = <0x00 0x6400000 0x00 0x10000>, 1157 <0x00 0x6410000 0x00 0x10000>, 1158 <0x00 0x6420000 0x00 0x10000>; 1159 reg-names = "otg", "xhci", "dev"; 1160 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1161 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1162 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1163 interrupt-names = "host", 1164 "peripheral", 1165 "otg"; 1166 maximum-speed = "super-speed"; 1167 dr_mode = "otg"; 1168 }; 1169 }; 1170 1171 main_i2c0: i2c@2000000 { 1172 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1173 reg = <0x0 0x2000000 0x0 0x100>; 1174 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 clock-names = "fck"; 1178 clocks = <&k3_clks 187 0>; 1179 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1180 }; 1181 1182 main_i2c1: i2c@2010000 { 1183 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1184 reg = <0x0 0x2010000 0x0 0x100>; 1185 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 clock-names = "fck"; 1189 clocks = <&k3_clks 188 0>; 1190 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1191 }; 1192 1193 main_i2c2: i2c@2020000 { 1194 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1195 reg = <0x0 0x2020000 0x0 0x100>; 1196 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 clock-names = "fck"; 1200 clocks = <&k3_clks 189 0>; 1201 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1202 }; 1203 1204 main_i2c3: i2c@2030000 { 1205 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1206 reg = <0x0 0x2030000 0x0 0x100>; 1207 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 clock-names = "fck"; 1211 clocks = <&k3_clks 190 0>; 1212 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1213 }; 1214 1215 main_i2c4: i2c@2040000 { 1216 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1217 reg = <0x0 0x2040000 0x0 0x100>; 1218 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 clock-names = "fck"; 1222 clocks = <&k3_clks 191 0>; 1223 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1224 }; 1225 1226 main_i2c5: i2c@2050000 { 1227 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1228 reg = <0x0 0x2050000 0x0 0x100>; 1229 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 clock-names = "fck"; 1233 clocks = <&k3_clks 192 0>; 1234 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1235 }; 1236 1237 main_i2c6: i2c@2060000 { 1238 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1239 reg = <0x0 0x2060000 0x0 0x100>; 1240 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 clock-names = "fck"; 1244 clocks = <&k3_clks 193 0>; 1245 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1246 }; 1247 1248 ufs_wrapper: ufs-wrapper@4e80000 { 1249 compatible = "ti,j721e-ufs"; 1250 reg = <0x0 0x4e80000 0x0 0x100>; 1251 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1252 clocks = <&k3_clks 277 1>; 1253 assigned-clocks = <&k3_clks 277 1>; 1254 assigned-clock-parents = <&k3_clks 277 4>; 1255 ranges; 1256 #address-cells = <2>; 1257 #size-cells = <2>; 1258 1259 ufs@4e84000 { 1260 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1261 reg = <0x0 0x4e84000 0x0 0x10000>; 1262 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1263 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1264 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1265 clock-names = "core_clk", "phy_clk", "ref_clk"; 1266 dma-coherent; 1267 }; 1268 }; 1269 1270 dss: dss@4a00000 { 1271 compatible = "ti,j721e-dss"; 1272 reg = 1273 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1274 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1275 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1276 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1277 1278 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1279 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1280 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1281 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1282 1283 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1284 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1285 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1286 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1287 1288 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1289 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1290 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1291 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1292 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1293 1294 reg-names = "common_m", "common_s0", 1295 "common_s1", "common_s2", 1296 "vidl1", "vidl2","vid1","vid2", 1297 "ovr1", "ovr2", "ovr3", "ovr4", 1298 "vp1", "vp2", "vp3", "vp4", 1299 "wb"; 1300 1301 clocks = <&k3_clks 152 0>, 1302 <&k3_clks 152 1>, 1303 <&k3_clks 152 4>, 1304 <&k3_clks 152 9>, 1305 <&k3_clks 152 13>; 1306 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1307 1308 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1309 1310 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1314 interrupt-names = "common_m", 1315 "common_s0", 1316 "common_s1", 1317 "common_s2"; 1318 1319 dss_ports: ports { 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 }; 1323 }; 1324 1325 mcasp0: mcasp@2b00000 { 1326 compatible = "ti,am33xx-mcasp-audio"; 1327 reg = <0x0 0x02b00000 0x0 0x2000>, 1328 <0x0 0x02b08000 0x0 0x1000>; 1329 reg-names = "mpu","dat"; 1330 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1332 interrupt-names = "tx", "rx"; 1333 1334 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1335 dma-names = "tx", "rx"; 1336 1337 clocks = <&k3_clks 174 1>; 1338 clock-names = "fck"; 1339 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1340 }; 1341 1342 mcasp1: mcasp@2b10000 { 1343 compatible = "ti,am33xx-mcasp-audio"; 1344 reg = <0x0 0x02b10000 0x0 0x2000>, 1345 <0x0 0x02b18000 0x0 0x1000>; 1346 reg-names = "mpu","dat"; 1347 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1349 interrupt-names = "tx", "rx"; 1350 1351 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1352 dma-names = "tx", "rx"; 1353 1354 clocks = <&k3_clks 175 1>; 1355 clock-names = "fck"; 1356 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1357 }; 1358 1359 mcasp2: mcasp@2b20000 { 1360 compatible = "ti,am33xx-mcasp-audio"; 1361 reg = <0x0 0x02b20000 0x0 0x2000>, 1362 <0x0 0x02b28000 0x0 0x1000>; 1363 reg-names = "mpu","dat"; 1364 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1366 interrupt-names = "tx", "rx"; 1367 1368 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1369 dma-names = "tx", "rx"; 1370 1371 clocks = <&k3_clks 176 1>; 1372 clock-names = "fck"; 1373 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1374 }; 1375 1376 mcasp3: mcasp@2b30000 { 1377 compatible = "ti,am33xx-mcasp-audio"; 1378 reg = <0x0 0x02b30000 0x0 0x2000>, 1379 <0x0 0x02b38000 0x0 0x1000>; 1380 reg-names = "mpu","dat"; 1381 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1383 interrupt-names = "tx", "rx"; 1384 1385 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 1386 dma-names = "tx", "rx"; 1387 1388 clocks = <&k3_clks 177 1>; 1389 clock-names = "fck"; 1390 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 1391 }; 1392 1393 mcasp4: mcasp@2b40000 { 1394 compatible = "ti,am33xx-mcasp-audio"; 1395 reg = <0x0 0x02b40000 0x0 0x2000>, 1396 <0x0 0x02b48000 0x0 0x1000>; 1397 reg-names = "mpu","dat"; 1398 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "tx", "rx"; 1401 1402 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 1403 dma-names = "tx", "rx"; 1404 1405 clocks = <&k3_clks 178 1>; 1406 clock-names = "fck"; 1407 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 1408 }; 1409 1410 mcasp5: mcasp@2b50000 { 1411 compatible = "ti,am33xx-mcasp-audio"; 1412 reg = <0x0 0x02b50000 0x0 0x2000>, 1413 <0x0 0x02b58000 0x0 0x1000>; 1414 reg-names = "mpu","dat"; 1415 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 1417 interrupt-names = "tx", "rx"; 1418 1419 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 1420 dma-names = "tx", "rx"; 1421 1422 clocks = <&k3_clks 179 1>; 1423 clock-names = "fck"; 1424 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 1425 }; 1426 1427 mcasp6: mcasp@2b60000 { 1428 compatible = "ti,am33xx-mcasp-audio"; 1429 reg = <0x0 0x02b60000 0x0 0x2000>, 1430 <0x0 0x02b68000 0x0 0x1000>; 1431 reg-names = "mpu","dat"; 1432 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 1434 interrupt-names = "tx", "rx"; 1435 1436 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 1437 dma-names = "tx", "rx"; 1438 1439 clocks = <&k3_clks 180 1>; 1440 clock-names = "fck"; 1441 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 1442 }; 1443 1444 mcasp7: mcasp@2b70000 { 1445 compatible = "ti,am33xx-mcasp-audio"; 1446 reg = <0x0 0x02b70000 0x0 0x2000>, 1447 <0x0 0x02b78000 0x0 0x1000>; 1448 reg-names = "mpu","dat"; 1449 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 1451 interrupt-names = "tx", "rx"; 1452 1453 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 1454 dma-names = "tx", "rx"; 1455 1456 clocks = <&k3_clks 181 1>; 1457 clock-names = "fck"; 1458 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 1459 }; 1460 1461 mcasp8: mcasp@2b80000 { 1462 compatible = "ti,am33xx-mcasp-audio"; 1463 reg = <0x0 0x02b80000 0x0 0x2000>, 1464 <0x0 0x02b88000 0x0 0x1000>; 1465 reg-names = "mpu","dat"; 1466 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 1468 interrupt-names = "tx", "rx"; 1469 1470 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 1471 dma-names = "tx", "rx"; 1472 1473 clocks = <&k3_clks 182 1>; 1474 clock-names = "fck"; 1475 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1476 }; 1477 1478 mcasp9: mcasp@2b90000 { 1479 compatible = "ti,am33xx-mcasp-audio"; 1480 reg = <0x0 0x02b90000 0x0 0x2000>, 1481 <0x0 0x02b98000 0x0 0x1000>; 1482 reg-names = "mpu","dat"; 1483 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 1485 interrupt-names = "tx", "rx"; 1486 1487 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 1488 dma-names = "tx", "rx"; 1489 1490 clocks = <&k3_clks 183 1>; 1491 clock-names = "fck"; 1492 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1493 }; 1494 1495 mcasp10: mcasp@2ba0000 { 1496 compatible = "ti,am33xx-mcasp-audio"; 1497 reg = <0x0 0x02ba0000 0x0 0x2000>, 1498 <0x0 0x02ba8000 0x0 0x1000>; 1499 reg-names = "mpu","dat"; 1500 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 1502 interrupt-names = "tx", "rx"; 1503 1504 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 1505 dma-names = "tx", "rx"; 1506 1507 clocks = <&k3_clks 184 1>; 1508 clock-names = "fck"; 1509 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1510 }; 1511 1512 mcasp11: mcasp@2bb0000 { 1513 compatible = "ti,am33xx-mcasp-audio"; 1514 reg = <0x0 0x02bb0000 0x0 0x2000>, 1515 <0x0 0x02bb8000 0x0 0x1000>; 1516 reg-names = "mpu","dat"; 1517 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 1519 interrupt-names = "tx", "rx"; 1520 1521 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 1522 dma-names = "tx", "rx"; 1523 1524 clocks = <&k3_clks 185 1>; 1525 clock-names = "fck"; 1526 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1527 }; 1528 1529 watchdog0: watchdog@2200000 { 1530 compatible = "ti,j7-rti-wdt"; 1531 reg = <0x0 0x2200000 0x0 0x100>; 1532 clocks = <&k3_clks 252 1>; 1533 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1534 assigned-clocks = <&k3_clks 252 1>; 1535 assigned-clock-parents = <&k3_clks 252 5>; 1536 }; 1537 1538 watchdog1: watchdog@2210000 { 1539 compatible = "ti,j7-rti-wdt"; 1540 reg = <0x0 0x2210000 0x0 0x100>; 1541 clocks = <&k3_clks 253 1>; 1542 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1543 assigned-clocks = <&k3_clks 253 1>; 1544 assigned-clock-parents = <&k3_clks 253 5>; 1545 }; 1546 1547 main_r5fss0: r5fss@5c00000 { 1548 compatible = "ti,j721e-r5fss"; 1549 ti,cluster-mode = <1>; 1550 #address-cells = <1>; 1551 #size-cells = <1>; 1552 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1553 <0x5d00000 0x00 0x5d00000 0x20000>; 1554 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1555 1556 main_r5fss0_core0: r5f@5c00000 { 1557 compatible = "ti,j721e-r5f"; 1558 reg = <0x5c00000 0x00008000>, 1559 <0x5c10000 0x00008000>; 1560 reg-names = "atcm", "btcm"; 1561 ti,sci = <&dmsc>; 1562 ti,sci-dev-id = <245>; 1563 ti,sci-proc-ids = <0x06 0xff>; 1564 resets = <&k3_reset 245 1>; 1565 firmware-name = "j7-main-r5f0_0-fw"; 1566 ti,atcm-enable = <1>; 1567 ti,btcm-enable = <1>; 1568 ti,loczrama = <1>; 1569 }; 1570 1571 main_r5fss0_core1: r5f@5d00000 { 1572 compatible = "ti,j721e-r5f"; 1573 reg = <0x5d00000 0x00008000>, 1574 <0x5d10000 0x00008000>; 1575 reg-names = "atcm", "btcm"; 1576 ti,sci = <&dmsc>; 1577 ti,sci-dev-id = <246>; 1578 ti,sci-proc-ids = <0x07 0xff>; 1579 resets = <&k3_reset 246 1>; 1580 firmware-name = "j7-main-r5f0_1-fw"; 1581 ti,atcm-enable = <1>; 1582 ti,btcm-enable = <1>; 1583 ti,loczrama = <1>; 1584 }; 1585 }; 1586 1587 main_r5fss1: r5fss@5e00000 { 1588 compatible = "ti,j721e-r5fss"; 1589 ti,cluster-mode = <1>; 1590 #address-cells = <1>; 1591 #size-cells = <1>; 1592 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 1593 <0x5f00000 0x00 0x5f00000 0x20000>; 1594 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 1595 1596 main_r5fss1_core0: r5f@5e00000 { 1597 compatible = "ti,j721e-r5f"; 1598 reg = <0x5e00000 0x00008000>, 1599 <0x5e10000 0x00008000>; 1600 reg-names = "atcm", "btcm"; 1601 ti,sci = <&dmsc>; 1602 ti,sci-dev-id = <247>; 1603 ti,sci-proc-ids = <0x08 0xff>; 1604 resets = <&k3_reset 247 1>; 1605 firmware-name = "j7-main-r5f1_0-fw"; 1606 ti,atcm-enable = <1>; 1607 ti,btcm-enable = <1>; 1608 ti,loczrama = <1>; 1609 }; 1610 1611 main_r5fss1_core1: r5f@5f00000 { 1612 compatible = "ti,j721e-r5f"; 1613 reg = <0x5f00000 0x00008000>, 1614 <0x5f10000 0x00008000>; 1615 reg-names = "atcm", "btcm"; 1616 ti,sci = <&dmsc>; 1617 ti,sci-dev-id = <248>; 1618 ti,sci-proc-ids = <0x09 0xff>; 1619 resets = <&k3_reset 248 1>; 1620 firmware-name = "j7-main-r5f1_1-fw"; 1621 ti,atcm-enable = <1>; 1622 ti,btcm-enable = <1>; 1623 ti,loczrama = <1>; 1624 }; 1625 }; 1626 1627 c66_0: dsp@4d80800000 { 1628 compatible = "ti,j721e-c66-dsp"; 1629 reg = <0x4d 0x80800000 0x00 0x00048000>, 1630 <0x4d 0x80e00000 0x00 0x00008000>, 1631 <0x4d 0x80f00000 0x00 0x00008000>; 1632 reg-names = "l2sram", "l1pram", "l1dram"; 1633 ti,sci = <&dmsc>; 1634 ti,sci-dev-id = <142>; 1635 ti,sci-proc-ids = <0x03 0xff>; 1636 resets = <&k3_reset 142 1>; 1637 firmware-name = "j7-c66_0-fw"; 1638 }; 1639 1640 c66_1: dsp@4d81800000 { 1641 compatible = "ti,j721e-c66-dsp"; 1642 reg = <0x4d 0x81800000 0x00 0x00048000>, 1643 <0x4d 0x81e00000 0x00 0x00008000>, 1644 <0x4d 0x81f00000 0x00 0x00008000>; 1645 reg-names = "l2sram", "l1pram", "l1dram"; 1646 ti,sci = <&dmsc>; 1647 ti,sci-dev-id = <143>; 1648 ti,sci-proc-ids = <0x04 0xff>; 1649 resets = <&k3_reset 143 1>; 1650 firmware-name = "j7-c66_1-fw"; 1651 }; 1652 1653 c71_0: dsp@64800000 { 1654 compatible = "ti,j721e-c71-dsp"; 1655 reg = <0x00 0x64800000 0x00 0x00080000>, 1656 <0x00 0x64e00000 0x00 0x0000c000>; 1657 reg-names = "l2sram", "l1dram"; 1658 ti,sci = <&dmsc>; 1659 ti,sci-dev-id = <15>; 1660 ti,sci-proc-ids = <0x30 0xff>; 1661 resets = <&k3_reset 15 1>; 1662 firmware-name = "j7-c71_0-fw"; 1663 }; 1664 1665 icssg0: icssg@b000000 { 1666 compatible = "ti,j721e-icssg"; 1667 reg = <0x00 0xb000000 0x00 0x80000>; 1668 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 1669 #address-cells = <1>; 1670 #size-cells = <1>; 1671 ranges = <0x0 0x00 0x0b000000 0x100000>; 1672 1673 icssg0_mem: memories@0 { 1674 reg = <0x0 0x2000>, 1675 <0x2000 0x2000>, 1676 <0x10000 0x10000>; 1677 reg-names = "dram0", "dram1", 1678 "shrdram2"; 1679 }; 1680 1681 icssg0_cfg: cfg@26000 { 1682 compatible = "ti,pruss-cfg", "syscon"; 1683 reg = <0x26000 0x200>; 1684 #address-cells = <1>; 1685 #size-cells = <1>; 1686 ranges = <0x0 0x26000 0x2000>; 1687 1688 clocks { 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 1692 icssg0_coreclk_mux: coreclk-mux@3c { 1693 reg = <0x3c>; 1694 #clock-cells = <0>; 1695 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 1696 <&k3_clks 119 1>; /* icssg0_iclk */ 1697 assigned-clocks = <&icssg0_coreclk_mux>; 1698 assigned-clock-parents = <&k3_clks 119 1>; 1699 }; 1700 1701 icssg0_iepclk_mux: iepclk-mux@30 { 1702 reg = <0x30>; 1703 #clock-cells = <0>; 1704 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 1705 <&icssg0_coreclk_mux>; /* core_clk */ 1706 assigned-clocks = <&icssg0_iepclk_mux>; 1707 assigned-clock-parents = <&icssg0_coreclk_mux>; 1708 }; 1709 }; 1710 }; 1711 1712 icssg0_mii_rt: mii-rt@32000 { 1713 compatible = "ti,pruss-mii", "syscon"; 1714 reg = <0x32000 0x100>; 1715 }; 1716 1717 icssg0_mii_g_rt: mii-g-rt@33000 { 1718 compatible = "ti,pruss-mii-g", "syscon"; 1719 reg = <0x33000 0x1000>; 1720 }; 1721 1722 icssg0_intc: interrupt-controller@20000 { 1723 compatible = "ti,icssg-intc"; 1724 reg = <0x20000 0x2000>; 1725 interrupt-controller; 1726 #interrupt-cells = <3>; 1727 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1735 interrupt-names = "host_intr0", "host_intr1", 1736 "host_intr2", "host_intr3", 1737 "host_intr4", "host_intr5", 1738 "host_intr6", "host_intr7"; 1739 }; 1740 1741 pru0_0: pru@34000 { 1742 compatible = "ti,j721e-pru"; 1743 reg = <0x34000 0x3000>, 1744 <0x22000 0x100>, 1745 <0x22400 0x100>; 1746 reg-names = "iram", "control", "debug"; 1747 firmware-name = "j7-pru0_0-fw"; 1748 }; 1749 1750 rtu0_0: rtu@4000 { 1751 compatible = "ti,j721e-rtu"; 1752 reg = <0x4000 0x2000>, 1753 <0x23000 0x100>, 1754 <0x23400 0x100>; 1755 reg-names = "iram", "control", "debug"; 1756 firmware-name = "j7-rtu0_0-fw"; 1757 }; 1758 1759 tx_pru0_0: txpru@a000 { 1760 compatible = "ti,j721e-tx-pru"; 1761 reg = <0xa000 0x1800>, 1762 <0x25000 0x100>, 1763 <0x25400 0x100>; 1764 reg-names = "iram", "control", "debug"; 1765 firmware-name = "j7-txpru0_0-fw"; 1766 }; 1767 1768 pru0_1: pru@38000 { 1769 compatible = "ti,j721e-pru"; 1770 reg = <0x38000 0x3000>, 1771 <0x24000 0x100>, 1772 <0x24400 0x100>; 1773 reg-names = "iram", "control", "debug"; 1774 firmware-name = "j7-pru0_1-fw"; 1775 }; 1776 1777 rtu0_1: rtu@6000 { 1778 compatible = "ti,j721e-rtu"; 1779 reg = <0x6000 0x2000>, 1780 <0x23800 0x100>, 1781 <0x23c00 0x100>; 1782 reg-names = "iram", "control", "debug"; 1783 firmware-name = "j7-rtu0_1-fw"; 1784 }; 1785 1786 tx_pru0_1: txpru@c000 { 1787 compatible = "ti,j721e-tx-pru"; 1788 reg = <0xc000 0x1800>, 1789 <0x25800 0x100>, 1790 <0x25c00 0x100>; 1791 reg-names = "iram", "control", "debug"; 1792 firmware-name = "j7-txpru0_1-fw"; 1793 }; 1794 1795 icssg0_mdio: mdio@32400 { 1796 compatible = "ti,davinci_mdio"; 1797 reg = <0x32400 0x100>; 1798 clocks = <&k3_clks 119 1>; 1799 clock-names = "fck"; 1800 #address-cells = <1>; 1801 #size-cells = <0>; 1802 bus_freq = <1000000>; 1803 }; 1804 }; 1805 1806 icssg1: icssg@b100000 { 1807 compatible = "ti,j721e-icssg"; 1808 reg = <0x00 0xb100000 0x00 0x80000>; 1809 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 1810 #address-cells = <1>; 1811 #size-cells = <1>; 1812 ranges = <0x0 0x00 0x0b100000 0x100000>; 1813 1814 icssg1_mem: memories@b100000 { 1815 reg = <0x0 0x2000>, 1816 <0x2000 0x2000>, 1817 <0x10000 0x10000>; 1818 reg-names = "dram0", "dram1", 1819 "shrdram2"; 1820 }; 1821 1822 icssg1_cfg: cfg@26000 { 1823 compatible = "ti,pruss-cfg", "syscon"; 1824 reg = <0x26000 0x200>; 1825 #address-cells = <1>; 1826 #size-cells = <1>; 1827 ranges = <0x0 0x26000 0x2000>; 1828 1829 clocks { 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 1833 icssg1_coreclk_mux: coreclk-mux@3c { 1834 reg = <0x3c>; 1835 #clock-cells = <0>; 1836 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 1837 <&k3_clks 120 4>; /* icssg1_iclk */ 1838 assigned-clocks = <&icssg1_coreclk_mux>; 1839 assigned-clock-parents = <&k3_clks 120 4>; 1840 }; 1841 1842 icssg1_iepclk_mux: iepclk-mux@30 { 1843 reg = <0x30>; 1844 #clock-cells = <0>; 1845 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 1846 <&icssg1_coreclk_mux>; /* core_clk */ 1847 assigned-clocks = <&icssg1_iepclk_mux>; 1848 assigned-clock-parents = <&icssg1_coreclk_mux>; 1849 }; 1850 }; 1851 }; 1852 1853 icssg1_mii_rt: mii-rt@32000 { 1854 compatible = "ti,pruss-mii", "syscon"; 1855 reg = <0x32000 0x100>; 1856 }; 1857 1858 icssg1_mii_g_rt: mii-g-rt@33000 { 1859 compatible = "ti,pruss-mii-g", "syscon"; 1860 reg = <0x33000 0x1000>; 1861 }; 1862 1863 icssg1_intc: interrupt-controller@20000 { 1864 compatible = "ti,icssg-intc"; 1865 reg = <0x20000 0x2000>; 1866 interrupt-controller; 1867 #interrupt-cells = <3>; 1868 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1876 interrupt-names = "host_intr0", "host_intr1", 1877 "host_intr2", "host_intr3", 1878 "host_intr4", "host_intr5", 1879 "host_intr6", "host_intr7"; 1880 }; 1881 1882 pru1_0: pru@34000 { 1883 compatible = "ti,j721e-pru"; 1884 reg = <0x34000 0x4000>, 1885 <0x22000 0x100>, 1886 <0x22400 0x100>; 1887 reg-names = "iram", "control", "debug"; 1888 firmware-name = "j7-pru1_0-fw"; 1889 }; 1890 1891 rtu1_0: rtu@4000 { 1892 compatible = "ti,j721e-rtu"; 1893 reg = <0x4000 0x2000>, 1894 <0x23000 0x100>, 1895 <0x23400 0x100>; 1896 reg-names = "iram", "control", "debug"; 1897 firmware-name = "j7-rtu1_0-fw"; 1898 }; 1899 1900 tx_pru1_0: txpru@a000 { 1901 compatible = "ti,j721e-tx-pru"; 1902 reg = <0xa000 0x1800>, 1903 <0x25000 0x100>, 1904 <0x25400 0x100>; 1905 reg-names = "iram", "control", "debug"; 1906 firmware-name = "j7-txpru1_0-fw"; 1907 }; 1908 1909 pru1_1: pru@38000 { 1910 compatible = "ti,j721e-pru"; 1911 reg = <0x38000 0x4000>, 1912 <0x24000 0x100>, 1913 <0x24400 0x100>; 1914 reg-names = "iram", "control", "debug"; 1915 firmware-name = "j7-pru1_1-fw"; 1916 }; 1917 1918 rtu1_1: rtu@6000 { 1919 compatible = "ti,j721e-rtu"; 1920 reg = <0x6000 0x2000>, 1921 <0x23800 0x100>, 1922 <0x23c00 0x100>; 1923 reg-names = "iram", "control", "debug"; 1924 firmware-name = "j7-rtu1_1-fw"; 1925 }; 1926 1927 tx_pru1_1: txpru@c000 { 1928 compatible = "ti,j721e-tx-pru"; 1929 reg = <0xc000 0x1800>, 1930 <0x25800 0x100>, 1931 <0x25c00 0x100>; 1932 reg-names = "iram", "control", "debug"; 1933 firmware-name = "j7-txpru1_1-fw"; 1934 }; 1935 1936 icssg1_mdio: mdio@32400 { 1937 compatible = "ti,davinci_mdio"; 1938 reg = <0x32400 0x100>; 1939 clocks = <&k3_clks 120 4>; 1940 clock-names = "fck"; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 bus_freq = <1000000>; 1944 }; 1945 }; 1946 1947 main_mcan0: can@2701000 { 1948 compatible = "bosch,m_can"; 1949 reg = <0x00 0x02701000 0x00 0x200>, 1950 <0x00 0x02708000 0x00 0x8000>; 1951 reg-names = "m_can", "message_ram"; 1952 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 1953 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 1954 clock-names = "hclk", "cclk"; 1955 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1957 interrupt-names = "int0", "int1"; 1958 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1959 }; 1960 1961 main_mcan1: can@2711000 { 1962 compatible = "bosch,m_can"; 1963 reg = <0x00 0x02711000 0x00 0x200>, 1964 <0x00 0x02718000 0x00 0x8000>; 1965 reg-names = "m_can", "message_ram"; 1966 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 1967 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 1968 clock-names = "hclk", "cclk"; 1969 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1971 interrupt-names = "int0", "int1"; 1972 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1973 }; 1974 1975 main_mcan2: can@2721000 { 1976 compatible = "bosch,m_can"; 1977 reg = <0x00 0x02721000 0x00 0x200>, 1978 <0x00 0x02728000 0x00 0x8000>; 1979 reg-names = "m_can", "message_ram"; 1980 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 1981 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 1982 clock-names = "hclk", "cclk"; 1983 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1985 interrupt-names = "int0", "int1"; 1986 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1987 }; 1988 1989 main_mcan3: can@2731000 { 1990 compatible = "bosch,m_can"; 1991 reg = <0x00 0x02731000 0x00 0x200>, 1992 <0x00 0x02738000 0x00 0x8000>; 1993 reg-names = "m_can", "message_ram"; 1994 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 1995 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 1996 clock-names = "hclk", "cclk"; 1997 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1998 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1999 interrupt-names = "int0", "int1"; 2000 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2001 }; 2002 2003 main_mcan4: can@2741000 { 2004 compatible = "bosch,m_can"; 2005 reg = <0x00 0x02741000 0x00 0x200>, 2006 <0x00 0x02748000 0x00 0x8000>; 2007 reg-names = "m_can", "message_ram"; 2008 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2009 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2010 clock-names = "hclk", "cclk"; 2011 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2013 interrupt-names = "int0", "int1"; 2014 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2015 }; 2016 2017 main_mcan5: can@2751000 { 2018 compatible = "bosch,m_can"; 2019 reg = <0x00 0x02751000 0x00 0x200>, 2020 <0x00 0x02758000 0x00 0x8000>; 2021 reg-names = "m_can", "message_ram"; 2022 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2023 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2024 clock-names = "hclk", "cclk"; 2025 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2027 interrupt-names = "int0", "int1"; 2028 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2029 }; 2030 2031 main_mcan6: can@2761000 { 2032 compatible = "bosch,m_can"; 2033 reg = <0x00 0x02761000 0x00 0x200>, 2034 <0x00 0x02768000 0x00 0x8000>; 2035 reg-names = "m_can", "message_ram"; 2036 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2037 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2038 clock-names = "hclk", "cclk"; 2039 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2041 interrupt-names = "int0", "int1"; 2042 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2043 }; 2044 2045 main_mcan7: can@2771000 { 2046 compatible = "bosch,m_can"; 2047 reg = <0x00 0x02771000 0x00 0x200>, 2048 <0x00 0x02778000 0x00 0x8000>; 2049 reg-names = "m_can", "message_ram"; 2050 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2051 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2052 clock-names = "hclk", "cclk"; 2053 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2055 interrupt-names = "int0", "int1"; 2056 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2057 }; 2058 2059 main_mcan8: can@2781000 { 2060 compatible = "bosch,m_can"; 2061 reg = <0x00 0x02781000 0x00 0x200>, 2062 <0x00 0x02788000 0x00 0x8000>; 2063 reg-names = "m_can", "message_ram"; 2064 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2065 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2066 clock-names = "hclk", "cclk"; 2067 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2069 interrupt-names = "int0", "int1"; 2070 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2071 }; 2072 2073 main_mcan9: can@2791000 { 2074 compatible = "bosch,m_can"; 2075 reg = <0x00 0x02791000 0x00 0x200>, 2076 <0x00 0x02798000 0x00 0x8000>; 2077 reg-names = "m_can", "message_ram"; 2078 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2079 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2080 clock-names = "hclk", "cclk"; 2081 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2083 interrupt-names = "int0", "int1"; 2084 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2085 }; 2086 2087 main_mcan10: can@27a1000 { 2088 compatible = "bosch,m_can"; 2089 reg = <0x00 0x027a1000 0x00 0x200>, 2090 <0x00 0x027a8000 0x00 0x8000>; 2091 reg-names = "m_can", "message_ram"; 2092 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2093 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2094 clock-names = "hclk", "cclk"; 2095 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2097 interrupt-names = "int0", "int1"; 2098 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2099 }; 2100 2101 main_mcan11: can@27b1000 { 2102 compatible = "bosch,m_can"; 2103 reg = <0x00 0x027b1000 0x00 0x200>, 2104 <0x00 0x027b8000 0x00 0x8000>; 2105 reg-names = "m_can", "message_ram"; 2106 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2107 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2108 clock-names = "hclk", "cclk"; 2109 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2111 interrupt-names = "int0", "int1"; 2112 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2113 }; 2114 2115 main_mcan12: can@27c1000 { 2116 compatible = "bosch,m_can"; 2117 reg = <0x00 0x027c1000 0x00 0x200>, 2118 <0x00 0x027c8000 0x00 0x8000>; 2119 reg-names = "m_can", "message_ram"; 2120 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2121 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2122 clock-names = "hclk", "cclk"; 2123 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2125 interrupt-names = "int0", "int1"; 2126 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2127 }; 2128 2129 main_mcan13: can@27d1000 { 2130 compatible = "bosch,m_can"; 2131 reg = <0x00 0x027d1000 0x00 0x200>, 2132 <0x00 0x027d8000 0x00 0x8000>; 2133 reg-names = "m_can", "message_ram"; 2134 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2135 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2136 clock-names = "hclk", "cclk"; 2137 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2139 interrupt-names = "int0", "int1"; 2140 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2141 }; 2142}; 2143