1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM 6 */ 7 8/dts-v1/; 9 10#include "k3-j721e.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/net/ti-dp83867.h> 14 15/ { 16 compatible = "ti,j721e-sk", "ti,j721e"; 17 model = "Texas Instruments J721E SK"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 ethernet0 = &cpsw_port1; 25 mmc1 = &main_sdhci1; 26 }; 27 28 chosen { 29 stdout-path = "serial2:115200n8"; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 /* 4G RAM */ 35 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 36 <0x00000008 0x80000000 0x00000000 0x80000000>; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_ddr: optee@9e800000 { 45 reg = <0x00 0x9e800000 0x00 0x01800000>; 46 alignment = <0x1000>; 47 no-map; 48 }; 49 50 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 51 compatible = "shared-dma-pool"; 52 reg = <0x00 0xa0000000 0x00 0x100000>; 53 no-map; 54 }; 55 56 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 57 compatible = "shared-dma-pool"; 58 reg = <0x00 0xa0100000 0x00 0xf00000>; 59 no-map; 60 }; 61 62 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0xa1000000 0x00 0x100000>; 65 no-map; 66 }; 67 68 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0xa1100000 0x00 0xf00000>; 71 no-map; 72 }; 73 74 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0xa2000000 0x00 0x100000>; 77 no-map; 78 }; 79 80 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 81 compatible = "shared-dma-pool"; 82 reg = <0x00 0xa2100000 0x00 0xf00000>; 83 no-map; 84 }; 85 86 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 87 compatible = "shared-dma-pool"; 88 reg = <0x00 0xa3000000 0x00 0x100000>; 89 no-map; 90 }; 91 92 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 93 compatible = "shared-dma-pool"; 94 reg = <0x00 0xa3100000 0x00 0xf00000>; 95 no-map; 96 }; 97 98 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 99 compatible = "shared-dma-pool"; 100 reg = <0x00 0xa4000000 0x00 0x100000>; 101 no-map; 102 }; 103 104 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 105 compatible = "shared-dma-pool"; 106 reg = <0x00 0xa4100000 0x00 0xf00000>; 107 no-map; 108 }; 109 110 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 111 compatible = "shared-dma-pool"; 112 reg = <0x00 0xa5000000 0x00 0x100000>; 113 no-map; 114 }; 115 116 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 117 compatible = "shared-dma-pool"; 118 reg = <0x00 0xa5100000 0x00 0xf00000>; 119 no-map; 120 }; 121 122 c66_1_dma_memory_region: c66-dma-memory@a6000000 { 123 compatible = "shared-dma-pool"; 124 reg = <0x00 0xa6000000 0x00 0x100000>; 125 no-map; 126 }; 127 128 c66_0_memory_region: c66-memory@a6100000 { 129 compatible = "shared-dma-pool"; 130 reg = <0x00 0xa6100000 0x00 0xf00000>; 131 no-map; 132 }; 133 134 c66_0_dma_memory_region: c66-dma-memory@a7000000 { 135 compatible = "shared-dma-pool"; 136 reg = <0x00 0xa7000000 0x00 0x100000>; 137 no-map; 138 }; 139 140 c66_1_memory_region: c66-memory@a7100000 { 141 compatible = "shared-dma-pool"; 142 reg = <0x00 0xa7100000 0x00 0xf00000>; 143 no-map; 144 }; 145 146 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 147 compatible = "shared-dma-pool"; 148 reg = <0x00 0xa8000000 0x00 0x100000>; 149 no-map; 150 }; 151 152 c71_0_memory_region: c71-memory@a8100000 { 153 compatible = "shared-dma-pool"; 154 reg = <0x00 0xa8100000 0x00 0xf00000>; 155 no-map; 156 }; 157 158 rtos_ipc_memory_region: ipc-memories@aa000000 { 159 reg = <0x00 0xaa000000 0x00 0x01c00000>; 160 alignment = <0x1000>; 161 no-map; 162 }; 163 }; 164 165 vusb_main: fixedregulator-vusb-main5v0 { 166 /* USB MAIN INPUT 5V DC */ 167 compatible = "regulator-fixed"; 168 regulator-name = "vusb-main5v0"; 169 regulator-min-microvolt = <5000000>; 170 regulator-max-microvolt = <5000000>; 171 regulator-always-on; 172 regulator-boot-on; 173 }; 174 175 vsys_3v3: fixedregulator-vsys3v3 { 176 /* Output of LM5141 */ 177 compatible = "regulator-fixed"; 178 regulator-name = "vsys_3v3"; 179 regulator-min-microvolt = <3300000>; 180 regulator-max-microvolt = <3300000>; 181 vin-supply = <&vusb_main>; 182 regulator-always-on; 183 regulator-boot-on; 184 }; 185 186 vdd_mmc1: fixedregulator-sd { 187 compatible = "regulator-fixed"; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&vdd_mmc1_en_pins_default>; 190 regulator-name = "vdd_mmc1"; 191 regulator-min-microvolt = <3300000>; 192 regulator-max-microvolt = <3300000>; 193 regulator-boot-on; 194 enable-active-high; 195 vin-supply = <&vsys_3v3>; 196 gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>; 197 }; 198 199 vdd_sd_dv_alt: gpio-regulator-tps659411 { 200 compatible = "regulator-gpio"; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 203 regulator-name = "tps659411"; 204 regulator-min-microvolt = <1800000>; 205 regulator-max-microvolt = <3300000>; 206 regulator-boot-on; 207 vin-supply = <&vsys_3v3>; 208 gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>; 209 states = <1800000 0x0>, 210 <3300000 0x1>; 211 }; 212 213 dp_pwr_3v3: fixedregulator-dp-prw { 214 compatible = "regulator-fixed"; 215 regulator-name = "dp-pwr"; 216 regulator-min-microvolt = <3300000>; 217 regulator-max-microvolt = <3300000>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&dp_pwr_en_pins_default>; 220 gpio = <&main_gpio0 111 0>; /* DP0_3V3 _EN */ 221 enable-active-high; 222 }; 223 224 dp0: connector { 225 compatible = "dp-connector"; 226 label = "DP0"; 227 type = "full-size"; 228 dp-pwr-supply = <&dp_pwr_3v3>; 229 230 port { 231 dp_connector_in: endpoint { 232 remote-endpoint = <&dp0_out>; 233 }; 234 }; 235 }; 236 237 hdmi-connector { 238 compatible = "hdmi-connector"; 239 label = "hdmi"; 240 type = "a"; 241 242 pinctrl-names = "default"; 243 pinctrl-0 = <&hdmi_hpd_pins_default>; 244 245 ddc-i2c-bus = <&main_i2c1>; 246 247 /* HDMI_HPD */ 248 hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; 249 250 port { 251 hdmi_connector_in: endpoint { 252 remote-endpoint = <&tfp410_out>; 253 }; 254 }; 255 }; 256 257 dvi-bridge { 258 compatible = "ti,tfp410"; 259 260 pinctrl-names = "default"; 261 pinctrl-0 = <&hdmi_pdn_pins_default>; 262 263 powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; 264 ti,deskew = <0>; 265 266 ports { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 270 port@0 { 271 reg = <0>; 272 273 tfp410_in: endpoint { 274 remote-endpoint = <&dpi1_out>; 275 pclk-sample = <1>; 276 }; 277 }; 278 279 port@1 { 280 reg = <1>; 281 282 tfp410_out: endpoint { 283 remote-endpoint = 284 <&hdmi_connector_in>; 285 }; 286 }; 287 }; 288 }; 289}; 290 291&main_pmx0 { 292 main_mmc1_pins_default: main-mmc1-default-pins { 293 pinctrl-single,pins = < 294 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 295 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 296 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 297 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 298 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 299 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 300 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 301 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 302 >; 303 }; 304 305 main_uart0_pins_default: main-uart0-default-pins { 306 pinctrl-single,pins = < 307 J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ 308 J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ 309 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ 310 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ 311 >; 312 }; 313 314 main_uart1_pins_default: main-uart1-default-pins { 315 pinctrl-single,pins = < 316 J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ 317 J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ 318 >; 319 }; 320 321 main_i2c0_pins_default: main-i2c0-default-pins { 322 pinctrl-single,pins = < 323 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 324 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 325 >; 326 }; 327 328 main_i2c1_pins_default: main-i2c1-default-pins { 329 pinctrl-single,pins = < 330 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 331 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 332 >; 333 }; 334 335 main_i2c3_pins_default: main-i2c3-default-pins { 336 pinctrl-single,pins = < 337 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 338 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 339 >; 340 }; 341 342 main_usbss0_pins_default: main-usbss0-default-pins { 343 pinctrl-single,pins = < 344 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 345 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 346 >; 347 }; 348 349 main_usbss1_pins_default: main-usbss1-default-pins { 350 pinctrl-single,pins = < 351 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 352 >; 353 }; 354 355 dp0_pins_default: dp0-default-pins { 356 pinctrl-single,pins = < 357 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ 358 >; 359 }; 360 361 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 362 pinctrl-single,pins = < 363 J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ 364 >; 365 }; 366 367 dss_vout0_pins_default: dss-vout0-default-pins { 368 pinctrl-single,pins = < 369 J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ 370 J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ 371 J721E_IOPAD(0x60, PIN_OUTPUT, 10) /* (AF23) PRG1_PRU1_GPO2.VOUT0_DATA2 */ 372 J721E_IOPAD(0x64, PIN_OUTPUT, 10) /* (AD23) PRG1_PRU1_GPO3.VOUT0_DATA3 */ 373 J721E_IOPAD(0x68, PIN_OUTPUT, 10) /* (AH24) PRG1_PRU1_GPO4.VOUT0_DATA4 */ 374 J721E_IOPAD(0x6c, PIN_OUTPUT, 10) /* (AG21) PRG1_PRU1_GPO5.VOUT0_DATA5 */ 375 J721E_IOPAD(0x70, PIN_OUTPUT, 10) /* (AE23) PRG1_PRU1_GPO6.VOUT0_DATA6 */ 376 J721E_IOPAD(0x74, PIN_OUTPUT, 10) /* (AC21) PRG1_PRU1_GPO7.VOUT0_DATA7 */ 377 J721E_IOPAD(0x78, PIN_OUTPUT, 10) /* (Y23) PRG1_PRU1_GPO8.VOUT0_DATA8 */ 378 J721E_IOPAD(0x7c, PIN_OUTPUT, 10) /* (AF21) PRG1_PRU1_GPO9.VOUT0_DATA9 */ 379 J721E_IOPAD(0x80, PIN_OUTPUT, 10) /* (AB23) PRG1_PRU1_GPO10.VOUT0_DATA10 */ 380 J721E_IOPAD(0x84, PIN_OUTPUT, 10) /* (AJ25) PRG1_PRU1_GPO11.VOUT0_DATA11 */ 381 J721E_IOPAD(0x88, PIN_OUTPUT, 10) /* (AH25) PRG1_PRU1_GPO12.VOUT0_DATA12 */ 382 J721E_IOPAD(0x8c, PIN_OUTPUT, 10) /* (AG25) PRG1_PRU1_GPO13.VOUT0_DATA13 */ 383 J721E_IOPAD(0x90, PIN_OUTPUT, 10) /* (AH26) PRG1_PRU1_GPO14.VOUT0_DATA14 */ 384 J721E_IOPAD(0x94, PIN_OUTPUT, 10) /* (AJ27) PRG1_PRU1_GPO15.VOUT0_DATA15 */ 385 J721E_IOPAD(0x30, PIN_OUTPUT, 10) /* (AF24) PRG1_PRU0_GPO11.VOUT0_DATA16 */ 386 J721E_IOPAD(0x34, PIN_OUTPUT, 10) /* (AJ24) PRG1_PRU0_GPO12.VOUT0_DATA17 */ 387 J721E_IOPAD(0x38, PIN_OUTPUT, 10) /* (AG24) PRG1_PRU0_GPO13.VOUT0_DATA18 */ 388 J721E_IOPAD(0x3c, PIN_OUTPUT, 10) /* (AD24) PRG1_PRU0_GPO14.VOUT0_DATA19 */ 389 J721E_IOPAD(0x40, PIN_OUTPUT, 10) /* (AC24) PRG1_PRU0_GPO15.VOUT0_DATA20 */ 390 J721E_IOPAD(0x44, PIN_OUTPUT, 10) /* (AE24) PRG1_PRU0_GPO16.VOUT0_DATA21 */ 391 J721E_IOPAD(0x24, PIN_OUTPUT, 10) /* (AJ20) PRG1_PRU0_GPO8.VOUT0_DATA22 */ 392 J721E_IOPAD(0x28, PIN_OUTPUT, 10) /* (AG20) PRG1_PRU0_GPO9.VOUT0_DATA23 */ 393 J721E_IOPAD(0x9c, PIN_OUTPUT, 10) /* (AC22) PRG1_PRU1_GPO17.VOUT0_DE */ 394 J721E_IOPAD(0x98, PIN_OUTPUT, 10) /* (AJ26) PRG1_PRU1_GPO16.VOUT0_HSYNC */ 395 J721E_IOPAD(0xa4, PIN_OUTPUT, 10) /* (AH22) PRG1_PRU1_GPO19.VOUT0_PCLK */ 396 J721E_IOPAD(0xa0, PIN_OUTPUT, 10) /* (AJ22) PRG1_PRU1_GPO18.VOUT0_VSYNC */ 397 >; 398 }; 399 400 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 401 pinctrl-single,pins = < 402 J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ 403 >; 404 }; 405 406 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 407 pinctrl-single,pins = < 408 J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ 409 >; 410 }; 411 412 /* Reset for M.2 E Key slot on PCIe0 */ 413 ekey_reset_pins_default: ekey-reset-pns-default-pins { 414 pinctrl-single,pins = < 415 J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ 416 >; 417 }; 418 419 main_i2c5_pins_default: main-i2c5-default-pins { 420 pinctrl-single,pins = < 421 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ 422 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ 423 >; 424 }; 425 426 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 427 pinctrl-single,pins = < 428 J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ 429 J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ 430 J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ 431 J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ 432 J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ 433 J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ 434 J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ 435 J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ 436 J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ 437 J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ 438 J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ 439 J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ 440 J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ 441 J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ 442 J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ 443 J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ 444 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ 445 J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ 446 J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ 447 J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ 448 J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ 449 J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ 450 J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ 451 >; 452 }; 453 454 rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { 455 pinctrl-single,pins = < 456 J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ 457 >; 458 }; 459}; 460 461&wkup_pmx0 { 462 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 463 pinctrl-single,pins = < 464 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ 465 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ 466 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ 467 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ 468 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ 469 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ 470 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ 471 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ 472 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ 473 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ 474 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ 475 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ 476 >; 477 }; 478 479 mcu_mdio_pins_default: mcu-mdio1-default-pins { 480 pinctrl-single,pins = < 481 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ 482 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ 483 >; 484 }; 485 486 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 487 pinctrl-single,pins = < 488 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ 489 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ 490 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ 491 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ 492 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ 493 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ 494 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ 495 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ 496 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ 497 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ 498 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ 499 >; 500 }; 501 502 vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { 503 pinctrl-single,pins = < 504 J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ 505 >; 506 }; 507 508 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { 509 pinctrl-single,pins = < 510 J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ 511 >; 512 }; 513 514 wkup_uart0_pins_default: wkup-uart0-default-pins { 515 pinctrl-single,pins = < 516 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ 517 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ 518 >; 519 }; 520 521 mcu_uart0_pins_default: mcu-uart0-default-pins { 522 pinctrl-single,pins = < 523 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ 524 J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ 525 J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ 526 J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ 527 >; 528 }; 529 530 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 531 pinctrl-single,pins = < 532 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ 533 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ 534 >; 535 }; 536 537 /* Reset for M.2 M Key slot on PCIe1 */ 538 mkey_reset_pins_default: mkey-reset-pns-default-pins { 539 pinctrl-single,pins = < 540 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ 541 >; 542 }; 543}; 544 545&wkup_uart0 { 546 /* Wakeup UART is used by System firmware */ 547 status = "reserved"; 548 pinctrl-names = "default"; 549 pinctrl-0 = <&wkup_uart0_pins_default>; 550}; 551 552&wkup_i2c0 { 553 status = "okay"; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&wkup_i2c0_pins_default>; 556 clock-frequency = <400000>; 557 558 eeprom@51 { 559 /* AT24C512C-MAHM-T */ 560 compatible = "atmel,24c512"; 561 reg = <0x51>; 562 }; 563}; 564 565&mcu_uart0 { 566 status = "okay"; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&mcu_uart0_pins_default>; 569}; 570 571&main_uart0 { 572 status = "okay"; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&main_uart0_pins_default>; 575 /* Shared with ATF on this platform */ 576 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 577}; 578 579&main_uart1 { 580 status = "okay"; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&main_uart1_pins_default>; 583}; 584 585&main_sdhci1 { 586 /* SD Card */ 587 status = "okay"; 588 vmmc-supply = <&vdd_mmc1>; 589 vqmmc-supply = <&vdd_sd_dv_alt>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&main_mmc1_pins_default>; 592 ti,driver-strength-ohm = <50>; 593 disable-wp; 594}; 595 596&ospi0 { 597 status = "okay"; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 600 601 flash@0 { 602 compatible = "jedec,spi-nor"; 603 reg = <0x0>; 604 spi-tx-bus-width = <8>; 605 spi-rx-bus-width = <8>; 606 spi-max-frequency = <25000000>; 607 cdns,tshsl-ns = <60>; 608 cdns,tsd2d-ns = <60>; 609 cdns,tchsh-ns = <60>; 610 cdns,tslch-ns = <60>; 611 cdns,read-delay = <4>; 612 613 partitions { 614 compatible = "fixed-partitions"; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 618 partition@0 { 619 label = "ospi.tiboot3"; 620 reg = <0x0 0x80000>; 621 }; 622 623 partition@80000 { 624 label = "ospi.tispl"; 625 reg = <0x80000 0x200000>; 626 }; 627 628 partition@280000 { 629 label = "ospi.u-boot"; 630 reg = <0x280000 0x400000>; 631 }; 632 633 partition@680000 { 634 label = "ospi.env"; 635 reg = <0x680000 0x40000>; 636 }; 637 638 partition@6c0000 { 639 label = "ospi.sysfw"; 640 reg = <0x6c0000 0x100000>; 641 }; 642 643 partition@7c0000 { 644 label = "ospi.env.backup"; 645 reg = <0x7c0000 0x40000>; 646 }; 647 648 partition@800000 { 649 label = "ospi.rootfs"; 650 reg = <0x800000 0x37c0000>; 651 }; 652 653 partition@3fc0000 { 654 label = "ospi.phypattern"; 655 reg = <0x3fc0000 0x40000>; 656 }; 657 }; 658 }; 659}; 660 661&main_i2c0 { 662 status = "okay"; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&main_i2c0_pins_default>; 665 clock-frequency = <400000>; 666 667 i2c-mux@71 { 668 compatible = "nxp,pca9543"; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 reg = <0x71>; 672 673 /* PCIe1 M.2 M Key I2C */ 674 i2c@0 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 reg = <0>; 678 }; 679 680 /* PCIe0 M.2 E Key I2C */ 681 i2c@1 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 reg = <1>; 685 }; 686 }; 687}; 688 689&main_i2c1 { 690 status = "okay"; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&main_i2c1_pins_default>; 693 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 694 clock-frequency = <100000>; 695}; 696 697&main_i2c3 { 698 status = "okay"; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&main_i2c3_pins_default>; 701 clock-frequency = <400000>; 702 703 i2c-mux@70 { 704 compatible = "nxp,pca9543"; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 reg = <0x70>; 708 709 /* CSI0 I2C */ 710 i2c@0 { 711 #address-cells = <1>; 712 #size-cells = <0>; 713 reg = <0>; 714 }; 715 716 /* CSI1 I2C */ 717 i2c@1 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 reg = <1>; 721 }; 722 }; 723}; 724 725&main_i2c5 { 726 /* Brought out on RPi Header */ 727 status = "okay"; 728 pinctrl-names = "default"; 729 pinctrl-0 = <&main_i2c5_pins_default>; 730 clock-frequency = <400000>; 731}; 732 733&main_gpio0 { 734 status = "okay"; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 737}; 738 739&main_gpio1 { 740 status = "okay"; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&rpi_header_gpio1_pins_default>; 743}; 744 745&wkup_gpio0 { 746 status = "okay"; 747}; 748 749&usb_serdes_mux { 750 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 751}; 752 753&serdes_ln_ctrl { 754 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_IP4_UNUSED>, 755 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 756 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, 757 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 758 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 759 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 760}; 761 762&serdes_wiz3 { 763 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 764 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 765}; 766 767&serdes3 { 768 serdes3_usb_link: phy@0 { 769 reg = <0>; 770 cdns,num-lanes = <2>; 771 #phy-cells = <0>; 772 cdns,phy-type = <PHY_TYPE_USB3>; 773 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 774 }; 775}; 776 777&serdes4 { 778 torrent_phy_dp: phy@0 { 779 reg = <0>; 780 resets = <&serdes_wiz4 1>; 781 cdns,phy-type = <PHY_TYPE_DP>; 782 cdns,num-lanes = <4>; 783 cdns,max-bit-rate = <5400>; 784 #phy-cells = <0>; 785 }; 786}; 787 788&mhdp { 789 phys = <&torrent_phy_dp>; 790 phy-names = "dpphy"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&dp0_pins_default>; 793}; 794 795&usbss0 { 796 pinctrl-names = "default"; 797 pinctrl-0 = <&main_usbss0_pins_default>; 798 ti,vbus-divider; 799}; 800 801&usb0 { 802 dr_mode = "otg"; 803 maximum-speed = "super-speed"; 804 phys = <&serdes3_usb_link>; 805 phy-names = "cdns3,usb3-phy"; 806}; 807 808&serdes2 { 809 serdes2_usb_link: phy@1 { 810 reg = <1>; 811 cdns,num-lanes = <1>; 812 #phy-cells = <0>; 813 cdns,phy-type = <PHY_TYPE_USB3>; 814 resets = <&serdes_wiz2 2>; 815 }; 816}; 817 818&usbss1 { 819 pinctrl-names = "default"; 820 pinctrl-0 = <&main_usbss1_pins_default>; 821 ti,vbus-divider; 822}; 823 824&usb1 { 825 dr_mode = "host"; 826 maximum-speed = "super-speed"; 827 phys = <&serdes2_usb_link>; 828 phy-names = "cdns3,usb3-phy"; 829}; 830 831&mcu_cpsw { 832 pinctrl-names = "default"; 833 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 834}; 835 836&davinci_mdio { 837 phy0: ethernet-phy@0 { 838 reg = <0>; 839 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 840 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 841 }; 842}; 843 844&cpsw_port1 { 845 phy-mode = "rgmii-rxid"; 846 phy-handle = <&phy0>; 847}; 848 849&dss { 850 pinctrl-names = "default"; 851 pinctrl-0 = <&dss_vout0_pins_default>; 852 853 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ 854 <&k3_clks 152 4>, /* VP 2 pixel clock */ 855 <&k3_clks 152 9>, /* VP 3 pixel clock */ 856 <&k3_clks 152 13>; /* VP 4 pixel clock */ 857 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 858 <&k3_clks 152 6>, /* DPI0_EXT_CLKSEL_OUT0 */ 859 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 860 <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ 861}; 862 863&dss_ports { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 867 port@0 { 868 reg = <0>; 869 870 dpi0_out: endpoint { 871 remote-endpoint = <&dp0_in>; 872 }; 873 }; 874 875 port@1 { 876 reg = <1>; 877 878 dpi1_out: endpoint { 879 remote-endpoint = <&tfp410_in>; 880 }; 881 }; 882}; 883 884&dp0_ports { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 port@0 { 889 reg = <0>; 890 dp0_in: endpoint { 891 remote-endpoint = <&dpi0_out>; 892 }; 893 }; 894 895 port@4 { 896 reg = <4>; 897 dp0_out: endpoint { 898 remote-endpoint = <&dp_connector_in>; 899 }; 900 }; 901}; 902 903&serdes0 { 904 serdes0_pcie_link: phy@0 { 905 reg = <0>; 906 cdns,num-lanes = <1>; 907 #phy-cells = <0>; 908 cdns,phy-type = <PHY_TYPE_PCIE>; 909 resets = <&serdes_wiz0 1>; 910 }; 911}; 912 913&serdes1 { 914 serdes1_pcie_link: phy@0 { 915 reg = <0>; 916 cdns,num-lanes = <2>; 917 #phy-cells = <0>; 918 cdns,phy-type = <PHY_TYPE_PCIE>; 919 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 920 }; 921}; 922 923&pcie0_rc { 924 status = "okay"; 925 pinctrl-names = "default"; 926 pinctrl-0 = <&ekey_reset_pins_default>; 927 reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; 928 929 phys = <&serdes0_pcie_link>; 930 phy-names = "pcie-phy"; 931 num-lanes = <1>; 932}; 933 934&pcie1_rc { 935 status = "okay"; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&mkey_reset_pins_default>; 938 reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; 939 940 phys = <&serdes1_pcie_link>; 941 phy-names = "pcie-phy"; 942 num-lanes = <2>; 943}; 944 945&ufs_wrapper { 946 status = "disabled"; 947}; 948 949&mailbox0_cluster0 { 950 status = "okay"; 951 interrupts = <436>; 952 953 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 954 ti,mbox-rx = <0 0 0>; 955 ti,mbox-tx = <1 0 0>; 956 }; 957 958 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 959 ti,mbox-rx = <2 0 0>; 960 ti,mbox-tx = <3 0 0>; 961 }; 962}; 963 964&mailbox0_cluster1 { 965 status = "okay"; 966 interrupts = <432>; 967 968 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 969 ti,mbox-rx = <0 0 0>; 970 ti,mbox-tx = <1 0 0>; 971 }; 972 973 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 974 ti,mbox-rx = <2 0 0>; 975 ti,mbox-tx = <3 0 0>; 976 }; 977}; 978 979&mailbox0_cluster2 { 980 status = "okay"; 981 interrupts = <428>; 982 983 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 984 ti,mbox-rx = <0 0 0>; 985 ti,mbox-tx = <1 0 0>; 986 }; 987 988 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 989 ti,mbox-rx = <2 0 0>; 990 ti,mbox-tx = <3 0 0>; 991 }; 992}; 993 994&mailbox0_cluster3 { 995 status = "okay"; 996 interrupts = <424>; 997 998 mbox_c66_0: mbox-c66-0 { 999 ti,mbox-rx = <0 0 0>; 1000 ti,mbox-tx = <1 0 0>; 1001 }; 1002 1003 mbox_c66_1: mbox-c66-1 { 1004 ti,mbox-rx = <2 0 0>; 1005 ti,mbox-tx = <3 0 0>; 1006 }; 1007}; 1008 1009&mailbox0_cluster4 { 1010 status = "okay"; 1011 interrupts = <420>; 1012 1013 mbox_c71_0: mbox-c71-0 { 1014 ti,mbox-rx = <0 0 0>; 1015 ti,mbox-tx = <1 0 0>; 1016 }; 1017}; 1018 1019&mcu_r5fss0_core0 { 1020 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; 1021 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1022 <&mcu_r5fss0_core0_memory_region>; 1023}; 1024 1025&mcu_r5fss0_core1 { 1026 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; 1027 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1028 <&mcu_r5fss0_core1_memory_region>; 1029}; 1030 1031&main_r5fss0_core0 { 1032 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; 1033 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1034 <&main_r5fss0_core0_memory_region>; 1035}; 1036 1037&main_r5fss0_core1 { 1038 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; 1039 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1040 <&main_r5fss0_core1_memory_region>; 1041}; 1042 1043&main_r5fss1_core0 { 1044 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; 1045 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1046 <&main_r5fss1_core0_memory_region>; 1047}; 1048 1049&main_r5fss1_core1 { 1050 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; 1051 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1052 <&main_r5fss1_core1_memory_region>; 1053}; 1054 1055&c66_0 { 1056 status = "okay"; 1057 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; 1058 memory-region = <&c66_0_dma_memory_region>, 1059 <&c66_0_memory_region>; 1060}; 1061 1062&c66_1 { 1063 status = "okay"; 1064 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; 1065 memory-region = <&c66_1_dma_memory_region>, 1066 <&c66_1_memory_region>; 1067}; 1068 1069&c71_0 { 1070 status = "okay"; 1071 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; 1072 memory-region = <&c71_0_dma_memory_region>, 1073 <&c71_0_memory_region>; 1074}; 1075