1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial1 = &mcu_uart0; 25 serial2 = &main_uart8; 26 mmc0 = &main_sdhci0; 27 mmc1 = &main_sdhci1; 28 i2c0 = &wkup_i2c0; 29 i2c3 = &main_i2c0; 30 ethernet0 = &mcu_cpsw_port1; 31 ethernet1 = &main_cpsw1_port1; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 bootph-all; 37 /* 32G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 39 <0x00000008 0x80000000 0x00000007 0x80000000>; 40 }; 41 42 reserved_memory: reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 secure_ddr: optee@9e800000 { 48 reg = <0x00 0x9e800000 0x00 0x01800000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1000000 0x00 0x100000>; 67 no-map; 68 }; 69 70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa1100000 0x00 0xf00000>; 73 no-map; 74 }; 75 76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2000000 0x00 0x100000>; 79 no-map; 80 }; 81 82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa2100000 0x00 0xf00000>; 85 no-map; 86 }; 87 88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3000000 0x00 0x100000>; 91 no-map; 92 }; 93 94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa3100000 0x00 0xf00000>; 97 no-map; 98 }; 99 100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa4000000 0x00 0x100000>; 103 no-map; 104 }; 105 106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa4100000 0x00 0xf00000>; 109 no-map; 110 }; 111 112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa5000000 0x00 0x100000>; 115 no-map; 116 }; 117 118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa5100000 0x00 0xf00000>; 121 no-map; 122 }; 123 124 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa6000000 0x00 0x100000>; 127 no-map; 128 }; 129 130 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa6100000 0x00 0xf00000>; 133 no-map; 134 }; 135 136 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa7000000 0x00 0x100000>; 139 no-map; 140 }; 141 142 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa7100000 0x00 0xf00000>; 145 no-map; 146 }; 147 148 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 149 compatible = "shared-dma-pool"; 150 reg = <0x00 0xa8000000 0x00 0x100000>; 151 no-map; 152 }; 153 154 c71_0_memory_region: c71-memory@a8100000 { 155 compatible = "shared-dma-pool"; 156 reg = <0x00 0xa8100000 0x00 0xf00000>; 157 no-map; 158 }; 159 160 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 161 compatible = "shared-dma-pool"; 162 reg = <0x00 0xa9000000 0x00 0x100000>; 163 no-map; 164 }; 165 166 c71_1_memory_region: c71-memory@a9100000 { 167 compatible = "shared-dma-pool"; 168 reg = <0x00 0xa9100000 0x00 0xf00000>; 169 no-map; 170 }; 171 172 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 173 compatible = "shared-dma-pool"; 174 reg = <0x00 0xaa000000 0x00 0x100000>; 175 no-map; 176 }; 177 178 c71_2_memory_region: c71-memory@aa100000 { 179 compatible = "shared-dma-pool"; 180 reg = <0x00 0xaa100000 0x00 0xf00000>; 181 no-map; 182 }; 183 184 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 185 compatible = "shared-dma-pool"; 186 reg = <0x00 0xab000000 0x00 0x100000>; 187 no-map; 188 }; 189 190 c71_3_memory_region: c71-memory@ab100000 { 191 compatible = "shared-dma-pool"; 192 reg = <0x00 0xab100000 0x00 0xf00000>; 193 no-map; 194 }; 195 }; 196 197 evm_12v0: regulator-evm12v0 { 198 /* main supply */ 199 compatible = "regulator-fixed"; 200 regulator-name = "evm_12v0"; 201 regulator-min-microvolt = <12000000>; 202 regulator-max-microvolt = <12000000>; 203 regulator-always-on; 204 regulator-boot-on; 205 }; 206 207 vsys_3v3: regulator-vsys3v3 { 208 /* Output of LM5140 */ 209 compatible = "regulator-fixed"; 210 regulator-name = "vsys_3v3"; 211 regulator-min-microvolt = <3300000>; 212 regulator-max-microvolt = <3300000>; 213 vin-supply = <&evm_12v0>; 214 regulator-always-on; 215 regulator-boot-on; 216 }; 217 218 vsys_5v0: regulator-vsys5v0 { 219 /* Output of LM5140 */ 220 compatible = "regulator-fixed"; 221 regulator-name = "vsys_5v0"; 222 regulator-min-microvolt = <5000000>; 223 regulator-max-microvolt = <5000000>; 224 vin-supply = <&evm_12v0>; 225 regulator-always-on; 226 regulator-boot-on; 227 }; 228 229 vdd_mmc1: regulator-sd { 230 /* Output of TPS22918 */ 231 compatible = "regulator-fixed"; 232 regulator-name = "vdd_mmc1"; 233 regulator-min-microvolt = <3300000>; 234 regulator-max-microvolt = <3300000>; 235 regulator-boot-on; 236 enable-active-high; 237 vin-supply = <&vsys_3v3>; 238 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 239 }; 240 241 vdd_sd_dv: regulator-TLV71033 { 242 /* Output of TLV71033 */ 243 compatible = "regulator-gpio"; 244 regulator-name = "tlv71033"; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&vdd_sd_dv_pins_default>; 247 regulator-min-microvolt = <1800000>; 248 regulator-max-microvolt = <3300000>; 249 regulator-boot-on; 250 vin-supply = <&vsys_5v0>; 251 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 252 states = <1800000 0x0>, 253 <3300000 0x1>; 254 }; 255 256 dp0_pwr_3v3: regulator-dp0-prw { 257 compatible = "regulator-fixed"; 258 regulator-name = "dp0-pwr"; 259 regulator-min-microvolt = <3300000>; 260 regulator-max-microvolt = <3300000>; 261 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; 262 enable-active-high; 263 }; 264 265 dp0: connector-dp0 { 266 compatible = "dp-connector"; 267 label = "DP0"; 268 type = "full-size"; 269 dp-pwr-supply = <&dp0_pwr_3v3>; 270 271 port { 272 dp0_connector_in: endpoint { 273 remote-endpoint = <&dp0_out>; 274 }; 275 }; 276 }; 277 278 transceiver0: can-phy0 { 279 compatible = "ti,tcan1042"; 280 #phy-cells = <0>; 281 max-bitrate = <5000000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 284 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; 285 }; 286 287 transceiver1: can-phy1 { 288 compatible = "ti,tcan1042"; 289 #phy-cells = <0>; 290 max-bitrate = <5000000>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 293 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 294 }; 295 296 transceiver2: can-phy2 { 297 /* standby pin has been grounded by default */ 298 compatible = "ti,tcan1042"; 299 #phy-cells = <0>; 300 max-bitrate = <5000000>; 301 }; 302 303 transceiver3: can-phy3 { 304 compatible = "ti,tcan1042"; 305 #phy-cells = <0>; 306 max-bitrate = <5000000>; 307 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 308 mux-states = <&mux1 1>; 309 }; 310 311 mux1: mux-controller { 312 compatible = "gpio-mux"; 313 #mux-state-cells = <1>; 314 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; 315 idle-state = <1>; 316 }; 317 318 codec_audio: sound { 319 compatible = "ti,j7200-cpb-audio"; 320 model = "j784s4-cpb"; 321 322 ti,cpb-mcasp = <&mcasp0>; 323 ti,cpb-codec = <&pcm3168a_1>; 324 325 clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, 326 <&k3_clks 157 34>, <&k3_clks 157 63>; 327 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", 328 "cpb-codec-scki", "cpb-codec-scki-48000"; 329 }; 330}; 331 332&wkup_gpio0 { 333 status = "okay"; 334}; 335 336&main_pmx0 { 337 bootph-all; 338 main_cpsw2g_default_pins: main-cpsw2g-default-pins { 339 pinctrl-single,pins = < 340 J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ 341 J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ 342 J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ 343 J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ 344 J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ 345 J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ 346 J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ 347 J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ 348 J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ 349 J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ 350 J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ 351 J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ 352 >; 353 }; 354 355 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { 356 pinctrl-single,pins = < 357 J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ 358 J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ 359 >; 360 }; 361 362 main_uart8_pins_default: main-uart8-default-pins { 363 bootph-all; 364 pinctrl-single,pins = < 365 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 366 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 367 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 368 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 369 >; 370 }; 371 372 main_i2c0_pins_default: main-i2c0-default-pins { 373 pinctrl-single,pins = < 374 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 375 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 376 >; 377 }; 378 379 main_i2c5_pins_default: main-i2c5-default-pins { 380 pinctrl-single,pins = < 381 J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ 382 J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ 383 >; 384 }; 385 386 main_mmc1_pins_default: main-mmc1-default-pins { 387 bootph-all; 388 pinctrl-single,pins = < 389 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 390 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 391 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 392 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 393 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 394 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 395 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 396 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 397 >; 398 }; 399 400 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 401 pinctrl-single,pins = < 402 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 403 >; 404 }; 405 406 dp0_pins_default: dp0-default-pins { 407 pinctrl-single,pins = < 408 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ 409 >; 410 }; 411 412 main_i2c4_pins_default: main-i2c4-default-pins { 413 pinctrl-single,pins = < 414 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ 415 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ 416 >; 417 }; 418 419 main_mcan4_pins_default: main-mcan4-default-pins { 420 pinctrl-single,pins = < 421 J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ 422 J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ 423 >; 424 }; 425 426 main_mcan16_pins_default: main-mcan16-default-pins { 427 pinctrl-single,pins = < 428 J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ 429 J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ 430 >; 431 }; 432 433 main_usbss0_pins_default: main-usbss0-default-pins { 434 bootph-all; 435 pinctrl-single,pins = < 436 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 437 >; 438 }; 439 440 main_i2c3_pins_default: main-i2c3-default-pins { 441 pinctrl-single,pins = < 442 J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ 443 J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ 444 >; 445 }; 446 447 main_mcasp0_pins_default: main-mcasp0-default-pins { 448 pinctrl-single,pins = < 449 J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ 450 J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ 451 J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ 452 J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ 453 >; 454 }; 455 456 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 457 pinctrl-single,pins = < 458 J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ 459 >; 460 }; 461}; 462 463&wkup_pmx2 { 464 bootph-all; 465 wkup_uart0_pins_default: wkup-uart0-default-pins { 466 bootph-all; 467 pinctrl-single,pins = < 468 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 469 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 470 >; 471 }; 472 473 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 474 bootph-all; 475 pinctrl-single,pins = < 476 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 477 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 478 >; 479 }; 480 481 mcu_uart0_pins_default: mcu-uart0-default-pins { 482 bootph-all; 483 pinctrl-single,pins = < 484 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 485 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 486 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 487 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 488 >; 489 }; 490 491 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 492 pinctrl-single,pins = < 493 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 494 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 495 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 496 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 497 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 498 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 499 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 500 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 501 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 502 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 503 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 504 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 505 >; 506 }; 507 508 mcu_mdio_pins_default: mcu-mdio-default-pins { 509 pinctrl-single,pins = < 510 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 511 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 512 >; 513 }; 514 515 mcu_adc0_pins_default: mcu-adc0-default-pins { 516 pinctrl-single,pins = < 517 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 518 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 519 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 520 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 521 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 522 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 523 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 524 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 525 >; 526 }; 527 528 mcu_adc1_pins_default: mcu-adc1-default-pins { 529 pinctrl-single,pins = < 530 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 531 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 532 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 533 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 534 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 535 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 536 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 537 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 538 >; 539 }; 540 541 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 542 pinctrl-single,pins = < 543 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 544 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 545 >; 546 }; 547 548 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 549 pinctrl-single,pins = < 550 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 551 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 552 >; 553 }; 554 555 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 556 pinctrl-single,pins = < 557 J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ 558 >; 559 }; 560 561 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 562 pinctrl-single,pins = < 563 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 564 >; 565 }; 566}; 567 568&wkup_pmx1 { 569 status = "okay"; 570 571 pmic_irq_pins_default: pmic-irq-default-pins { 572 pinctrl-single,pins = < 573 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 574 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) 575 >; 576 }; 577}; 578 579&wkup_pmx0 { 580 bootph-all; 581 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 582 bootph-all; 583 pinctrl-single,pins = < 584 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 585 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 586 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 587 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 588 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 589 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 590 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 591 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 592 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 593 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 594 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 595 >; 596 }; 597}; 598 599&wkup_pmx1 { 600 bootph-all; 601 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 602 bootph-all; 603 pinctrl-single,pins = < 604 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 605 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 606 >; 607 }; 608 609 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 610 bootph-all; 611 pinctrl-single,pins = < 612 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 613 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 614 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 615 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 616 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 617 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 618 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 619 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 620 >; 621 }; 622}; 623 624&wkup_uart0 { 625 /* Firmware usage */ 626 status = "reserved"; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&wkup_uart0_pins_default>; 629}; 630 631&wkup_i2c0 { 632 bootph-all; 633 status = "okay"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&wkup_i2c0_pins_default>; 636 clock-frequency = <400000>; 637 638 eeprom@50 { 639 /* CAV24C256WE-GT3 */ 640 compatible = "atmel,24c256"; 641 reg = <0x50>; 642 }; 643 644 tps659413: pmic@48 { 645 compatible = "ti,tps6594-q1"; 646 reg = <0x48>; 647 system-power-controller; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pmic_irq_pins_default>; 650 interrupt-parent = <&wkup_gpio0>; 651 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 652 gpio-controller; 653 #gpio-cells = <2>; 654 ti,primary-pmic; 655 buck12-supply = <&vsys_3v3>; 656 buck3-supply = <&vsys_3v3>; 657 buck4-supply = <&vsys_3v3>; 658 buck5-supply = <&vsys_3v3>; 659 ldo1-supply = <&vsys_3v3>; 660 ldo2-supply = <&vsys_3v3>; 661 ldo3-supply = <&vsys_3v3>; 662 ldo4-supply = <&vsys_3v3>; 663 664 regulators { 665 bucka12: buck12 { 666 regulator-name = "vdd_ddr_1v1"; 667 regulator-min-microvolt = <1100000>; 668 regulator-max-microvolt = <1100000>; 669 regulator-boot-on; 670 regulator-always-on; 671 }; 672 673 bucka3: buck3 { 674 regulator-name = "vdd_ram_0v85"; 675 regulator-min-microvolt = <850000>; 676 regulator-max-microvolt = <850000>; 677 regulator-boot-on; 678 regulator-always-on; 679 }; 680 681 bucka4: buck4 { 682 regulator-name = "vdd_io_1v8"; 683 regulator-min-microvolt = <1800000>; 684 regulator-max-microvolt = <1800000>; 685 regulator-boot-on; 686 regulator-always-on; 687 }; 688 689 bucka5: buck5 { 690 regulator-name = "vdd_mcu_0v85"; 691 regulator-min-microvolt = <850000>; 692 regulator-max-microvolt = <850000>; 693 regulator-boot-on; 694 regulator-always-on; 695 }; 696 697 ldoa1: ldo1 { 698 regulator-name = "vdd_mcuio_1v8"; 699 regulator-min-microvolt = <1800000>; 700 regulator-max-microvolt = <1800000>; 701 regulator-boot-on; 702 regulator-always-on; 703 }; 704 705 ldoa2: ldo2 { 706 regulator-name = "vdd_mcuio_3v3"; 707 regulator-min-microvolt = <3300000>; 708 regulator-max-microvolt = <3300000>; 709 regulator-boot-on; 710 regulator-always-on; 711 }; 712 713 ldoa3: ldo3 { 714 regulator-name = "vds_dll_0v8"; 715 regulator-min-microvolt = <800000>; 716 regulator-max-microvolt = <800000>; 717 regulator-boot-on; 718 regulator-always-on; 719 }; 720 721 ldoa4: ldo4 { 722 regulator-name = "vda_mcu_1v8"; 723 regulator-min-microvolt = <1800000>; 724 regulator-max-microvolt = <1800000>; 725 regulator-boot-on; 726 regulator-always-on; 727 }; 728 }; 729 }; 730 731 tps62873a: regulator@40 { 732 compatible = "ti,tps62873"; 733 reg = <0x40>; 734 bootph-pre-ram; 735 regulator-name = "VDD_CPU_AVS"; 736 regulator-min-microvolt = <750000>; 737 regulator-max-microvolt = <1330000>; 738 regulator-boot-on; 739 regulator-always-on; 740 }; 741 742 tps62873b: regulator@43 { 743 compatible = "ti,tps62873"; 744 reg = <0x43>; 745 regulator-name = "VDD_CORE_0V8"; 746 regulator-min-microvolt = <760000>; 747 regulator-max-microvolt = <840000>; 748 regulator-boot-on; 749 regulator-always-on; 750 }; 751}; 752 753&mcu_uart0 { 754 bootph-all; 755 status = "okay"; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&mcu_uart0_pins_default>; 758}; 759 760&main_uart8 { 761 bootph-all; 762 status = "okay"; 763 pinctrl-names = "default"; 764 pinctrl-0 = <&main_uart8_pins_default>; 765}; 766 767&ufs_wrapper { 768 status = "okay"; 769}; 770 771&fss { 772 bootph-all; 773 status = "okay"; 774}; 775 776&ospi0 { 777 bootph-all; 778 status = "okay"; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 781 782 flash@0 { 783 bootph-all; 784 compatible = "jedec,spi-nor"; 785 reg = <0x0>; 786 spi-tx-bus-width = <8>; 787 spi-rx-bus-width = <8>; 788 spi-max-frequency = <25000000>; 789 cdns,tshsl-ns = <60>; 790 cdns,tsd2d-ns = <60>; 791 cdns,tchsh-ns = <60>; 792 cdns,tslch-ns = <60>; 793 cdns,read-delay = <4>; 794 795 partitions { 796 compatible = "fixed-partitions"; 797 #address-cells = <1>; 798 #size-cells = <1>; 799 800 partition@0 { 801 label = "ospi.tiboot3"; 802 reg = <0x0 0x80000>; 803 }; 804 805 partition@80000 { 806 label = "ospi.tispl"; 807 reg = <0x80000 0x200000>; 808 }; 809 810 partition@280000 { 811 label = "ospi.u-boot"; 812 reg = <0x280000 0x400000>; 813 }; 814 815 partition@680000 { 816 label = "ospi.env"; 817 reg = <0x680000 0x40000>; 818 }; 819 820 partition@6c0000 { 821 label = "ospi.env.backup"; 822 reg = <0x6c0000 0x40000>; 823 }; 824 825 partition@800000 { 826 label = "ospi.rootfs"; 827 reg = <0x800000 0x37c0000>; 828 }; 829 830 partition@3fc0000 { 831 bootph-all; 832 label = "ospi.phypattern"; 833 reg = <0x3fc0000 0x40000>; 834 }; 835 }; 836 }; 837}; 838 839&ospi1 { 840 bootph-all; 841 status = "okay"; 842 pinctrl-names = "default"; 843 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 844 845 flash@0 { 846 bootph-all; 847 compatible = "jedec,spi-nor"; 848 reg = <0x0>; 849 spi-tx-bus-width = <1>; 850 spi-rx-bus-width = <4>; 851 spi-max-frequency = <40000000>; 852 cdns,tshsl-ns = <60>; 853 cdns,tsd2d-ns = <60>; 854 cdns,tchsh-ns = <60>; 855 cdns,tslch-ns = <60>; 856 cdns,read-delay = <2>; 857 858 partitions { 859 compatible = "fixed-partitions"; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 863 partition@0 { 864 label = "qspi.tiboot3"; 865 reg = <0x0 0x80000>; 866 }; 867 868 partition@80000 { 869 label = "qspi.tispl"; 870 reg = <0x80000 0x200000>; 871 }; 872 873 partition@280000 { 874 label = "qspi.u-boot"; 875 reg = <0x280000 0x400000>; 876 }; 877 878 partition@680000 { 879 label = "qspi.env"; 880 reg = <0x680000 0x40000>; 881 }; 882 883 partition@6c0000 { 884 label = "qspi.env.backup"; 885 reg = <0x6c0000 0x40000>; 886 }; 887 888 partition@800000 { 889 label = "qspi.rootfs"; 890 reg = <0x800000 0x37c0000>; 891 }; 892 893 partition@3fc0000 { 894 bootph-all; 895 label = "qspi.phypattern"; 896 reg = <0x3fc0000 0x40000>; 897 }; 898 }; 899 900 }; 901}; 902 903&main_i2c0 { 904 status = "okay"; 905 pinctrl-names = "default"; 906 pinctrl-0 = <&main_i2c0_pins_default>; 907 908 clock-frequency = <400000>; 909 910 exp1: gpio@20 { 911 compatible = "ti,tca6416"; 912 reg = <0x20>; 913 gpio-controller; 914 #gpio-cells = <2>; 915 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 916 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 917 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 918 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 919 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 920 921 p12-hog { 922 /* P12 - AUDIO_MUX_SEL */ 923 gpio-hog; 924 gpios = <12 GPIO_ACTIVE_HIGH>; 925 output-low; 926 line-name = "AUDIO_MUX_SEL"; 927 }; 928 }; 929 930 exp2: gpio@22 { 931 compatible = "ti,tca6424"; 932 reg = <0x22>; 933 gpio-controller; 934 #gpio-cells = <2>; 935 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 936 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 937 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 938 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 939 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 940 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 941 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 942 "USER_INPUT1", "USER_LED1", "USER_LED2"; 943 944 p13-hog { 945 /* P13 - CANUART_MUX_SEL0 */ 946 gpio-hog; 947 gpios = <13 GPIO_ACTIVE_HIGH>; 948 output-high; 949 line-name = "CANUART_MUX_SEL0"; 950 }; 951 952 p15-hog { 953 /* P15 - CANUART_MUX1_SEL1 */ 954 gpio-hog; 955 gpios = <15 GPIO_ACTIVE_HIGH>; 956 output-high; 957 line-name = "CANUART_MUX1_SEL1"; 958 }; 959 }; 960}; 961 962&main_i2c5 { 963 pinctrl-names = "default"; 964 pinctrl-0 = <&main_i2c5_pins_default>; 965 clock-frequency = <400000>; 966 status = "okay"; 967 968 exp5: gpio@20 { 969 compatible = "ti,tca6408"; 970 reg = <0x20>; 971 gpio-controller; 972 #gpio-cells = <2>; 973 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", 974 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", 975 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", 976 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; 977 }; 978}; 979 980&main_sdhci0 { 981 bootph-all; 982 /* eMMC */ 983 status = "okay"; 984 non-removable; 985 ti,driver-strength-ohm = <50>; 986 disable-wp; 987}; 988 989&main_sdhci1 { 990 bootph-all; 991 /* SD card */ 992 status = "okay"; 993 pinctrl-0 = <&main_mmc1_pins_default>; 994 pinctrl-names = "default"; 995 disable-wp; 996 vmmc-supply = <&vdd_mmc1>; 997 vqmmc-supply = <&vdd_sd_dv>; 998}; 999 1000&main_gpio0 { 1001 status = "okay"; 1002}; 1003 1004&mcu_cpsw { 1005 status = "okay"; 1006 pinctrl-names = "default"; 1007 pinctrl-0 = <&mcu_cpsw_pins_default>; 1008}; 1009 1010&davinci_mdio { 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&mcu_mdio_pins_default>; 1013 1014 mcu_phy0: ethernet-phy@0 { 1015 reg = <0>; 1016 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1017 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1018 ti,min-output-impedance; 1019 }; 1020}; 1021 1022&mcu_cpsw_port1 { 1023 status = "okay"; 1024 phy-mode = "rgmii-rxid"; 1025 phy-handle = <&mcu_phy0>; 1026}; 1027 1028&main_cpsw1 { 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&main_cpsw2g_default_pins>; 1031 status = "okay"; 1032}; 1033 1034&main_cpsw1_mdio { 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; 1037 status = "okay"; 1038 1039 main_cpsw1_phy0: ethernet-phy@0 { 1040 reg = <0>; 1041 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1042 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1043 ti,min-output-impedance; 1044 }; 1045}; 1046 1047&main_cpsw1_port1 { 1048 phy-mode = "rgmii-rxid"; 1049 phy-handle = <&main_cpsw1_phy0>; 1050 status = "okay"; 1051}; 1052 1053&mailbox0_cluster0 { 1054 status = "okay"; 1055 interrupts = <436>; 1056 1057 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1058 ti,mbox-rx = <0 0 0>; 1059 ti,mbox-tx = <1 0 0>; 1060 }; 1061 1062 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1063 ti,mbox-rx = <2 0 0>; 1064 ti,mbox-tx = <3 0 0>; 1065 }; 1066}; 1067 1068&mailbox0_cluster1 { 1069 status = "okay"; 1070 interrupts = <432>; 1071 1072 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1073 ti,mbox-rx = <0 0 0>; 1074 ti,mbox-tx = <1 0 0>; 1075 }; 1076 1077 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1078 ti,mbox-rx = <2 0 0>; 1079 ti,mbox-tx = <3 0 0>; 1080 }; 1081}; 1082 1083&mailbox0_cluster2 { 1084 status = "okay"; 1085 interrupts = <428>; 1086 1087 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1088 ti,mbox-rx = <0 0 0>; 1089 ti,mbox-tx = <1 0 0>; 1090 }; 1091 1092 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1093 ti,mbox-rx = <2 0 0>; 1094 ti,mbox-tx = <3 0 0>; 1095 }; 1096}; 1097 1098&mailbox0_cluster3 { 1099 status = "okay"; 1100 interrupts = <424>; 1101 1102 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 1103 ti,mbox-rx = <0 0 0>; 1104 ti,mbox-tx = <1 0 0>; 1105 }; 1106 1107 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 1108 ti,mbox-rx = <2 0 0>; 1109 ti,mbox-tx = <3 0 0>; 1110 }; 1111}; 1112 1113&mailbox0_cluster4 { 1114 status = "okay"; 1115 interrupts = <420>; 1116 1117 mbox_c71_0: mbox-c71-0 { 1118 ti,mbox-rx = <0 0 0>; 1119 ti,mbox-tx = <1 0 0>; 1120 }; 1121 1122 mbox_c71_1: mbox-c71-1 { 1123 ti,mbox-rx = <2 0 0>; 1124 ti,mbox-tx = <3 0 0>; 1125 }; 1126}; 1127 1128&mailbox0_cluster5 { 1129 status = "okay"; 1130 interrupts = <416>; 1131 1132 mbox_c71_2: mbox-c71-2 { 1133 ti,mbox-rx = <0 0 0>; 1134 ti,mbox-tx = <1 0 0>; 1135 }; 1136 1137 mbox_c71_3: mbox-c71-3 { 1138 ti,mbox-rx = <2 0 0>; 1139 ti,mbox-tx = <3 0 0>; 1140 }; 1141}; 1142 1143&mcu_r5fss0_core0 { 1144 status = "okay"; 1145 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1146 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1147 <&mcu_r5fss0_core0_memory_region>; 1148}; 1149 1150&mcu_r5fss0_core1 { 1151 status = "okay"; 1152 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1153 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1154 <&mcu_r5fss0_core1_memory_region>; 1155}; 1156 1157&main_r5fss0_core0 { 1158 status = "okay"; 1159 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1160 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1161 <&main_r5fss0_core0_memory_region>; 1162}; 1163 1164&main_r5fss0_core1 { 1165 status = "okay"; 1166 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1167 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1168 <&main_r5fss0_core1_memory_region>; 1169}; 1170 1171&main_r5fss1_core0 { 1172 status = "okay"; 1173 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1174 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1175 <&main_r5fss1_core0_memory_region>; 1176}; 1177 1178&main_r5fss1_core1 { 1179 status = "okay"; 1180 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1181 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1182 <&main_r5fss1_core1_memory_region>; 1183}; 1184 1185&main_r5fss2_core0 { 1186 status = "okay"; 1187 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 1188 memory-region = <&main_r5fss2_core0_dma_memory_region>, 1189 <&main_r5fss2_core0_memory_region>; 1190}; 1191 1192&main_r5fss2_core1 { 1193 status = "okay"; 1194 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 1195 memory-region = <&main_r5fss2_core1_dma_memory_region>, 1196 <&main_r5fss2_core1_memory_region>; 1197}; 1198 1199&c71_0 { 1200 status = "okay"; 1201 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1202 memory-region = <&c71_0_dma_memory_region>, 1203 <&c71_0_memory_region>; 1204}; 1205 1206&c71_1 { 1207 status = "okay"; 1208 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 1209 memory-region = <&c71_1_dma_memory_region>, 1210 <&c71_1_memory_region>; 1211}; 1212 1213&c71_2 { 1214 status = "okay"; 1215 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 1216 memory-region = <&c71_2_dma_memory_region>, 1217 <&c71_2_memory_region>; 1218}; 1219 1220&c71_3 { 1221 status = "okay"; 1222 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 1223 memory-region = <&c71_3_dma_memory_region>, 1224 <&c71_3_memory_region>; 1225}; 1226 1227&tscadc0 { 1228 pinctrl-0 = <&mcu_adc0_pins_default>; 1229 pinctrl-names = "default"; 1230 status = "okay"; 1231 adc { 1232 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1233 }; 1234}; 1235 1236&tscadc1 { 1237 pinctrl-0 = <&mcu_adc1_pins_default>; 1238 pinctrl-names = "default"; 1239 status = "okay"; 1240 adc { 1241 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1242 }; 1243}; 1244 1245&serdes_refclk { 1246 status = "okay"; 1247 clock-frequency = <100000000>; 1248}; 1249 1250&dss { 1251 status = "okay"; 1252 assigned-clocks = <&k3_clks 218 2>, 1253 <&k3_clks 218 5>, 1254 <&k3_clks 218 14>, 1255 <&k3_clks 218 18>; 1256 assigned-clock-parents = <&k3_clks 218 3>, 1257 <&k3_clks 218 7>, 1258 <&k3_clks 218 16>, 1259 <&k3_clks 218 22>; 1260}; 1261 1262&serdes0 { 1263 status = "okay"; 1264 1265 serdes0_usb_link: phy@3 { 1266 reg = <3>; 1267 cdns,num-lanes = <1>; 1268 #phy-cells = <0>; 1269 cdns,phy-type = <PHY_TYPE_USB3>; 1270 resets = <&serdes_wiz0 4>; 1271 }; 1272}; 1273 1274&serdes_wiz0 { 1275 status = "okay"; 1276}; 1277 1278&usb_serdes_mux { 1279 idle-states = <0>; /* USB0 to SERDES lane 3 */ 1280}; 1281 1282&usbss0 { 1283 status = "okay"; 1284 pinctrl-0 = <&main_usbss0_pins_default>; 1285 pinctrl-names = "default"; 1286 ti,vbus-divider; 1287}; 1288 1289&usb0 { 1290 dr_mode = "otg"; 1291 maximum-speed = "super-speed"; 1292 phys = <&serdes0_usb_link>; 1293 phy-names = "cdns3,usb3-phy"; 1294}; 1295 1296&serdes_wiz4 { 1297 status = "okay"; 1298}; 1299 1300&serdes4 { 1301 status = "okay"; 1302 serdes4_dp_link: phy@0 { 1303 reg = <0>; 1304 cdns,num-lanes = <4>; 1305 #phy-cells = <0>; 1306 cdns,phy-type = <PHY_TYPE_DP>; 1307 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1308 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1309 }; 1310}; 1311 1312&mhdp { 1313 status = "okay"; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&dp0_pins_default>; 1316 phys = <&serdes4_dp_link>; 1317 phy-names = "dpphy"; 1318}; 1319 1320&dss_ports { 1321 /* DP */ 1322 port { 1323 dpi0_out: endpoint { 1324 remote-endpoint = <&dp0_in>; 1325 }; 1326 }; 1327}; 1328 1329&main_i2c4 { 1330 status = "okay"; 1331 pinctrl-names = "default"; 1332 pinctrl-0 = <&main_i2c4_pins_default>; 1333 clock-frequency = <400000>; 1334 1335 exp4: gpio@20 { 1336 compatible = "ti,tca6408"; 1337 reg = <0x20>; 1338 gpio-controller; 1339 #gpio-cells = <2>; 1340 }; 1341}; 1342 1343&dp0_ports { 1344 port@0 { 1345 reg = <0>; 1346 1347 dp0_in: endpoint { 1348 remote-endpoint = <&dpi0_out>; 1349 }; 1350 }; 1351 1352 port@4 { 1353 reg = <4>; 1354 1355 dp0_out: endpoint { 1356 remote-endpoint = <&dp0_connector_in>; 1357 }; 1358 }; 1359}; 1360 1361&mcu_mcan0 { 1362 status = "okay"; 1363 pinctrl-names = "default"; 1364 pinctrl-0 = <&mcu_mcan0_pins_default>; 1365 phys = <&transceiver0>; 1366}; 1367 1368&mcu_mcan1 { 1369 status = "okay"; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&mcu_mcan1_pins_default>; 1372 phys = <&transceiver1>; 1373}; 1374 1375&main_mcan16 { 1376 status = "okay"; 1377 pinctrl-names = "default"; 1378 pinctrl-0 = <&main_mcan16_pins_default>; 1379 phys = <&transceiver2>; 1380}; 1381 1382&main_mcan4 { 1383 status = "okay"; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&main_mcan4_pins_default>; 1386 phys = <&transceiver3>; 1387}; 1388 1389&serdes0 { 1390 status = "okay"; 1391 1392 serdes0_pcie1_link: phy@0 { 1393 reg = <0>; 1394 cdns,num-lanes = <4>; 1395 #phy-cells = <0>; 1396 cdns,phy-type = <PHY_TYPE_PCIE>; 1397 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, 1398 <&serdes_wiz0 3>, <&serdes_wiz0 4>; 1399 }; 1400}; 1401 1402&serdes_wiz0 { 1403 status = "okay"; 1404}; 1405 1406&pcie1_rc { 1407 status = "okay"; 1408 num-lanes = <2>; 1409 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 1410 phys = <&serdes0_pcie1_link>; 1411 phy-names = "pcie-phy"; 1412}; 1413 1414&serdes1 { 1415 status = "okay"; 1416 1417 serdes1_pcie0_link: phy@0 { 1418 reg = <0>; 1419 cdns,num-lanes = <2>; 1420 #phy-cells = <0>; 1421 cdns,phy-type = <PHY_TYPE_PCIE>; 1422 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 1423 }; 1424}; 1425 1426&serdes_wiz1 { 1427 status = "okay"; 1428}; 1429 1430&pcie0_rc { 1431 status = "okay"; 1432 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1433 phys = <&serdes1_pcie0_link>; 1434 phy-names = "pcie-phy"; 1435}; 1436 1437&k3_clks { 1438 /* Confiure AUDIO_EXT_REFCLK1 pin as output */ 1439 pinctrl-names = "default"; 1440 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 1441}; 1442 1443&main_i2c3 { 1444 status = "okay"; 1445 pinctrl-names = "default"; 1446 pinctrl-0 = <&main_i2c3_pins_default>; 1447 clock-frequency = <400000>; 1448 1449 exp3: gpio@20 { 1450 compatible = "ti,tca6408"; 1451 reg = <0x20>; 1452 gpio-controller; 1453 #gpio-cells = <2>; 1454 }; 1455 1456 pcm3168a_1: audio-codec@44 { 1457 compatible = "ti,pcm3168a"; 1458 reg = <0x44>; 1459 #sound-dai-cells = <1>; 1460 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 1461 clocks = <&audio_refclk1>; 1462 clock-names = "scki"; 1463 VDD1-supply = <&vsys_3v3>; 1464 VDD2-supply = <&vsys_3v3>; 1465 VCCAD1-supply = <&vsys_5v0>; 1466 VCCAD2-supply = <&vsys_5v0>; 1467 VCCDA1-supply = <&vsys_5v0>; 1468 VCCDA2-supply = <&vsys_5v0>; 1469 }; 1470}; 1471 1472&mcasp0 { 1473 status = "okay"; 1474 #sound-dai-cells = <0>; 1475 pinctrl-names = "default"; 1476 pinctrl-0 = <&main_mcasp0_pins_default>; 1477 op-mode = <0>; /* MCASP_IIS_MODE */ 1478 tdm-slots = <2>; 1479 auxclk-fs-ratio = <256>; 1480 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1481 0 0 0 1 1482 2 0 0 0 1483 0 0 0 0 1484 0 0 0 0 1485 >; 1486}; 1487