1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family 4 * 5 * TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52 6 * 7 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/k3.h> 14#include <dt-bindings/soc/ti,sci_pm_domain.h> 15 16/ { 17 model = "Texas Instruments K3 J784S4 SoC"; 18 compatible = "ti,j784s4"; 19 interrupt-parent = <&gic500>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 cpu-map { 27 cluster0: cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 45 cluster1: cluster1 { 46 core0 { 47 cpu = <&cpu4>; 48 }; 49 50 core1 { 51 cpu = <&cpu5>; 52 }; 53 54 core2 { 55 cpu = <&cpu6>; 56 }; 57 58 core3 { 59 cpu = <&cpu7>; 60 }; 61 }; 62 }; 63 64 cpu0: cpu@0 { 65 compatible = "arm,cortex-a72"; 66 reg = <0x000>; 67 device_type = "cpu"; 68 enable-method = "psci"; 69 i-cache-size = <0xc000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; 72 d-cache-size = <0x8000>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <256>; 75 next-level-cache = <&L2_0>; 76 }; 77 78 cpu1: cpu@1 { 79 compatible = "arm,cortex-a72"; 80 reg = <0x001>; 81 device_type = "cpu"; 82 enable-method = "psci"; 83 i-cache-size = <0xc000>; 84 i-cache-line-size = <64>; 85 i-cache-sets = <256>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <256>; 89 next-level-cache = <&L2_0>; 90 }; 91 92 cpu2: cpu@2 { 93 compatible = "arm,cortex-a72"; 94 reg = <0x002>; 95 device_type = "cpu"; 96 enable-method = "psci"; 97 i-cache-size = <0xc000>; 98 i-cache-line-size = <64>; 99 i-cache-sets = <256>; 100 d-cache-size = <0x8000>; 101 d-cache-line-size = <64>; 102 d-cache-sets = <256>; 103 next-level-cache = <&L2_0>; 104 }; 105 106 cpu3: cpu@3 { 107 compatible = "arm,cortex-a72"; 108 reg = <0x003>; 109 device_type = "cpu"; 110 enable-method = "psci"; 111 i-cache-size = <0xc000>; 112 i-cache-line-size = <64>; 113 i-cache-sets = <256>; 114 d-cache-size = <0x8000>; 115 d-cache-line-size = <64>; 116 d-cache-sets = <256>; 117 next-level-cache = <&L2_0>; 118 }; 119 120 cpu4: cpu@100 { 121 compatible = "arm,cortex-a72"; 122 reg = <0x100>; 123 device_type = "cpu"; 124 enable-method = "psci"; 125 i-cache-size = <0xc000>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <256>; 128 d-cache-size = <0x8000>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <256>; 131 next-level-cache = <&L2_1>; 132 }; 133 134 cpu5: cpu@101 { 135 compatible = "arm,cortex-a72"; 136 reg = <0x101>; 137 device_type = "cpu"; 138 enable-method = "psci"; 139 i-cache-size = <0xc000>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <256>; 142 d-cache-size = <0x8000>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <256>; 145 next-level-cache = <&L2_1>; 146 }; 147 148 cpu6: cpu@102 { 149 compatible = "arm,cortex-a72"; 150 reg = <0x102>; 151 device_type = "cpu"; 152 enable-method = "psci"; 153 i-cache-size = <0xc000>; 154 i-cache-line-size = <64>; 155 i-cache-sets = <256>; 156 d-cache-size = <0x8000>; 157 d-cache-line-size = <64>; 158 d-cache-sets = <256>; 159 next-level-cache = <&L2_1>; 160 }; 161 162 cpu7: cpu@103 { 163 compatible = "arm,cortex-a72"; 164 reg = <0x103>; 165 device_type = "cpu"; 166 enable-method = "psci"; 167 i-cache-size = <0xc000>; 168 i-cache-line-size = <64>; 169 i-cache-sets = <256>; 170 d-cache-size = <0x8000>; 171 d-cache-line-size = <64>; 172 d-cache-sets = <256>; 173 next-level-cache = <&L2_1>; 174 }; 175 }; 176 177 L2_0: l2-cache0 { 178 compatible = "cache"; 179 cache-level = <2>; 180 cache-unified; 181 cache-size = <0x200000>; 182 cache-line-size = <64>; 183 cache-sets = <1024>; 184 next-level-cache = <&msmc_l3>; 185 }; 186 187 L2_1: l2-cache1 { 188 compatible = "cache"; 189 cache-level = <2>; 190 cache-unified; 191 cache-size = <0x200000>; 192 cache-line-size = <64>; 193 cache-sets = <1024>; 194 next-level-cache = <&msmc_l3>; 195 }; 196 197 msmc_l3: l3-cache0 { 198 compatible = "cache"; 199 cache-level = <3>; 200 cache-unified; 201 }; 202 203 firmware { 204 optee { 205 compatible = "linaro,optee-tz"; 206 method = "smc"; 207 }; 208 209 psci: psci { 210 compatible = "arm,psci-1.0"; 211 method = "smc"; 212 }; 213 }; 214 215 a72_timer0: timer-cl0-cpu0 { 216 compatible = "arm,armv8-timer"; 217 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 218 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 219 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 220 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 221 }; 222 223 pmu: pmu { 224 compatible = "arm,cortex-a72-pmu"; 225 /* Recommendation from GIC500 TRM Table A.3 */ 226 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 cbass_main: bus@100000 { 230 compatible = "simple-bus"; 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 234 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 235 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ 236 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ 237 <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ 238 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ 239 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ 240 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ 241 <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */ 242 <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */ 243 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 244 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ 245 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 246 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ 247 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 248 249 /* MCUSS_WKUP Range */ 250 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 251 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 252 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 253 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 254 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 255 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 256 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 257 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 258 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 259 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 260 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 261 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 262 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 263 264 cbass_mcu_wakeup: bus@28380000 { 265 compatible = "simple-bus"; 266 #address-cells = <2>; 267 #size-cells = <2>; 268 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 269 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 270 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 271 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 272 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 273 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 274 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 275 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 276 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 277 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 278 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 279 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 280 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 281 }; 282 }; 283}; 284 285/* Now include peripherals from each bus segment */ 286#include "k3-j784s4-main.dtsi" 287#include "k3-j784s4-mcu-wakeup.dtsi" 288