1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/phy/phy.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17
18/ {
19	model = "ZynqMP zc1751-xm015-dc1 RevA";
20	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		i2c0 = &i2c1;
25		mmc0 = &sdhci0;
26		mmc1 = &sdhci1;
27		rtc0 = &rtc;
28		serial0 = &uart0;
29		spi0 = &qspi;
30		usb0 = &usb0;
31	};
32
33	chosen {
34		bootargs = "earlycon";
35		stdout-path = "serial0:115200n8";
36	};
37
38	memory@0 {
39		device_type = "memory";
40		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
41	};
42
43	clock_si5338_0: clk27 {	/* u55 SI5338-GM */
44		compatible = "fixed-clock";
45		#clock-cells = <0>;
46		clock-frequency = <27000000>;
47	};
48
49	clock_si5338_2: clk26 {
50		compatible = "fixed-clock";
51		#clock-cells = <0>;
52		clock-frequency = <26000000>;
53	};
54
55	clock_si5338_3: clk150 {
56		compatible = "fixed-clock";
57		#clock-cells = <0>;
58		clock-frequency = <150000000>;
59	};
60};
61
62&fpd_dma_chan1 {
63	status = "okay";
64};
65
66&fpd_dma_chan2 {
67	status = "okay";
68};
69
70&fpd_dma_chan3 {
71	status = "okay";
72};
73
74&fpd_dma_chan4 {
75	status = "okay";
76};
77
78&fpd_dma_chan5 {
79	status = "okay";
80};
81
82&fpd_dma_chan6 {
83	status = "okay";
84};
85
86&fpd_dma_chan7 {
87	status = "okay";
88};
89
90&fpd_dma_chan8 {
91	status = "okay";
92};
93
94&gem3 {
95	status = "okay";
96	phy-handle = <&phy0>;
97	phy-mode = "rgmii-id";
98	pinctrl-names = "default";
99	pinctrl-0 = <&pinctrl_gem3_default>;
100	phy0: ethernet-phy@0 {
101		reg = <0>;
102	};
103};
104
105&gpio {
106	status = "okay";
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_gpio_default>;
109};
110
111
112&i2c1 {
113	status = "okay";
114	clock-frequency = <400000>;
115	pinctrl-names = "default", "gpio";
116	pinctrl-0 = <&pinctrl_i2c1_default>;
117	pinctrl-1 = <&pinctrl_i2c1_gpio>;
118	scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
119	sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
120
121	eeprom: eeprom@55 {
122		compatible = "atmel,24c64"; /* 24AA64 */
123		reg = <0x55>;
124	};
125};
126
127&pinctrl0 {
128	status = "okay";
129	pinctrl_i2c1_default: i2c1-default {
130		mux {
131			groups = "i2c1_9_grp";
132			function = "i2c1";
133		};
134
135		conf {
136			groups = "i2c1_9_grp";
137			bias-pull-up;
138			slew-rate = <SLEW_RATE_SLOW>;
139			power-source = <IO_STANDARD_LVCMOS18>;
140		};
141	};
142
143	pinctrl_i2c1_gpio: i2c1-gpio {
144		mux {
145			groups = "gpio0_36_grp", "gpio0_37_grp";
146			function = "gpio0";
147		};
148
149		conf {
150			groups = "gpio0_36_grp", "gpio0_37_grp";
151			slew-rate = <SLEW_RATE_SLOW>;
152			power-source = <IO_STANDARD_LVCMOS18>;
153		};
154	};
155
156	pinctrl_uart0_default: uart0-default {
157		mux {
158			groups = "uart0_8_grp";
159			function = "uart0";
160		};
161
162		conf {
163			groups = "uart0_8_grp";
164			slew-rate = <SLEW_RATE_SLOW>;
165			power-source = <IO_STANDARD_LVCMOS18>;
166		};
167
168		conf-rx {
169			pins = "MIO34";
170			bias-high-impedance;
171		};
172
173		conf-tx {
174			pins = "MIO35";
175			bias-disable;
176		};
177	};
178
179	pinctrl_usb0_default: usb0-default {
180		mux {
181			groups = "usb0_0_grp";
182			function = "usb0";
183		};
184
185		conf {
186			groups = "usb0_0_grp";
187			slew-rate = <SLEW_RATE_SLOW>;
188			power-source = <IO_STANDARD_LVCMOS18>;
189		};
190
191		conf-rx {
192			pins = "MIO52", "MIO53", "MIO55";
193			bias-high-impedance;
194		};
195
196		conf-tx {
197			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
198			       "MIO60", "MIO61", "MIO62", "MIO63";
199			bias-disable;
200		};
201	};
202
203	pinctrl_gem3_default: gem3-default {
204		mux {
205			function = "ethernet3";
206			groups = "ethernet3_0_grp";
207		};
208
209		conf {
210			groups = "ethernet3_0_grp";
211			slew-rate = <SLEW_RATE_SLOW>;
212			power-source = <IO_STANDARD_LVCMOS18>;
213		};
214
215		conf-rx {
216			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
217									"MIO75";
218			bias-high-impedance;
219			low-power-disable;
220		};
221
222		conf-tx {
223			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
224									"MIO69";
225			bias-disable;
226			low-power-enable;
227		};
228
229		mux-mdio {
230			function = "mdio3";
231			groups = "mdio3_0_grp";
232		};
233
234		conf-mdio {
235			groups = "mdio3_0_grp";
236			slew-rate = <SLEW_RATE_SLOW>;
237			power-source = <IO_STANDARD_LVCMOS18>;
238			bias-disable;
239		};
240	};
241
242	pinctrl_sdhci0_default: sdhci0-default {
243		mux {
244			groups = "sdio0_0_grp";
245			function = "sdio0";
246		};
247
248		conf {
249			groups = "sdio0_0_grp";
250			slew-rate = <SLEW_RATE_SLOW>;
251			power-source = <IO_STANDARD_LVCMOS18>;
252			bias-disable;
253		};
254
255		mux-cd {
256			groups = "sdio0_cd_0_grp";
257			function = "sdio0_cd";
258		};
259
260		conf-cd {
261			groups = "sdio0_cd_0_grp";
262			bias-high-impedance;
263			bias-pull-up;
264			slew-rate = <SLEW_RATE_SLOW>;
265			power-source = <IO_STANDARD_LVCMOS18>;
266		};
267
268		mux-wp {
269			groups = "sdio0_wp_0_grp";
270			function = "sdio0_wp";
271		};
272
273		conf-wp {
274			groups = "sdio0_wp_0_grp";
275			bias-high-impedance;
276			bias-pull-up;
277			slew-rate = <SLEW_RATE_SLOW>;
278			power-source = <IO_STANDARD_LVCMOS18>;
279		};
280	};
281
282	pinctrl_sdhci1_default: sdhci1-default {
283		mux {
284			groups = "sdio1_0_grp";
285			function = "sdio1";
286		};
287
288		conf {
289			groups = "sdio1_0_grp";
290			slew-rate = <SLEW_RATE_SLOW>;
291			power-source = <IO_STANDARD_LVCMOS18>;
292			bias-disable;
293		};
294
295		mux-cd {
296			groups = "sdio1_cd_0_grp";
297			function = "sdio1_cd";
298		};
299
300		conf-cd {
301			groups = "sdio1_cd_0_grp";
302			bias-high-impedance;
303			bias-pull-up;
304			slew-rate = <SLEW_RATE_SLOW>;
305			power-source = <IO_STANDARD_LVCMOS18>;
306		};
307
308		mux-wp {
309			groups = "sdio1_wp_0_grp";
310			function = "sdio1_wp";
311		};
312
313		conf-wp {
314			groups = "sdio1_wp_0_grp";
315			bias-high-impedance;
316			bias-pull-up;
317			slew-rate = <SLEW_RATE_SLOW>;
318			power-source = <IO_STANDARD_LVCMOS18>;
319		};
320	};
321
322	pinctrl_gpio_default: gpio-default {
323		mux {
324			function = "gpio0";
325			groups = "gpio0_38_grp";
326		};
327
328		conf {
329			groups = "gpio0_38_grp";
330			bias-disable;
331			slew-rate = <SLEW_RATE_SLOW>;
332			power-source = <IO_STANDARD_LVCMOS18>;
333		};
334	};
335};
336
337&psgtr {
338	status = "okay";
339	/* dp, usb3, sata */
340	clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
341	clock-names = "ref1", "ref2", "ref3";
342};
343
344&qspi {
345	status = "okay";
346	flash@0 {
347		compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
348		#address-cells = <1>;
349		#size-cells = <1>;
350		reg = <0x0>;
351		spi-tx-bus-width = <1>;
352		spi-rx-bus-width = <4>;
353		spi-max-frequency = <108000000>; /* Based on DC1 spec */
354	};
355};
356
357&rtc {
358	status = "okay";
359};
360
361&sata {
362	status = "okay";
363	/* SATA phy OOB timing settings */
364	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
365	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
366	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
367	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
368	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
369	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
370	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
371	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
372	phy-names = "sata-phy";
373	phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
374};
375
376/* eMMC */
377&sdhci0 {
378	status = "okay";
379	pinctrl-names = "default";
380	pinctrl-0 = <&pinctrl_sdhci0_default>;
381	bus-width = <8>;
382	xlnx,mio-bank = <0>;
383};
384
385/* SD1 with level shifter */
386&sdhci1 {
387	status = "okay";
388	/*
389	 * This property should be removed for supporting UHS mode
390	 */
391	no-1-8-v;
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_sdhci1_default>;
394	xlnx,mio-bank = <1>;
395};
396
397&uart0 {
398	status = "okay";
399	pinctrl-names = "default";
400	pinctrl-0 = <&pinctrl_uart0_default>;
401};
402
403/* ULPI SMSC USB3320 */
404&usb0 {
405	status = "okay";
406	pinctrl-names = "default";
407	pinctrl-0 = <&pinctrl_usb0_default>;
408	phy-names = "usb3-phy";
409	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
410};
411
412&dwc3_0 {
413	status = "okay";
414	dr_mode = "host";
415	snps,usb3_lpm_capable;
416	maximum-speed = "super-speed";
417};
418
419&zynqmp_dpdma {
420	status = "okay";
421};
422
423&zynqmp_dpsub {
424	status = "okay";
425	phy-names = "dp-phy0", "dp-phy1";
426	phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
427	       <&psgtr 0 PHY_TYPE_DP 1 1>;
428};
429