1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU102 RevA
4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20	model = "ZynqMP ZCU102 RevA";
21	compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		mmc0 = &sdhci1;
28		nvmem0 = &eeprom;
29		rtc0 = &rtc;
30		serial0 = &uart0;
31		serial1 = &uart1;
32		serial2 = &dcc;
33		spi0 = &qspi;
34		usb0 = &usb0;
35	};
36
37	chosen {
38		bootargs = "earlycon";
39		stdout-path = "serial0:115200n8";
40	};
41
42	memory@0 {
43		device_type = "memory";
44		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
45	};
46
47	gpio-keys {
48		compatible = "gpio-keys";
49		autorepeat;
50		switch-19 {
51			label = "sw19";
52			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53			linux,code = <KEY_DOWN>;
54			wakeup-source;
55			autorepeat;
56		};
57	};
58
59	leds {
60		compatible = "gpio-leds";
61		heartbeat-led {
62			label = "heartbeat";
63			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64			linux,default-trigger = "heartbeat";
65		};
66	};
67
68	ina226-u76 {
69		compatible = "iio-hwmon";
70		io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
71	};
72	ina226-u77 {
73		compatible = "iio-hwmon";
74		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
75	};
76	ina226-u78 {
77		compatible = "iio-hwmon";
78		io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
79	};
80	ina226-u87 {
81		compatible = "iio-hwmon";
82		io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
83	};
84	ina226-u85 {
85		compatible = "iio-hwmon";
86		io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
87	};
88	ina226-u86 {
89		compatible = "iio-hwmon";
90		io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
91	};
92	ina226-u93 {
93		compatible = "iio-hwmon";
94		io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
95	};
96	ina226-u88 {
97		compatible = "iio-hwmon";
98		io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
99	};
100	ina226-u15 {
101		compatible = "iio-hwmon";
102		io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
103	};
104	ina226-u92 {
105		compatible = "iio-hwmon";
106		io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
107	};
108	ina226-u79 {
109		compatible = "iio-hwmon";
110		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
111	};
112	ina226-u81 {
113		compatible = "iio-hwmon";
114		io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
115	};
116	ina226-u80 {
117		compatible = "iio-hwmon";
118		io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
119	};
120	ina226-u84 {
121		compatible = "iio-hwmon";
122		io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
123	};
124	ina226-u16 {
125		compatible = "iio-hwmon";
126		io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
127	};
128	ina226-u65 {
129		compatible = "iio-hwmon";
130		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
131	};
132	ina226-u74 {
133		compatible = "iio-hwmon";
134		io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
135	};
136	ina226-u75 {
137		compatible = "iio-hwmon";
138		io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
139	};
140
141	/* 48MHz reference crystal */
142	ref48: ref48M {
143		compatible = "fixed-clock";
144		#clock-cells = <0>;
145		clock-frequency = <48000000>;
146	};
147
148	refhdmi: refhdmi {
149		compatible = "fixed-clock";
150		#clock-cells = <0>;
151		clock-frequency = <114285000>;
152	};
153};
154
155&can1 {
156	status = "okay";
157	pinctrl-names = "default";
158	pinctrl-0 = <&pinctrl_can1_default>;
159};
160
161&dcc {
162	status = "okay";
163};
164
165&fpd_dma_chan1 {
166	status = "okay";
167};
168
169&fpd_dma_chan2 {
170	status = "okay";
171};
172
173&fpd_dma_chan3 {
174	status = "okay";
175};
176
177&fpd_dma_chan4 {
178	status = "okay";
179};
180
181&fpd_dma_chan5 {
182	status = "okay";
183};
184
185&fpd_dma_chan6 {
186	status = "okay";
187};
188
189&fpd_dma_chan7 {
190	status = "okay";
191};
192
193&fpd_dma_chan8 {
194	status = "okay";
195};
196
197&gem3 {
198	status = "okay";
199	phy-handle = <&phy0>;
200	phy-mode = "rgmii-id";
201	pinctrl-names = "default";
202	pinctrl-0 = <&pinctrl_gem3_default>;
203	phy0: ethernet-phy@21 {
204		reg = <21>;
205		ti,rx-internal-delay = <0x8>;
206		ti,tx-internal-delay = <0xa>;
207		ti,fifo-depth = <0x1>;
208		ti,dp83867-rxctrl-strap-quirk;
209		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
210	};
211};
212
213&gpio {
214	status = "okay";
215	pinctrl-names = "default";
216	pinctrl-0 = <&pinctrl_gpio_default>;
217};
218
219&i2c0 {
220	status = "okay";
221	clock-frequency = <400000>;
222	pinctrl-names = "default", "gpio";
223	pinctrl-0 = <&pinctrl_i2c0_default>;
224	pinctrl-1 = <&pinctrl_i2c0_gpio>;
225	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
226	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
227
228	tca6416_u97: gpio@20 {
229		compatible = "ti,tca6416";
230		reg = <0x20>;
231		gpio-controller; /* IRQ not connected */
232		#gpio-cells = <2>;
233		gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
234				"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
235				"", "", "", "", "", "", "", "", "";
236		gtr-sel0-hog {
237			gpio-hog;
238			gpios = <0 0>;
239			output-low; /* PCIE = 0, DP = 1 */
240			line-name = "sel0";
241		};
242		gtr-sel1-hog {
243			gpio-hog;
244			gpios = <1 0>;
245			output-high; /* PCIE = 0, DP = 1 */
246			line-name = "sel1";
247		};
248		gtr-sel2-hog {
249			gpio-hog;
250			gpios = <2 0>;
251			output-high; /* PCIE = 0, USB0 = 1 */
252			line-name = "sel2";
253		};
254		gtr-sel3-hog {
255			gpio-hog;
256			gpios = <3 0>;
257			output-high; /* PCIE = 0, SATA = 1 */
258			line-name = "sel3";
259		};
260	};
261
262	tca6416_u61: gpio@21 {
263		compatible = "ti,tca6416";
264		reg = <0x21>;
265		gpio-controller; /* IRQ not connected */
266		#gpio-cells = <2>;
267		gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
268				"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
269				"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
270				"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
271	};
272
273	i2c-mux@75 { /* u60 */
274		compatible = "nxp,pca9544";
275		#address-cells = <1>;
276		#size-cells = <0>;
277		reg = <0x75>;
278		i2c@0 {
279			#address-cells = <1>;
280			#size-cells = <0>;
281			reg = <0>;
282			/* PS_PMBUS */
283			u76: ina226@40 { /* u76 */
284				compatible = "ti,ina226";
285				#io-channel-cells = <1>;
286				label = "ina226-u76";
287				reg = <0x40>;
288				shunt-resistor = <5000>;
289			};
290			u77: ina226@41 { /* u77 */
291				compatible = "ti,ina226";
292				#io-channel-cells = <1>;
293				label = "ina226-u77";
294				reg = <0x41>;
295				shunt-resistor = <5000>;
296			};
297			u78: ina226@42 { /* u78 */
298				compatible = "ti,ina226";
299				#io-channel-cells = <1>;
300				label = "ina226-u78";
301				reg = <0x42>;
302				shunt-resistor = <5000>;
303			};
304			u87: ina226@43 { /* u87 */
305				compatible = "ti,ina226";
306				#io-channel-cells = <1>;
307				label = "ina226-u87";
308				reg = <0x43>;
309				shunt-resistor = <5000>;
310			};
311			u85: ina226@44 { /* u85 */
312				compatible = "ti,ina226";
313				#io-channel-cells = <1>;
314				label = "ina226-u85";
315				reg = <0x44>;
316				shunt-resistor = <5000>;
317			};
318			u86: ina226@45 { /* u86 */
319				compatible = "ti,ina226";
320				#io-channel-cells = <1>;
321				label = "ina226-u86";
322				reg = <0x45>;
323				shunt-resistor = <5000>;
324			};
325			u93: ina226@46 { /* u93 */
326				compatible = "ti,ina226";
327				#io-channel-cells = <1>;
328				label = "ina226-u93";
329				reg = <0x46>;
330				shunt-resistor = <5000>;
331			};
332			u88: ina226@47 { /* u88 */
333				compatible = "ti,ina226";
334				#io-channel-cells = <1>;
335				label = "ina226-u88";
336				reg = <0x47>;
337				shunt-resistor = <5000>;
338			};
339			u15: ina226@4a { /* u15 */
340				compatible = "ti,ina226";
341				#io-channel-cells = <1>;
342				label = "ina226-u15";
343				reg = <0x4a>;
344				shunt-resistor = <5000>;
345			};
346			u92: ina226@4b { /* u92 */
347				compatible = "ti,ina226";
348				#io-channel-cells = <1>;
349				label = "ina226-u92";
350				reg = <0x4b>;
351				shunt-resistor = <5000>;
352			};
353		};
354		i2c@1 {
355			#address-cells = <1>;
356			#size-cells = <0>;
357			reg = <1>;
358			/* PL_PMBUS */
359			u79: ina226@40 { /* u79 */
360				compatible = "ti,ina226";
361				#io-channel-cells = <1>;
362				label = "ina226-u79";
363				reg = <0x40>;
364				shunt-resistor = <2000>;
365			};
366			u81: ina226@41 { /* u81 */
367				compatible = "ti,ina226";
368				#io-channel-cells = <1>;
369				label = "ina226-u81";
370				reg = <0x41>;
371				shunt-resistor = <5000>;
372			};
373			u80: ina226@42 { /* u80 */
374				compatible = "ti,ina226";
375				#io-channel-cells = <1>;
376				label = "ina226-u80";
377				reg = <0x42>;
378				shunt-resistor = <5000>;
379			};
380			u84: ina226@43 { /* u84 */
381				compatible = "ti,ina226";
382				#io-channel-cells = <1>;
383				label = "ina226-u84";
384				reg = <0x43>;
385				shunt-resistor = <5000>;
386			};
387			u16: ina226@44 { /* u16 */
388				compatible = "ti,ina226";
389				#io-channel-cells = <1>;
390				label = "ina226-u16";
391				reg = <0x44>;
392				shunt-resistor = <5000>;
393			};
394			u65: ina226@45 { /* u65 */
395				compatible = "ti,ina226";
396				#io-channel-cells = <1>;
397				label = "ina226-u65";
398				reg = <0x45>;
399				shunt-resistor = <5000>;
400			};
401			u74: ina226@46 { /* u74 */
402				compatible = "ti,ina226";
403				#io-channel-cells = <1>;
404				label = "ina226-u74";
405				reg = <0x46>;
406				shunt-resistor = <5000>;
407			};
408			u75: ina226@47 { /* u75 */
409				compatible = "ti,ina226";
410				#io-channel-cells = <1>;
411				label = "ina226-u75";
412				reg = <0x47>;
413				shunt-resistor = <5000>;
414			};
415		};
416		i2c@2 {
417			#address-cells = <1>;
418			#size-cells = <0>;
419			reg = <2>;
420			/* MAXIM_PMBUS - 00 */
421			max15301@a { /* u46 */
422				compatible = "maxim,max15301";
423				reg = <0xa>;
424			};
425			max15303@b { /* u4 */
426				compatible = "maxim,max15303";
427				reg = <0xb>;
428			};
429			max15303@10 { /* u13 */
430				compatible = "maxim,max15303";
431				reg = <0x10>;
432			};
433			max15301@13 { /* u47 */
434				compatible = "maxim,max15301";
435				reg = <0x13>;
436			};
437			max15303@14 { /* u7 */
438				compatible = "maxim,max15303";
439				reg = <0x14>;
440			};
441			max15303@15 { /* u6 */
442				compatible = "maxim,max15303";
443				reg = <0x15>;
444			};
445			max15303@16 { /* u10 */
446				compatible = "maxim,max15303";
447				reg = <0x16>;
448			};
449			max15303@17 { /* u9 */
450				compatible = "maxim,max15303";
451				reg = <0x17>;
452			};
453			max15301@18 { /* u63 */
454				compatible = "maxim,max15301";
455				reg = <0x18>;
456			};
457			max15303@1a { /* u49 */
458				compatible = "maxim,max15303";
459				reg = <0x1a>;
460			};
461			max15303@1d { /* u18 */
462				compatible = "maxim,max15303";
463				reg = <0x1d>;
464			};
465			max15303@20 { /* u8 */
466				compatible = "maxim,max15303";
467				status = "disabled"; /* unreachable */
468				reg = <0x20>;
469			};
470			max20751@72 { /* u95 */
471				compatible = "maxim,max20751";
472				reg = <0x72>;
473			};
474			max20751@73 { /* u96 */
475				compatible = "maxim,max20751";
476				reg = <0x73>;
477			};
478		};
479		/* Bus 3 is not connected */
480	};
481};
482
483&i2c1 {
484	status = "okay";
485	clock-frequency = <400000>;
486	pinctrl-names = "default", "gpio";
487	pinctrl-0 = <&pinctrl_i2c1_default>;
488	pinctrl-1 = <&pinctrl_i2c1_gpio>;
489	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
490	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
491
492	/* PL i2c via PCA9306 - u45 */
493	i2c-mux@74 { /* u34 */
494		compatible = "nxp,pca9548";
495		#address-cells = <1>;
496		#size-cells = <0>;
497		reg = <0x74>;
498		i2c@0 {
499			#address-cells = <1>;
500			#size-cells = <0>;
501			reg = <0>;
502			/*
503			 * IIC_EEPROM 1kB memory which uses 256B blocks
504			 * where every block has different address.
505			 *    0 - 256B address 0x54
506			 * 256B - 512B address 0x55
507			 * 512B - 768B address 0x56
508			 * 768B - 1024B address 0x57
509			 */
510			eeprom: eeprom@54 { /* u23 */
511				compatible = "atmel,24c08";
512				reg = <0x54>;
513			};
514		};
515		i2c@1 {
516			#address-cells = <1>;
517			#size-cells = <0>;
518			reg = <1>;
519			si5341: clock-generator@36 { /* SI5341 - u69 */
520				compatible = "silabs,si5341";
521				reg = <0x36>;
522				#clock-cells = <2>;
523				#address-cells = <1>;
524				#size-cells = <0>;
525				clocks = <&ref48>;
526				clock-names = "xtal";
527				clock-output-names = "si5341";
528
529				si5341_0: out@0 {
530					/* refclk0 for PS-GT, used for DP */
531					reg = <0>;
532					always-on;
533				};
534				si5341_2: out@2 {
535					/* refclk2 for PS-GT, used for USB3 */
536					reg = <2>;
537					always-on;
538				};
539				si5341_3: out@3 {
540					/* refclk3 for PS-GT, used for SATA */
541					reg = <3>;
542					always-on;
543				};
544				si5341_4: out@4 {
545					/* refclk4 for PS-GT, used for PCIE slot */
546					reg = <4>;
547					always-on;
548				};
549				si5341_5: out@5 {
550					/* refclk5 for PS-GT, used for PCIE */
551					reg = <5>;
552					always-on;
553				};
554				si5341_6: out@6 {
555					/* refclk6 PL CLK125 */
556					reg = <6>;
557					always-on;
558				};
559				si5341_7: out@7 {
560					/* refclk7 PL CLK74 */
561					reg = <7>;
562					always-on;
563				};
564				si5341_9: out@9 {
565					/* refclk9 used for PS_REF_CLK 33.3 MHz */
566					reg = <9>;
567					always-on;
568				};
569			};
570		};
571		i2c@2 {
572			#address-cells = <1>;
573			#size-cells = <0>;
574			reg = <2>;
575			si570_1: clock-generator@5d { /* USER SI570 - u42 */
576				#clock-cells = <0>;
577				compatible = "silabs,si570";
578				reg = <0x5d>;
579				temperature-stability = <50>;
580				factory-fout = <300000000>;
581				clock-frequency = <300000000>;
582				clock-output-names = "si570_user";
583			};
584		};
585		i2c@3 {
586			#address-cells = <1>;
587			#size-cells = <0>;
588			reg = <3>;
589			si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
590				#clock-cells = <0>;
591				compatible = "silabs,si570";
592				reg = <0x5d>;
593				temperature-stability = <50>; /* copy from zc702 */
594				factory-fout = <156250000>;
595				clock-frequency = <148500000>;
596				clock-output-names = "si570_mgt";
597			};
598		};
599		i2c@4 {
600			#address-cells = <1>;
601			#size-cells = <0>;
602			reg = <4>;
603			/* SI5328 - u20 */
604		};
605		/* 5 - 7 unconnected */
606	};
607
608	i2c-mux@75 {
609		compatible = "nxp,pca9548"; /* u135 */
610		#address-cells = <1>;
611		#size-cells = <0>;
612		reg = <0x75>;
613
614		i2c@0 {
615			#address-cells = <1>;
616			#size-cells = <0>;
617			reg = <0>;
618			/* HPC0_IIC */
619		};
620		i2c@1 {
621			#address-cells = <1>;
622			#size-cells = <0>;
623			reg = <1>;
624			/* HPC1_IIC */
625		};
626		i2c@2 {
627			#address-cells = <1>;
628			#size-cells = <0>;
629			reg = <2>;
630			/* SYSMON */
631		};
632		i2c@3 {
633			#address-cells = <1>;
634			#size-cells = <0>;
635			reg = <3>;
636			/* DDR4 SODIMM */
637		};
638		i2c@4 {
639			#address-cells = <1>;
640			#size-cells = <0>;
641			reg = <4>;
642			/* SEP 3 */
643		};
644		i2c@5 {
645			#address-cells = <1>;
646			#size-cells = <0>;
647			reg = <5>;
648			/* SEP 2 */
649		};
650		i2c@6 {
651			#address-cells = <1>;
652			#size-cells = <0>;
653			reg = <6>;
654			/* SEP 1 */
655		};
656		i2c@7 {
657			#address-cells = <1>;
658			#size-cells = <0>;
659			reg = <7>;
660			/* SEP 0 */
661		};
662	};
663};
664
665&pinctrl0 {
666	status = "okay";
667	pinctrl_i2c0_default: i2c0-default {
668		mux {
669			groups = "i2c0_3_grp";
670			function = "i2c0";
671		};
672
673		conf {
674			groups = "i2c0_3_grp";
675			bias-pull-up;
676			slew-rate = <SLEW_RATE_SLOW>;
677			power-source = <IO_STANDARD_LVCMOS18>;
678		};
679	};
680
681	pinctrl_i2c0_gpio: i2c0-gpio {
682		mux {
683			groups = "gpio0_14_grp", "gpio0_15_grp";
684			function = "gpio0";
685		};
686
687		conf {
688			groups = "gpio0_14_grp", "gpio0_15_grp";
689			slew-rate = <SLEW_RATE_SLOW>;
690			power-source = <IO_STANDARD_LVCMOS18>;
691		};
692	};
693
694	pinctrl_i2c1_default: i2c1-default {
695		mux {
696			groups = "i2c1_4_grp";
697			function = "i2c1";
698		};
699
700		conf {
701			groups = "i2c1_4_grp";
702			bias-pull-up;
703			slew-rate = <SLEW_RATE_SLOW>;
704			power-source = <IO_STANDARD_LVCMOS18>;
705		};
706	};
707
708	pinctrl_i2c1_gpio: i2c1-gpio {
709		mux {
710			groups = "gpio0_16_grp", "gpio0_17_grp";
711			function = "gpio0";
712		};
713
714		conf {
715			groups = "gpio0_16_grp", "gpio0_17_grp";
716			slew-rate = <SLEW_RATE_SLOW>;
717			power-source = <IO_STANDARD_LVCMOS18>;
718		};
719	};
720
721	pinctrl_uart0_default: uart0-default {
722		mux {
723			groups = "uart0_4_grp";
724			function = "uart0";
725		};
726
727		conf {
728			groups = "uart0_4_grp";
729			slew-rate = <SLEW_RATE_SLOW>;
730			power-source = <IO_STANDARD_LVCMOS18>;
731		};
732
733		conf-rx {
734			pins = "MIO18";
735			bias-high-impedance;
736		};
737
738		conf-tx {
739			pins = "MIO19";
740			bias-disable;
741		};
742	};
743
744	pinctrl_uart1_default: uart1-default {
745		mux {
746			groups = "uart1_5_grp";
747			function = "uart1";
748		};
749
750		conf {
751			groups = "uart1_5_grp";
752			slew-rate = <SLEW_RATE_SLOW>;
753			power-source = <IO_STANDARD_LVCMOS18>;
754		};
755
756		conf-rx {
757			pins = "MIO21";
758			bias-high-impedance;
759		};
760
761		conf-tx {
762			pins = "MIO20";
763			bias-disable;
764		};
765	};
766
767	pinctrl_usb0_default: usb0-default {
768		mux {
769			groups = "usb0_0_grp";
770			function = "usb0";
771		};
772
773		conf {
774			groups = "usb0_0_grp";
775			slew-rate = <SLEW_RATE_SLOW>;
776			power-source = <IO_STANDARD_LVCMOS18>;
777		};
778
779		conf-rx {
780			pins = "MIO52", "MIO53", "MIO55";
781			bias-high-impedance;
782		};
783
784		conf-tx {
785			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
786			       "MIO60", "MIO61", "MIO62", "MIO63";
787			bias-disable;
788		};
789	};
790
791	pinctrl_gem3_default: gem3-default {
792		mux {
793			function = "ethernet3";
794			groups = "ethernet3_0_grp";
795		};
796
797		conf {
798			groups = "ethernet3_0_grp";
799			slew-rate = <SLEW_RATE_SLOW>;
800			power-source = <IO_STANDARD_LVCMOS18>;
801		};
802
803		conf-rx {
804			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
805									"MIO75";
806			bias-high-impedance;
807			low-power-disable;
808		};
809
810		conf-tx {
811			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
812									"MIO69";
813			bias-disable;
814			low-power-enable;
815		};
816
817		mux-mdio {
818			function = "mdio3";
819			groups = "mdio3_0_grp";
820		};
821
822		conf-mdio {
823			groups = "mdio3_0_grp";
824			slew-rate = <SLEW_RATE_SLOW>;
825			power-source = <IO_STANDARD_LVCMOS18>;
826			bias-disable;
827		};
828	};
829
830	pinctrl_can1_default: can1-default {
831		mux {
832			function = "can1";
833			groups = "can1_6_grp";
834		};
835
836		conf {
837			groups = "can1_6_grp";
838			slew-rate = <SLEW_RATE_SLOW>;
839			power-source = <IO_STANDARD_LVCMOS18>;
840		};
841
842		conf-rx {
843			pins = "MIO25";
844			bias-high-impedance;
845		};
846
847		conf-tx {
848			pins = "MIO24";
849			bias-disable;
850		};
851	};
852
853	pinctrl_sdhci1_default: sdhci1-default {
854		mux {
855			groups = "sdio1_0_grp";
856			function = "sdio1";
857		};
858
859		conf {
860			groups = "sdio1_0_grp";
861			slew-rate = <SLEW_RATE_SLOW>;
862			power-source = <IO_STANDARD_LVCMOS18>;
863			bias-disable;
864		};
865
866		mux-cd {
867			groups = "sdio1_cd_0_grp";
868			function = "sdio1_cd";
869		};
870
871		conf-cd {
872			groups = "sdio1_cd_0_grp";
873			bias-high-impedance;
874			bias-pull-up;
875			slew-rate = <SLEW_RATE_SLOW>;
876			power-source = <IO_STANDARD_LVCMOS18>;
877		};
878
879		mux-wp {
880			groups = "sdio1_wp_0_grp";
881			function = "sdio1_wp";
882		};
883
884		conf-wp {
885			groups = "sdio1_wp_0_grp";
886			bias-high-impedance;
887			bias-pull-up;
888			slew-rate = <SLEW_RATE_SLOW>;
889			power-source = <IO_STANDARD_LVCMOS18>;
890		};
891	};
892
893	pinctrl_gpio_default: gpio-default {
894		mux-sw {
895			function = "gpio0";
896			groups = "gpio0_22_grp", "gpio0_23_grp";
897		};
898
899		conf-sw {
900			groups = "gpio0_22_grp", "gpio0_23_grp";
901			slew-rate = <SLEW_RATE_SLOW>;
902			power-source = <IO_STANDARD_LVCMOS18>;
903		};
904
905		mux-msp {
906			function = "gpio0";
907			groups = "gpio0_13_grp", "gpio0_38_grp";
908		};
909
910		conf-msp {
911			groups = "gpio0_13_grp", "gpio0_38_grp";
912			slew-rate = <SLEW_RATE_SLOW>;
913			power-source = <IO_STANDARD_LVCMOS18>;
914		};
915
916		conf-pull-up {
917			pins = "MIO22", "MIO23";
918			bias-pull-up;
919		};
920
921		conf-pull-none {
922			pins = "MIO13", "MIO38";
923			bias-disable;
924		};
925	};
926};
927
928&pcie {
929	status = "okay";
930};
931
932&psgtr {
933	status = "okay";
934	/* pcie, sata, usb3, dp */
935	clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
936	clock-names = "ref0", "ref1", "ref2", "ref3";
937};
938
939&qspi {
940	status = "okay";
941	flash@0 {
942		compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
943		#address-cells = <1>;
944		#size-cells = <1>;
945		reg = <0x0>;
946		spi-tx-bus-width = <1>;
947		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
948		spi-max-frequency = <108000000>; /* Based on DC1 spec */
949	};
950};
951
952&rtc {
953	status = "okay";
954};
955
956&sata {
957	status = "okay";
958	/* SATA OOB timing settings */
959	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
960	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
961	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
962	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
963	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
964	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
965	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
966	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
967	phy-names = "sata-phy";
968	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
969};
970
971/* SD1 with level shifter */
972&sdhci1 {
973	status = "okay";
974	/*
975	 * 1.0 revision has level shifter and this property should be
976	 * removed for supporting UHS mode
977	 */
978	no-1-8-v;
979	pinctrl-names = "default";
980	pinctrl-0 = <&pinctrl_sdhci1_default>;
981	xlnx,mio-bank = <1>;
982};
983
984&uart0 {
985	status = "okay";
986	pinctrl-names = "default";
987	pinctrl-0 = <&pinctrl_uart0_default>;
988};
989
990&uart1 {
991	status = "okay";
992	pinctrl-names = "default";
993	pinctrl-0 = <&pinctrl_uart1_default>;
994};
995
996/* ULPI SMSC USB3320 */
997&usb0 {
998	status = "okay";
999	pinctrl-names = "default";
1000	pinctrl-0 = <&pinctrl_usb0_default>;
1001	phy-names = "usb3-phy";
1002	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
1003};
1004
1005&dwc3_0 {
1006	status = "okay";
1007	dr_mode = "host";
1008	snps,usb3_lpm_capable;
1009	maximum-speed = "super-speed";
1010};
1011
1012&watchdog0 {
1013	status = "okay";
1014};
1015
1016&zynqmp_dpdma {
1017	status = "okay";
1018};
1019
1020&zynqmp_dpsub {
1021	status = "okay";
1022	phy-names = "dp-phy0";
1023	phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
1024};
1025